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Beslan
2026-06-01 20:15:04 +03:00
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TESTS/mbed_hal/qspi/flash_configs/MT25Q_config.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_MT25Q_H
#define MBED_QSPI_FLASH_MT25Q_H
#define QSPI_FLASH_CHIP_STRING "Micron MT25Q"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_RDCR0 0xB5
// Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_RDCR1 0x85
// Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_RDCR2 0x65
// Command for writing status register
#define QSPI_CMD_WRSR 0x01
// Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_WRCR0 0xB1
// Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_WRCR1 0x81
// Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_WRCR2 0x61
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 9200 // 8ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_1I2O 0xA2 // 1-1-2 mode
#define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
#define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode
#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
#define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
#define QSPI_CMD_WRITE_QPI 0x38 // 4-4-4 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 2070 // 1.8ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 4096 // for 128Mb chip
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0 // 1-1-1 mode
#define QSPI_READ_FAST_DUMMY_CYCLE 8 // 1-1-1 mode
#define QSPI_READ_1I2O_DUMMY_CYCLE 8 // 1-1-2 mode
#define QSPI_READ_2IO_DUMMY_CYCLE 8 // 1-2-2 mode
#define QSPI_READ_DPI_DUMMY_CYCLE 8 // 2-2-2 mode
#define QSPI_READ_1I4O_DUMMY_CYCLE 8 // 1-1-4 mode
#define QSPI_READ_4IO_DUMMY_CYCLE 10 // 1-4-4 mode
#define QSPI_READ_QPI_DUMMY_CYCLE 10 // 4-4-4 mode
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 460000 // 0.4s
#define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 1150000 // 1s
// max frequency for basic rw operation
#define QSPI_COMMON_MAX_FREQUENCY 50000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 2
#define QSPI_CONFIG_REG_1_SIZE 1
#define QSPI_CONFIG_REG_2_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) // Block protect
#define STATUS_BIT_BP1 (1 << 3) // Block protect
#define STATUS_BIT_BP2 (1 << 4) // Block protect
#define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom
#define STATUS_BIT_BP3 (1 << 6) // Block protect
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0 (Nonvolatile Configuration Register)
// bit 0, 1 reserved
#define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled
#define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled
#define CONFIG0_BIT_RH (1 << 4) // Reset/hold
#define CONFIG0_BIT_DTR (1 << 5) // Double transfer rate protocol
#define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength
#define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength
#define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength
#define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset
#define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset
#define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset
#define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle
#define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle
#define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle
#define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle
// configuration register 1 (Volatile Configuration Register)
// bit 2, reserved
#define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap
#define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap
#define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default)
#define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles
#define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles
#define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles
#define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles
// configuration register 2 (Enhanced Volatile Configuration Register)
// bit 3, reserved
#define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default)
#define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength
#define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength
#define CONFIG2_BIT_RH (1 << 4) // Reset/hold
#define CONFIG2_BIT_DTR (1 << 5) // Double transfer rate protocol
#define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
#define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
#define DUAL_ENABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define DUAL_DISABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_ENABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_DISABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_MT25Q_H

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TESTS/mbed_hal/qspi/flash_configs/MX25L51245G_config.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_MX25L51245G_H
#define MBED_QSPI_FLASH_MX25L51245G_H
#define QSPI_FLASH_CHIP_STRING "macronix MX25L51245G"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x15
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 2048 //
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4
#define QSPI_READ_1I2O_DUMMY_CYCLE 8
#define QSPI_READ_4IO_DUMMY_CYCLE 6
#define QSPI_READ_1I4O_DUMMY_CYCLE 8
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
#define QSPI_ERASE_BLOCK_32_MAX_TIME 1200000 // 1s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 32000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 2
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#define STATUS_BIT_QE (1 << 6) // Quad Enable
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0
// bit 0, 1, 2, 4, 5, 7 reserved
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
#endif // MBED_QSPI_FLASH_MX25L51245G_H

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TESTS/mbed_hal/qspi/flash_configs/MX25LM51245G_config.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_MX25LM51245G_H
#define MBED_QSPI_FLASH_MX25LM51245G_H
#define QSPI_FLASH_CHIP_STRING "macronix MX25LM51245G"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x15
#define QSPI_CMD_RDCR1 0x71
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
// Only single/octal mode supported with this memory
// So only single 1-1-1 mode in this QSPI config
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 131072 // 512MB / QSPI_SECTOR_SIZE
// Commands for reading
// Only single/octal mode supported with this memory
// So only single 1-1-1 mode in this QSPI config
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
//#define QSPI_CMD_ERASE_BLOCK_32 // not supported
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
#define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 66000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 1
#define QSPI_CONFIG_REG_1_SIZE 12
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 12
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#endif // MBED_QSPI_FLASH_MX25LM51245G_H

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TESTS/mbed_hal/qspi/flash_configs/MX25RXX35F_config.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_MX25RXX35F_H
#define MBED_QSPI_FLASH_MX25RXX35F_H
#define QSPI_FLASH_CHIP_STRING "macronix MX25RXX35F"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x15
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 32 // adjusted to MX25R1035F smallest one from MX25RXX35F family
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4
#define QSPI_READ_1I2O_DUMMY_CYCLE 8
#define QSPI_READ_4IO_DUMMY_CYCLE 6
#define QSPI_READ_1I4O_DUMMY_CYCLE 8
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 32000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 2
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#define STATUS_BIT_QE (1 << 6) // Quad Enable
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0
// bit 0, 1, 2, 4, 5, 7 reserved
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
#define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
// configuration register 1
// bit 0, 2, 3, 4, 5, 6, 7 reserved
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
#define EXTENDED_SPI_ENABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = STATUS_BIT_QE; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define EXTENDED_SPI_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] &= ~(STATUS_BIT_QE); \
\
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define FAST_MODE_ENABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size]; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[2] |= CONFIG1_BIT_LH; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
if (read_register(CONFIG_REG0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[1] & CONFIG1_BIT_LH) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define FAST_MODE_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size]; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[2] &= ~(CONFIG1_BIT_LH); \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
if (read_register(CONFIG_REG0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[1] & CONFIG1_BIT_LH) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_MX25RXX35F_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_N25Q128A_H
#define MBED_QSPI_FLASH_N25Q128A_H
#define QSPI_FLASH_CHIP_STRING "Micron N25Q128A"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_RDCR0 0xB5
// Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_RDCR1 0x85
// Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_RDCR2 0x65
// Command for writing status
#define QSPI_CMD_WRSR 0x01
// Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_WRCR0 0xB1
// Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_WRCR1 0x81
// Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
#define QSPI_CMD_WRCR2 0x61
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 9200 // 8ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
#define QSPI_CMD_WRITE_4IO 0x12 // 1-4-4 mode
#define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
#define QSPI_CMD_WRITE_QPI 0x12 // 4-4-4 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 5750 // 5ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 4096
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
// 8 dummy (10 dummy when quad SPI protocol is enabled)
#define QSPI_READ_2IO_DUMMY_CYCLE 8
#define QSPI_READ_1I2O_DUMMY_CYCLE 8
#define QSPI_READ_4IO_DUMMY_CYCLE 10
#define QSPI_READ_1I4O_DUMMY_CYCLE 8
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 920000 // 0.8s
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3000000 // 3s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 3500000 // 3.5s
// max frequency for basic rw operation
#define QSPI_COMMON_MAX_FREQUENCY 50000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 2
#define QSPI_CONFIG_REG_1_SIZE 1
#define QSPI_CONFIG_REG_2_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) // block
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom
#define STATUS_BIT_BP3 (1 << 6) //
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0 (Nonvolatile Configuration Register)
// bit 1, 5, reserved
#define CONFIG0_BIT_LOCK (1 << 0) // Lock nonvolatile configuration register
#define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled
#define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled
#define CONFIG0_BIT_RH (1 << 4) // Reset/hold
#define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength
#define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength
#define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength
#define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset
#define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset
#define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset
#define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle
#define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle
#define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle
#define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle
#define CONFIG0_BITS_DEFAULT 0xFFFF // reg default state
// configuration register 1 (Volatile Configuration Register)
// bit 2, reserved
#define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap
#define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap
#define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default)
#define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles
#define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles
#define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles
#define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles
#define CONFIG1_BITS_DEFAULT 0xB // reg default state
// configuration register 2 (Enhanced Volatile Configuration Register)
// bit 5, reserved
#define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default)
#define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength
#define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength
#define CONFIG2_BIT_VPP (1 << 3) // VPP accelerator 1 = Disabled (Default)
#define CONFIG2_BIT_RH (1 << 4) // Reset/hold
#define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
#define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
#define CONFIG2_BITS_DEFAULT 0xDF // reg default state
#define DUAL_ENABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define DUAL_DISABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_ENABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_DISABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
if (write_register(QSPI_CMD_WRCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
if (read_register(QSPI_CMD_RDCR2, reg_data, \
QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_N25Q128A_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../W25Q32JV_config.h"
// NRF doesn't uses read/write opcodes, instead it uses commands id's.
// Before sending it to H/W opcodes are mapped to id's in Mbed hal qspi implementation
//
// for more details see:
// targets\TARGET_NORDIC\TARGET_NRF5x\TARGET_SDK_15_0\modules\nrfx\mdk\nrf52840_bitfields.h
// targets\TARGET_NORDIC\TARGET_NRF5x\qspi_api.c
// NRF doesn't support read 1IO (opcode 0x03)
#undef QSPI_CMD_READ_1IO
#define QSPI_CMD_READ_1IO QSPI_CMD_READ_1IO_FAST
#ifdef QSPI_SECTOR_COUNT
#undef QSPI_SECTOR_COUNT
#define QSPI_SECTOR_COUNT 1024 // for W25Q32JV
#endif
#endif // MBED_QSPI_FLASH_CONFIG_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MX25RXX35F_config.h"
// NRF doesn't uses read/write opcodes, instead it uses commands id's.
// Before sending it to H/W opcodes are mapped to id's in Mbed hal qspi implementation
//
// for more details see:
// targets\TARGET_NORDIC\TARGET_NRF5x\TARGET_SDK_14_2\device\nrf52840_bitfields.h
// targets\TARGET_NORDIC\TARGET_NRF5x\qspi_api.c
// NRF doesn't support read 1IO (opcode 0x03)
#undef QSPI_CMD_READ_1IO
#define QSPI_CMD_READ_1IO QSPI_CMD_READ_1IO_FAST
#ifdef QSPI_SECTOR_COUNT
#undef QSPI_SECTOR_COUNT
#define QSPI_SECTOR_COUNT 2048 // for MX25R6435F
#endif
#endif // MBED_QSPI_FLASH_CONFIG_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MX25RXX35F_config.h"
/* Fast mode not supported in MX25U3235F */
#undef FAST_MODE_ENABLE
#undef FAST_MODE_DISABLE
#ifdef QSPI_SECTOR_COUNT
#undef QSPI_SECTOR_COUNT
#define QSPI_SECTOR_COUNT 1024 // for MX25U3235F
#endif
/* The values for MX25U3235F are different, specify this here */
#undef QSPI_COMMON_MAX_FREQUENCY
#undef QSPI_WRSR_MAX_TIME
#undef QSPI_PAGE_PROG_MAX_TIME
#undef QSPI_ERASE_SECTOR_MAX_TIME
#undef QSPI_ERASE_BLOCK_32_MAX_TIME
#undef QSPI_ERASE_BLOCK_64_MAX_TIME
/* Implementation of these macros are slightly different for MX25U3235F */
#undef EXTENDED_SPI_ENABLE
#undef EXTENDED_SPI_DISABLE
/* Max frequency for basic rw operation in MX25U3235F */
#define QSPI_COMMON_MAX_FREQUENCY 54000000
/* WRSR operations max time [us] (datasheet max time + 15%) */
#define QSPI_WRSR_MAX_TIME 46000 // 40ms
/* Write operations max time [us] (datasheet max time + 15%) */
#define QSPI_PAGE_PROG_MAX_TIME 3450 // 3ms
/* erase operations max time [us] (datasheet max time + 15%) */
#define QSPI_ERASE_SECTOR_MAX_TIME 230000 // 200 ms
#define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 2300000 // 2s
#define EXTENDED_SPI_ENABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = STATUS_BIT_QE; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define EXTENDED_SPI_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] &= ~(STATUS_BIT_QE); \
\
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_CONFIG_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MT25Q_config.h"
#endif // MBED_QSPI_FLASH_CONFIG_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_S25FL128S_H
#define MBED_QSPI_FLASH_S25FL128S_H
#define QSPI_FLASH_CHIP_STRING "Cypress S25FL128S"
#define QSPI_FLASH_CYPRESS_S25FL128S
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x35 // To read Quad (QE) enable bit
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01 // To write Qual (QE) enable bit
// Command for reading status register
#define QSPI_CMD_RDSR 0x05 // To read WIP bit of status register 1
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0xF0 //0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 575000 // 575 ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100 ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode // 1-4-4 is not supported by S25FL512S
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 800 // 800 us
#define QSPI_PAGE_SIZE 512 // 512B
#define QSPI_SECTOR_SIZE 262144 // 256kB
#define QSPI_SECTOR_COUNT 64 // 16 MB
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode - dual I/O
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode - dual output
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode - quad I/O
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode - quad output
// Alt (mode) value for quad I/O read
#define QSPI_ALT_READ_4IO 0x01 // 1-4-4 mode only
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4 // dual I/O
#define QSPI_READ_1I2O_DUMMY_CYCLE 8 // dual output
#define QSPI_READ_4IO_DUMMY_CYCLE 6 // quad I/O - 2 cycles for Mode or Alt (4 bits per cycle x 2 cycles = 1 byte) + 4 dummy cycles
#define QSPI_READ_1I4O_DUMMY_CYCLE 8 // quad output
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0xD8 // 256kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 750000 // 1.15*650 ~ 750 ms
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 50000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 1
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#define STATUS_BIT_QE (1 << 1) // Quad Enable
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0
// bit 0, 1, 2, 4, 5, 7 reserved
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
#define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
// configuration register 1
// bit 0, 2, 3, 4, 5, 6, 7 reserved
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
#define EXTENDED_SPI_ENABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[1] |= STATUS_BIT_QE; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
if (read_register(CONFIG_REG0, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define EXTENDED_SPI_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[1] &= ~(STATUS_BIT_QE); \
\
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
if (read_register(CONFIG_REG0, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_S25FL128S_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_S25FL512S_H
#define MBED_QSPI_FLASH_S25FL512S_H
#define QSPI_FLASH_CHIP_STRING "Cypress S25FL512S"
#define QSPI_FLASH_CYPRESS_S25FL512S
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x35 // To read Quad (QE) enable bit
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01 // To write Qual (QE) enable bit
// Command for reading status register
#define QSPI_CMD_RDSR 0x05 // To read WIP bit of status register 1
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0xF0 //0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 2300000 // 2.3 seconds
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode // 1-4-4 is not supported by S25FL512S
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 1500 // 1.5ms
#define QSPI_PAGE_SIZE 512 // 512B
#define QSPI_SECTOR_SIZE 262144 // 256kB
#define QSPI_SECTOR_COUNT 256 // 64 MB
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode - dual I/O
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode - dual output
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode - quad I/O
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode - quad output
// Alt (mode) value for quad I/O read
#define QSPI_ALT_READ_4IO 0x01 // 1-4-4 mode only
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4 // dual I/O
#define QSPI_READ_1I2O_DUMMY_CYCLE 8 // dual output
#define QSPI_READ_4IO_DUMMY_CYCLE 6 // quad I/O - 2 cycles for Mode or Alt (4 bits per cycle x 2 cycles = 1 byte) + 4 dummy cycles
#define QSPI_READ_1I4O_DUMMY_CYCLE 8 // quad output
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0xD8 // 256kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 2990000 // 1.15*2600 ~ 2900 ms
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 50000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 1
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#define STATUS_BIT_QE (1 << 1) // Quad Enable
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0
// bit 0, 1, 2, 4, 5, 7 reserved
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
#define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
// configuration register 1
// bit 0, 2, 3, 4, 5, 6, 7 reserved
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
#define EXTENDED_SPI_ENABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[1] |= STATUS_BIT_QE; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
if (read_register(CONFIG_REG0, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define EXTENDED_SPI_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[1] &= ~(STATUS_BIT_QE); \
\
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
if (read_register(CONFIG_REG0, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_S25FL512S_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_S25FS512S_H
#define MBED_QSPI_FLASH_S25FS512S_H
#define QSPI_FLASH_CHIP_STRING "Cypress S25FS512S"
#define QSPI_FLASH_CYPRESS_S25FS512S
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x35 // To read Quad (QE) enable bit
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01 // To write Qual (QE) enable bit
// Command for reading status register
#define QSPI_CMD_RDSR 0x05 // To read WIP bit of status register 1
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x2B
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0xF0 //0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 2300000 // 2.3 seconds
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
#define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode // 1-4-4 is not supported by S25FS512S
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 2300 // 2.3ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 262144 // 256kB
#define QSPI_SECTOR_COUNT 256 // 64 MB
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode - dual I/O
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode - dual output
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode - quad I/O
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode - quad output
// Alt (mode) value for quad I/O read
#define QSPI_ALT_READ_4IO 0x01 // 1-4-4 mode only
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4 // dual I/O
#define QSPI_READ_1I2O_DUMMY_CYCLE 8 // dual output
#define QSPI_READ_4IO_DUMMY_CYCLE 6 // quad I/O - 2 cycles for Mode or Alt (4 bits per cycle x 2 cycles = 1 byte) + 4 dummy cycles
#define QSPI_READ_1I4O_DUMMY_CYCLE 8 // quad output
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0xD8 // 256kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 850000 // 1.15*725 ~ 850 ms
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 50000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 1
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 2
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) //
#define STATUS_BIT_BP1 (1 << 3) //
#define STATUS_BIT_BP2 (1 << 4) //
#define STATUS_BIT_BP3 (1 << 5) //
#define STATUS_BIT_QE (1 << 1) // Quad Enable
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
// configuration register 0
// bit 0, 1, 2, 4, 5, 7 reserved
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
#define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
// configuration register 1
// bit 0, 2, 3, 4, 5, 6, 7 reserved
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
#define EXTENDED_SPI_ENABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[1] |= STATUS_BIT_QE; \
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
if (read_register(CONFIG_REG0, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define EXTENDED_SPI_DISABLE() \
\
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
uint8_t reg_data[reg_size] = { 0 }; \
\
if (read_register(STATUS_REG, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[1] &= ~(STATUS_BIT_QE); \
\
if (write_register(QSPI_CMD_WRSR, reg_data, \
reg_size, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
WAIT_FOR(WRSR_MAX_TIME, qspi); \
\
reg_data[0] = 0; \
if (read_register(CONFIG_REG0, reg_data, \
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_S25FS512S_H

29
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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_CONFIG_H
#define MBED_QSPI_FLASH_CONFIG_H
#include "../../MX25RXX35F_config.h"
#ifdef QSPI_SECTOR_COUNT
#undef QSPI_SECTOR_COUNT
#define QSPI_SECTOR_COUNT 1024 // for MX25R3235F
#endif
#define QSPI_MIN_FREQUENCY 2000000
#endif // MBED_QSPI_FLASH_CONFIG_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_FLASH_W25Q32JV_H
#define MBED_QSPI_FLASH_W25Q32JV_H
#define QSPI_FLASH_CHIP_STRING "Winbond W25Q32JV"
// Command for reading status register
#define QSPI_CMD_RDSR 0x05
// Command for reading configuration register
#define QSPI_CMD_RDCR0 0x35
#define QSPI_CMD_RDCR1 0x15
// Command for writing status/configuration register
#define QSPI_CMD_WRSR 0x01
// Command for writing configuration register
#define QSPI_CMD_WRCR0 0x31
#define QSPI_CMD_WRCR1 0x11
// Command for reading security register
#define QSPI_CMD_RDSCUR 0x48
// Command for setting Reset Enable
#define QSPI_CMD_RSTEN 0x66
// Command for setting Reset
#define QSPI_CMD_RST 0x99
// Command for setting write enable
#define QSPI_CMD_WREN 0x06
// Command for setting write disable
#define QSPI_CMD_WRDI 0x04
// WRSR operations max time [us] (datasheet max time + 15%)
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
// general wait max time [us]
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
// Commands for writing (page programming)
#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
// write operations max time [us] (datasheet max time + 15%)
#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
#define QSPI_PAGE_SIZE 256 // 256B
#define QSPI_SECTOR_SIZE 4096 // 4kB
#define QSPI_SECTOR_COUNT 1024
// Commands for reading
#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
#define QSPI_READ_1IO_DUMMY_CYCLE 0
#define QSPI_READ_FAST_DUMMY_CYCLE 8
#define QSPI_READ_2IO_DUMMY_CYCLE 4
#define QSPI_READ_1I2O_DUMMY_CYCLE 8
#define QSPI_READ_4IO_DUMMY_CYCLE 6
#define QSPI_READ_1I4O_DUMMY_CYCLE 8
// Commands for erasing
#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
// erase operations max time [us] (datasheet max time + 15%)
#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
// max frequency for basic rw operation (for fast mode)
#define QSPI_COMMON_MAX_FREQUENCY 32000000
#define QSPI_STATUS_REG_SIZE 1
#define QSPI_CONFIG_REG_0_SIZE 1
#define QSPI_CONFIG_REG_1_SIZE 1
#define QSPI_SECURITY_REG_SIZE 1
#define QSPI_MAX_REG_SIZE 1
// status register
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
#define STATUS_BIT_WEL (1 << 1) // write enable latch
#define STATUS_BIT_BP0 (1 << 2) // block protect 0
#define STATUS_BIT_BP1 (1 << 3) // block protect 1
#define STATUS_BIT_BP2 (1 << 4) // block protect 2
#define STATUS_BIT_BP_TB (1 << 5) // block protect top/bottom
#define STATUS_BIT_SP (1 << 6) // sector protect
#define STATUS_BIT_SRWD (1 << 7) // status register protect
// configuration register 0
// bit 2 reserved
#define CONFIG0_BIT_SRL (1 << 0) // status register lock
#define CONFIG0_BIT_QE (1 << 1) // quad enable
#define CONFIG0_BIT_LB1 (1 << 3) // security register lock 1
#define CONFIG0_BIT_LB2 (1 << 4) // security register lock 2
#define CONFIG0_BIT_LB3 (1 << 5) // security register lock 3
#define CONFIG0_BIT_CMP (1 << 6) // complement protect
#define CONFIG0_BIT_SUS (1 << 7) // suspend status
// configuration register 1
// bits 0, 1, 3, 4, 7 reserved
#define CONFIG1_BIT_WPS (1 << 2) // write protect selection
#define CONFIG1_BIT_DRV2 (1 << 5) // output driver strength 2
#define CONFIG1_BIT_DRV1 (1 << 6) // output driver strength 1
#define QUAD_ENABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_0_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
if (read_register(QSPI_CMD_RDCR0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] & ~(CONFIG0_BIT_QE); \
if (write_register(QSPI_CMD_WRCR0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
if (read_register(QSPI_CMD_RDCR0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & (CONFIG0_BIT_QE)) == 0 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#define QUAD_DISABLE() \
\
uint8_t reg_data[QSPI_CONFIG_REG_0_SIZE]; \
\
memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
if (read_register(QSPI_CMD_RDCR0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
if (write_enable(qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
reg_data[0] = reg_data[0] | (CONFIG0_BIT_QE); \
if (write_register(QSPI_CMD_WRCR0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
WAIT_FOR(WRSR_MAX_TIME, qspi); \
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
memset(reg_data, 0, QSPI_CONFIG_REG_0_SIZE); \
if (read_register(QSPI_CMD_RDCR0, reg_data, \
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
return QSPI_STATUS_ERROR; \
} \
\
return ((reg_data[0] & CONFIG0_BIT_QE) != 1 ? \
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
#endif // MBED_QSPI_FLASH_W25Q32JV_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FLASH_CONFIGS_H
#define MBED_FLASH_CONFIGS_H
#if defined(TARGET_MX25R6435F)
#include "MX25RXX35F_config.h"
#elif defined(TARGET_DISCO_L476VG)
#include "N25Q128A_config.h" // N25Q128A13EF840E
/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
#undef QSPI_CMD_READ_DPI
#undef QSPI_CMD_READ_QPI
#undef QSPI_CMD_WRITE_DPI
#undef QSPI_CMD_WRITE_QPI
#elif defined(TARGET_N25Q128A)
#include "N25Q128A_config.h"
#elif defined(TARGET_MX25L51245G)
#include "MX25L51245G_config.h"
#elif defined(TARGET_MX25LM51245G)
#include "MX25LM51245G_config.h"
#elif defined(TARGET_RHOMBIO_L476DMW1K)
#include "MT25Q_config.h" // MT25QL128ABA1EW7
/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
#undef QSPI_CMD_READ_DPI
#undef QSPI_CMD_READ_QPI
#undef QSPI_CMD_WRITE_DPI
#undef QSPI_CMD_WRITE_QPI
#elif defined(TARGET_NRF52840)
#if TARGET_EP_AGORA
#include "NORDIC/EP_AGORA/flash_config.h"
#else
#include "NORDIC/NRF52840_DK/flash_config.h"
#endif
#elif defined(TARGET_EFM32GG11_STK3701)
#include "SiliconLabs/EFM32GG11_STK3701/flash_config.h"
#elif defined(TARGET_K82F)
#include "NXP/K82F/flash_config.h"
#elif defined(TARGET_LPC546XX)
#include "NXP/LPC546XX/flash_config.h"
#elif( defined(TARGET_CY8CKIT_062_BLE) || \
defined(TARGET_CY8CKIT_062_WIFI_BT) || \
defined(TARGET_CY8CKIT_062S2_43012) || \
defined(TARGET_CY8CKIT_062S2_4343W) || \
defined(TARGET_CY8CKIT_064S2_4343W) || \
defined(TARGET_CY8CKIT_064B0S2_4343W) || \
defined(TARGET_CY8CPROTO_062_4343W) || \
defined(TARGET_CY8CPROTO_062S2_43012) || \
defined(TARGET_CY8CPROTO_062S3_4343W) || \
defined(TARGET_CYW9P62S1_43438EVB_01) || \
defined(TARGET_CYSBSYSKIT_01))
#include "S25FL512S_config.h"
#elif defined(TARGET_CYW9P62S1_43012EVB_01)
#include "S25FS512S_config.h"
#endif
#endif // MBED_FLASH_CONFIGS_H

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if !DEVICE_QSPI
#error [NOT_SUPPORTED] QSPI not supported for this target
#else
#include "utest/utest.h"
#include "unity/unity.h"
#include "greentea-client/test_env.h"
#include "qspi_test.h"
#include "qspi_test_utils.h"
#include "mbed.h"
#include "qspi_api.h"
#include "hal/us_ticker_api.h"
#if !defined(QSPI_FLASH_CHIP_STRING)
#error [NOT_SUPPORTED] QSPI test not supported for this target
#else
using namespace utest::v1;
// uncomment to enable verbose mode
//#define QSPI_TEST_LOG_DATA
//#define QSPI_TEST_LOG_FLASH_TIME
//#define QSPI_TEST_LOG_FLASH_STATUS
#ifndef QSPI_MIN_FREQUENCY
#define QSPI_MIN_FREQUENCY 1000000
#endif
// max write size is usually page size
#define DATA_SIZE_256 (QSPI_PAGE_SIZE)
#define DATA_SIZE_1024 (QSPI_PAGE_SIZE * 4)
uint8_t tx_buf[DATA_SIZE_1024];
uint8_t rx_buf[DATA_SIZE_1024];
// write address should be page aligned
#define TEST_FLASH_ADDRESS 0x0
#define TEST_REPEAT_SINGLE 1
#define TEST_REPEAT_MULTIPLE 4
// write block of data in single write operation
#define WRITE_SINGLE 1
// write block of data in adjacent locations in multiple write operations
#define WRITE_MULTIPLE 4
// read block of data in single read operation
#define READ_SINGLE 1
// read block of data in adjacent locations in multiple read operations
#define READ_MULTIPLE 4
// some target defines QSPI pins as integers thus conversion needed
#define QPIN_0 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO0)
#define QPIN_1 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO1)
#define QPIN_2 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO2)
#define QPIN_3 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO3)
#define QSCK static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_SCK)
#define QCSN static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_CSN)
static uint32_t gen_flash_address()
{
srand(ticker_read(get_us_ticker_data()));
uint32_t address = (((uint32_t)rand()) % QSPI_SECTOR_COUNT) * QSPI_SECTOR_SIZE;
address &= 0xFFFFFF; // Ensure address is within 24 bits so as to not have to deal with 4-byte addressing
return address;
}
static void log_data(const char *str, uint8_t *data, uint32_t size)
{
utest_printf("%s: ", str);
for (uint32_t j = 0; j < size; j++) {
utest_printf("%02X ", data[j]);
}
utest_printf("\r\n");
}
static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width, qspi_bus_width_t write_addr_width,
qspi_bus_width_t write_data_width, qspi_bus_width_t write_alt_width, uint32_t write_cmd,
qspi_address_size_t write_addr_size, qspi_alt_size_t write_alt_size,
uint32_t write_count, qspi_bus_width_t read_inst_width, qspi_bus_width_t read_addr_width,
qspi_bus_width_t read_data_width, qspi_bus_width_t read_alt_width, uint32_t read_cmd,
int read_dummy_cycles, qspi_address_size_t read_addr_size, qspi_alt_size_t read_alt_size,
uint32_t read_count, uint32_t test_count, uint32_t data_size,
uint32_t flash_addr)
{
qspi_status_t ret = QSPI_STATUS_OK;
Timer timer;
int erase_time = 0, write_time = 0, read_time = 0;
size_t buf_len = data_size;
for (uint32_t tc = 0; tc < test_count; tc++) {
srand(ticker_read(get_us_ticker_data()));
for (uint32_t i = 0; i < data_size; i++) {
tx_buf[i] = (uint8_t)(rand() & 0xFF);
}
ret = write_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
timer.reset();
timer.start();
ret = erase(SECTOR_ERASE, flash_addr, qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(SECTOR_ERASE_MAX_TIME, qspi);
timer.stop();
erase_time = timer.read_us();
// switching to extended-SPI/DPI/QPI mode here for write operation
// for DPI/QPI qspi.cmd is automatically switched to 2_2_2/4_4_4 mode
ret = mode_enable(qspi, write_inst_width, write_addr_width, write_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
const uint32_t write_size = data_size / write_count;
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size) {
ret = write_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
timer.reset();
timer.start();
buf_len = write_size;
qspi.cmd.configure(write_inst_width, write_addr_width, write_data_width, write_alt_width, write_addr_size, write_alt_size);
qspi.cmd.build(write_cmd, write_start);
ret = qspi_write(&qspi.handle, qspi.cmd.get(), tx_buf + wc * write_size, &buf_len);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
TEST_ASSERT_EQUAL(write_size, buf_len);
if (is_extended_mode(write_inst_width, write_addr_width, write_data_width)) {
// on some flash chips in extended-SPI mode, control commands works only in 1-1-1 mode
// so switching back to 1-1-1 mode
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
}
WAIT_FOR(PAGE_PROG_MAX_TIME, qspi);
timer.stop();
write_time = timer.read_us();
}
// switching back to single channel SPI
ret = mode_disable(qspi, write_inst_width, write_addr_width, write_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// switching to extended-SPI/DPI/QPI mode here for read operation
// for DPI/QPI qspi.cmd is automatically switched to 2_2_2/4_4_4 mode
ret = mode_enable(qspi, read_inst_width, read_addr_width, read_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
memset(rx_buf, 0, sizeof(rx_buf));
const uint32_t read_size = data_size / read_count;
qspi.cmd.configure(read_inst_width, read_addr_width, read_data_width, read_alt_width, read_addr_size, read_alt_size, read_dummy_cycles);
for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size) {
timer.reset();
timer.start();
buf_len = read_size;
qspi.cmd.build(read_cmd, read_start);
ret = qspi_read(&qspi.handle, qspi.cmd.get(), rx_buf + rc * read_size, &buf_len);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
TEST_ASSERT_EQUAL(read_size, buf_len);
timer.stop();
read_time = timer.read_us();
}
qspi.cmd.set_dummy_cycles(0);
if (is_extended_mode(read_inst_width, read_addr_width, read_data_width)) {
// on some flash chips in extended-SPI mode, control commands works only in 1-1-1 mode
// so switching back to 1-1-1 mode
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
}
// switching back to single channel SPI
ret = mode_disable(qspi, read_inst_width, read_addr_width, read_data_width);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
for (uint32_t i = 0; i < data_size; i++) {
if (tx_buf[i] != rx_buf[i]) {
log_data("tx data", tx_buf, data_size);
log_data("rx data", rx_buf, data_size);
utest_printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time);
TEST_ASSERT_EQUAL(tx_buf[i], rx_buf[i]);
}
}
#ifdef QSPI_TEST_LOG_FLASH_TIME
utest_printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time);
#endif
#ifdef QSPI_TEST_LOG_DATA
log_data("tx data", tx_buf, data_size);
log_data("rx data", rx_buf, data_size);
utest_printf("rx/tx data match\r\n");
#endif
}
}
template < qspi_bus_width_t write_inst_width,
qspi_bus_width_t write_addr_width,
qspi_bus_width_t write_data_width,
qspi_bus_width_t write_alt_width,
unsigned int write_cmd,
qspi_address_size_t write_addr_size,
qspi_alt_size_t write_alt_size,
uint32_t write_count,
qspi_bus_width_t read_inst_width,
qspi_bus_width_t read_addr_width,
qspi_bus_width_t read_data_width,
qspi_bus_width_t read_alt_width,
unsigned int read_cmd,
int read_dummy_cycles,
qspi_address_size_t read_addr_size,
qspi_alt_size_t read_alt_size,
int frequency,
uint32_t read_count,
uint32_t test_count,
uint32_t data_size,
uint32_t flash_addr>
void qspi_write_read_test(void)
{
qspi_status_t ret;
Qspi qspi;
uint32_t addr = flash_addr;
if (addr == 0) {
// if no specified address selected, use random one to extend flash life
addr = gen_flash_address();
}
qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
ret = qspi_frequency(&qspi.handle, frequency);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
// switch memory to high performance mode (if available)
ret = fast_mode_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
#ifdef QSPI_TEST_LOG_FLASH_STATUS
log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi, "Status register");
log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi, "Config register 0");
#ifdef CONFIG_REG1
log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi, "Config register 1");
#endif
#ifdef CONFIG_REG2
log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi, "Config register 2");
#endif
#endif
_qspi_write_read_test(qspi, write_inst_width, write_addr_width, write_data_width, write_alt_width, write_cmd,
write_addr_size, write_alt_size, write_count, read_inst_width,
read_addr_width, read_data_width, read_alt_width, read_cmd, read_dummy_cycles,
read_addr_size, read_alt_size, read_count, test_count,
data_size, addr);
ret = fast_mode_disable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi_free(&qspi.handle);
}
void qspi_init_free_test(void)
{
Qspi qspi;
qspi_status_t ret;
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_free(&qspi.handle);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_free(&qspi.handle);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_free(&qspi.handle);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, QSPI_COMMON_MAX_FREQUENCY, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
#ifdef QSPI_TEST_LOG_FLASH_STATUS
log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi, "Status register");
log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi, "Config register 0");
#ifdef CONFIG_REG1
log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi, "Config register 1");
#endif
#ifdef CONFIG_REG2
log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi, "Config register 2");
#endif
#endif
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
qspi_free(&qspi.handle);
}
void qspi_frequency_test(void)
{
Qspi qspi;
qspi_status_t ret;
int freq = QSPI_COMMON_MAX_FREQUENCY;
ret = qspi_init(&qspi.handle, QPIN_0, QPIN_1, QPIN_2, QPIN_3, QSCK, QCSN, freq, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
while (ret == QSPI_STATUS_OK && freq >= QSPI_MIN_FREQUENCY) {
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
ret = qspi_frequency(&qspi.handle, freq);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
utest_printf("frequency setting %d [Hz] - OK\r\n", freq);
freq /= 2;
}
qspi_free(&qspi.handle);
}
void qspi_memory_id_test()
{
utest_printf("*** %s memory config loaded ***\r\n", QSPI_FLASH_CHIP_STRING);
}
Case cases[] = {
Case("qspi memory id test", qspi_memory_id_test),
Case("qspi init/free test", qspi_init_free_test),
Case("qspi frequency setting test", qspi_frequency_test),
// read/x1 write/x1 - read/write block of data in single write/read operation
// read/x4 write/x4 - read/write block of data in adjacent locations in multiple write/read operations
// repeat/xN - test repeat count (new data pattern each time)
// 1-1-1 - single channel SPI
// 1-1-2 - Dual data (extended SPI)
// 1-2-2 - Dual I/O (extended SPI)
// 1-1-4 - Quad data (extended SPI)
// 1-4-4 - Quad I/O (extended SPI)
// 2-2-2 - DPI (multi-channel SPI)
// 4-4-4 - QPI (multi-channel SPI)
Case("qspi write(1-1-1)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_1_1_2
Case("qspi write(1-1-1)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_2_2
Case("qspi write(1-1-1)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_2_2_2
Case("qspi write(1-1-1)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_1_4
Case("qspi write(1-1-1)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_4_4
Case("qspi write(1-1-1)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_4_4_4
Case("qspi write(1-1-1)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-1)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef WRITE_1_2_2
Case("qspi write(1-2-2)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(1-2-2)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_1_4
Case("qspi write(1-2-2)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(1-2-2)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(1-2-2)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-2-2)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
#ifdef WRITE_2_2_2
Case("qspi write(2-2-2)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(2-2-2)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_1_4
Case("qspi write(2-2-2)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(2-2-2)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(2-2-2)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(2-2-2)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
#ifdef WRITE_1_1_4
Case("qspi write(1-1-4)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(1-1-4)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_1_4
Case("qspi write(1-1-4)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(1-1-4)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(1-1-4)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-1-4)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
#ifdef WRITE_1_4_4
Case("qspi write(1-4-4)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(1-4-4)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_1_4
Case("qspi write(1-4-4)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(1-4-4)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(1-4-4)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(1-4-4)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
#ifdef WRITE_4_4_4
Case("qspi write(4-4-4)/x1 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-1-1)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-1)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-1)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-1-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_2_2_2
Case("qspi write(4-4-4)/x1 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(2-2-2)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(2-2-2)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(2-2-2)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_2_2_2, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#ifdef READ_1_1_4
Case("qspi write(4-4-4)/x1 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-1-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-1-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_1_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
Case("qspi write(4-4-4)/x1 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(1-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(1-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_1_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#ifdef READ_4_4_4
Case("qspi write(4-4-4)/x1 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x4 read(4-4-4)/x1 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_MULTIPLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_1024, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(4-4-4)/x4 repeat/x1 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_MULTIPLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
Case("qspi write(4-4-4)/x1 read(4-4-4)/x1 repeat/x4 test", qspi_write_read_test<WRITE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, WRITE_SINGLE, READ_4_4_4, ADDR_SIZE_24, ALT_SIZE_8, QSPI_COMMON_MAX_FREQUENCY, READ_SINGLE, TEST_REPEAT_MULTIPLE, DATA_SIZE_256, TEST_FLASH_ADDRESS>),
#endif
#endif
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
{
GREENTEA_SETUP(180, "default_auto");
return greentea_test_setup_handler(number_of_cases);
}
Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
int main()
{
Harness::run(specification);
}
#endif // !defined(QSPI_FLASH_CHIP_STRING)
#endif // !DEVICE_QSPI

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** \addtogroup hal_qspi
* @{
* \defgroup hal_qspi_tests Tests
* QSPI tests of the HAL.
* @{
*/
#ifndef MBED_QSPI_TEST_H
#define MBED_QSPI_TEST_H
#include "qspi_api.h"
#include "qspi_test_utils.h"
#if DEVICE_QSPI
/** Test that qspi_init/qspi_free can be called multiple times.
*
* Given board provides QSPI.
* When qspi_init/qspi_free is called multiple times.
* Then qspi_init/qspi_free are successfully performed (no exception is generated).
*
*/
void qspi_init_free_test(void);
/** Test qspi frequency setting.
*
* Given board provides QSPI, with QSPI already initialized.
* When set QSPI frequency.
* Then freguency setting is successfully performed (no exception is generated).
*
*/
void qspi_frequency_test(void);
/** Template for write/read tests
*
* Test single write/read operation of a block of data to/from the specific memory address
* Given board provides QSPI, with QSPI already initialized.
* When perform write and then read operations.
* Then data is successfully written and then read (no exception is generated) and the read data is valid.
*
* Test multiple write/read operation of a block of data to/from the same specific memory address
* Given board provides QSPI, with QSPI already initialized.
* When perform write and then read operations.
* Then data is successfully written and then read (no exception is generated) and the read data is valid.
*
* Test multiple adjacent write and single read operation of a block of data to/from the specific memory address
* Given board provides QSPI, with QSPI already initialized.
* When perform write and then read operations.
* Then data is successfully written and then read (no exception is generated) and the read data is valid.
*
* Test single write and multiple adjacent read operation of a block of data to/from the specific memory address
* Given board provides QSPI, with QSPI already initialized.
* When perform write and then read operations.
* Then data is successfully written and then read (no exception is generated) and the read data is valid.
*
*/
template < qspi_bus_width_t write_inst_width,
qspi_bus_width_t write_addr_width,
qspi_bus_width_t write_data_width,
qspi_bus_width_t write_alt_width,
unsigned int write_cmd,
qspi_address_size_t write_addr_size,
qspi_alt_size_t write_alt_size,
uint32_t write_count,
qspi_bus_width_t read_inst_width,
qspi_bus_width_t read_addr_width,
qspi_bus_width_t read_data_width,
qspi_bus_width_t read_alt_width,
unsigned int read_cmd,
int read_dummy_cycles,
qspi_address_size_t read_addr_size,
qspi_alt_size_t read_alt_size,
int frequency,
uint32_t read_count,
uint32_t test_count,
uint32_t data_size,
uint32_t flash_addr>
void qspi_write_read_test(void);
#endif
#endif
/** @}*/
/** @}*/

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "utest/utest.h"
#include "hal/qspi_api.h"
#include "hal/us_ticker_api.h"
#include "qspi_test_utils.h"
#include "unity/unity.h"
#include <string.h> // for memset
#include "flash_configs/flash_configs.h"
#include "mbed.h"
static qspi_status_t extended_enable(Qspi &qspi);
static qspi_status_t extended_disable(Qspi &qspi);
static qspi_status_t dual_enable(Qspi &qspi);
static qspi_status_t dual_disable(Qspi &qspi);
static qspi_status_t quad_enable(Qspi &qspi);
static qspi_status_t quad_disable(Qspi &qspi);
void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width,
qspi_bus_width_t data_width, qspi_bus_width_t alt_width,
qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
int dummy_cycles)
{
memset(&_cmd, 0, sizeof(qspi_command_t));
_cmd.instruction.disabled = _cmd.address.disabled = _cmd.alt.disabled = true;
_cmd.instruction.bus_width = inst_width;
_cmd.address.bus_width = addr_width;
_cmd.address.size = addr_size;
_cmd.alt.bus_width = alt_width;
_cmd.alt.size = alt_size;
_cmd.data.bus_width = data_width;
_cmd.dummy_count = dummy_cycles;
}
void QspiCommand::set_dummy_cycles(int dummy_cycles)
{
_cmd.dummy_count = dummy_cycles;
}
void QspiCommand::build(int instruction, int address, int alt)
{
_cmd.instruction.disabled = (instruction == QSPI_NO_INST);
if (!_cmd.instruction.disabled) {
_cmd.instruction.value = instruction;
}
_cmd.address.disabled = (address == QSPI_NONE);
if (!_cmd.address.disabled) {
_cmd.address.value = address;
}
_cmd.alt.disabled = (alt == QSPI_NONE);
if (!_cmd.alt.disabled) {
_cmd.alt.value = alt;
}
}
qspi_command_t *QspiCommand::get()
{
return &_cmd;
}
qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q)
{
q.cmd.build(cmd);
return qspi_command_transfer(&q.handle, q.cmd.get(), NULL, 0, buf, size);
}
qspi_status_t write_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q)
{
q.cmd.build(cmd);
return qspi_command_transfer(&q.handle, q.cmd.get(), buf, size, NULL, 0);
}
QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi)
{
uint8_t reg[QSPI_STATUS_REG_SIZE];
qspi_status_t ret;
uint32_t curr_time;
const ticker_data_t *const ticker = get_us_ticker_data();
const uint32_t start = ticker_read(ticker);
memset(reg, 255, QSPI_STATUS_REG_SIZE);
do {
ret = read_register(STATUS_REG, reg, QSPI_STATUS_REG_SIZE, qspi);
curr_time = ticker_read(ticker);
} while (((reg[0] & STATUS_BIT_WIP) != 0) && ((curr_time - start) < time_us));
if (((reg[0] & STATUS_BIT_WIP) == 0) && (ret == QSPI_STATUS_OK)) {
return sOK;
} else if (ret != QSPI_STATUS_OK) {
return sError;
} else if ((curr_time - start) >= time_us) {
return sTimeout;
}
return sUnknown;
}
void flash_init(Qspi &qspi)
{
uint8_t status[QSPI_STATUS_REG_SIZE];
qspi_status_t ret;
qspi.cmd.build(QSPI_CMD_RDSR);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, status, QSPI_STATUS_REG_SIZE);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// Only do reset enable if device needs it
if (QSPI_CMD_RSTEN != 0) {
qspi.cmd.build(QSPI_CMD_RSTEN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
qspi.cmd.build(QSPI_CMD_RST);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WAIT_MAX_TIME, qspi);
// Zero out status register to attempt to clear block protection bits
uint8_t blanks[QSPI_STATUS_REG_SIZE] = {0};
qspi.cmd.build(QSPI_CMD_WREN);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
qspi.cmd.build(QSPI_CMD_WRSR);
ret = qspi_command_transfer(&qspi.handle, qspi.cmd.get(), blanks, 1, NULL, 0);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
qspi_status_t write_enable(Qspi &qspi)
{
uint8_t reg[QSPI_STATUS_REG_SIZE];
qspi.cmd.build(QSPI_CMD_WREN);
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0) != QSPI_STATUS_OK) {
return QSPI_STATUS_ERROR;
}
WAIT_FOR(WRSR_MAX_TIME, qspi);
memset(reg, 0, QSPI_STATUS_REG_SIZE);
if (read_register(STATUS_REG, reg, QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {
return QSPI_STATUS_ERROR;
}
return ((reg[0] & STATUS_BIT_WEL) != 0 ? QSPI_STATUS_OK : QSPI_STATUS_ERROR);
}
qspi_status_t write_disable(Qspi &qspi)
{
uint8_t reg[QSPI_STATUS_REG_SIZE];
qspi.cmd.build(QSPI_CMD_WRDI);
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0) != QSPI_STATUS_OK) {
return QSPI_STATUS_ERROR;
}
WAIT_FOR(WRSR_MAX_TIME, qspi);
memset(reg, 0, QSPI_STATUS_REG_SIZE);
if (read_register(STATUS_REG, reg, QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) {
return QSPI_STATUS_ERROR;
}
return ((reg[0] & STATUS_BIT_WEL) == 0 ? QSPI_STATUS_OK : QSPI_STATUS_ERROR);
}
void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str)
{
qspi_status_t ret;
static uint8_t reg[QSPI_MAX_REG_SIZE];
ret = read_register(cmd, reg, reg_size, qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
for (uint32_t j = 0; j < reg_size; j++) {
utest_printf("%s byte %u (MSB first): ", str != NULL ? str : "", j);
for (int i = 0; i < 8; i++) {
utest_printf("%s ", ((reg[j] & (1 << (7 - i))) & 0xFF) == 0 ? "0" : "1");
}
utest_printf("\r\n");
}
}
qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi)
{
qspi.cmd.build(erase_cmd, flash_addr);
return qspi_command_transfer(&qspi.handle, qspi.cmd.get(), NULL, 0, NULL, 0);
}
qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
if (is_extended_mode(inst_width, addr_width, data_width)) {
return extended_enable(qspi);
} else if (is_dual_mode(inst_width, addr_width, data_width)) {
return dual_enable(qspi);
} else if (is_quad_mode(inst_width, addr_width, data_width)) {
return quad_enable(qspi);
} else {
return QSPI_STATUS_OK;
}
}
qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
if (is_extended_mode(inst_width, addr_width, data_width)) {
return extended_disable(qspi);
} else if (is_dual_mode(inst_width, addr_width, data_width)) {
return dual_disable(qspi);
} else if (is_quad_mode(inst_width, addr_width, data_width)) {
return quad_disable(qspi);
} else {
return QSPI_STATUS_OK;
}
}
static qspi_status_t extended_enable(Qspi &qspi)
{
#ifdef EXTENDED_SPI_ENABLE
EXTENDED_SPI_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t extended_disable(Qspi &qspi)
{
#ifdef EXTENDED_SPI_DISABLE
EXTENDED_SPI_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t dual_enable(Qspi &qspi)
{
#ifdef DUAL_ENABLE
DUAL_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t dual_disable(Qspi &qspi)
{
#ifdef DUAL_DISABLE
DUAL_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t quad_enable(Qspi &qspi)
{
#ifdef QUAD_ENABLE
QUAD_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
static qspi_status_t quad_disable(Qspi &qspi)
{
#ifdef QUAD_DISABLE
QUAD_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
qspi_status_t fast_mode_enable(Qspi &qspi)
{
#ifdef FAST_MODE_ENABLE
FAST_MODE_ENABLE();
#else
return QSPI_STATUS_OK;
#endif
}
qspi_status_t fast_mode_disable(Qspi &qspi)
{
#ifdef FAST_MODE_DISABLE
FAST_MODE_DISABLE();
#else
return QSPI_STATUS_OK;
#endif
}
bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
return (inst_width == QSPI_CFG_BUS_SINGLE) && ((addr_width != QSPI_CFG_BUS_SINGLE) || (data_width != QSPI_CFG_BUS_SINGLE));
}
bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
return (inst_width == QSPI_CFG_BUS_DUAL) && (addr_width == QSPI_CFG_BUS_DUAL) && (data_width == QSPI_CFG_BUS_DUAL);
}
bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)
{
return (inst_width == QSPI_CFG_BUS_QUAD) && (addr_width == QSPI_CFG_BUS_QUAD) && (data_width == QSPI_CFG_BUS_QUAD);
}

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/* mbed Microcontroller Library
* Copyright (c) 2018-2018 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_QSPI_TEST_UTILS_H
#define MBED_QSPI_TEST_UTILS_H
#include "flash_configs/flash_configs.h"
#include "unity/unity.h"
#define QSPI_NONE (-1)
enum QspiStatus {
sOK,
sError,
sTimeout,
sUnknown
};
class QspiCommand {
public:
void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
int dummy_cycles = 0);
void set_dummy_cycles(int dummy_cycles);
void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
qspi_command_t *get();
private:
qspi_command_t _cmd;
};
struct Qspi {
qspi_t handle;
QspiCommand cmd;
};
// MODE_Command_Address_Data_Alt
#define MODE_1_1_1 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
#define MODE_1_1_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
#define MODE_1_2_2 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
#define MODE_2_2_2 QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_DUAL
#define MODE_1_1_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
#define MODE_1_4_4 QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
#define MODE_4_4_4 QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD, QSPI_CFG_BUS_QUAD
#define WRITE_1_1_1 MODE_1_1_1, QSPI_CMD_WRITE_1IO
#ifdef QSPI_CMD_WRITE_2IO
#define WRITE_1_2_2 MODE_1_2_2, QSPI_CMD_WRITE_2IO
#endif
#ifdef QSPI_CMD_WRITE_1I4O // Quad page program - command: 0x32
#define WRITE_1_1_4 MODE_1_1_4, QSPI_CMD_WRITE_1I4O
#endif
#ifdef QSPI_CMD_WRITE_4IO
#define WRITE_1_4_4 MODE_1_4_4, QSPI_CMD_WRITE_4IO
#endif
#ifdef QSPI_CMD_WRITE_DPI
#define WRITE_2_2_2 MODE_2_2_2, QSPI_CMD_WRITE_DPI
#endif
#ifdef QSPI_CMD_WRITE_QPI
#define WRITE_4_4_4 MODE_4_4_4, QSPI_CMD_WRITE_QPI
#endif
#define READ_1_1_1 MODE_1_1_1, QSPI_CMD_READ_1IO, QSPI_READ_1IO_DUMMY_CYCLE
#ifdef QSPI_CMD_READ_1I2O
#define READ_1_1_2 MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
#endif
#ifdef QSPI_CMD_READ_2IO
#define READ_1_2_2 MODE_1_2_2, QSPI_CMD_READ_2IO, QSPI_READ_2IO_DUMMY_CYCLE
#endif
#ifdef QSPI_CMD_READ_1I4O
#define READ_1_1_4 MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
#endif
#ifdef QSPI_CMD_READ_4IO
#define READ_1_4_4 MODE_1_4_4, QSPI_CMD_READ_4IO, QSPI_READ_4IO_DUMMY_CYCLE
#endif
#ifdef QSPI_CMD_READ_DPI
#define READ_2_2_2 MODE_2_2_2, QSPI_CMD_READ_DPI, QSPI_READ_2IO_DUMMY_CYCLE
#endif
#ifdef QSPI_CMD_READ_QPI
#define READ_4_4_4 MODE_4_4_4, QSPI_CMD_READ_QPI, QSPI_READ_4IO_DUMMY_CYCLE
#endif
#define ADDR_SIZE_8 QSPI_CFG_ADDR_SIZE_8
#define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
#define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
#define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
#define ALT_SIZE_8 QSPI_CFG_ALT_SIZE_8
#define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
#define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
#define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
#define STATUS_REG QSPI_CMD_RDSR
#define CONFIG_REG0 QSPI_CMD_RDCR0
#ifdef QSPI_CMD_RDCR1
#define CONFIG_REG1 QSPI_CMD_RDCR1
#endif
#ifdef QSPI_CMD_RDCR2
#define CONFIG_REG2 QSPI_CMD_RDCR2
#endif
#define SECURITY_REG QSPI_CMD_RDSCUR
#ifndef QSPI_CONFIG_REG_1_SIZE
#define QSPI_CONFIG_REG_1_SIZE 0
#endif
#ifndef QSPI_CONFIG_REG_2_SIZE
#define QSPI_CONFIG_REG_2_SIZE 0
#endif
#define SECTOR_ERASE QSPI_CMD_ERASE_SECTOR
#define BLOCK_ERASE QSPI_CMD_ERASE_BLOCK_64
#define SECTOR_ERASE_MAX_TIME QSPI_ERASE_SECTOR_MAX_TIME
#define BLOCK32_ERASE_MAX_TIME QSPI_ERASE_BLOCK_32_MAX_TIME
#define BLOCK64_ERASE_MAX_TIME QSPI_ERASE_BLOCK_64_MAX_TIME
#define PAGE_PROG_MAX_TIME QSPI_PAGE_PROG_MAX_TIME
#define WRSR_MAX_TIME QSPI_WRSR_MAX_TIME
#define WAIT_MAX_TIME QSPI_WAIT_MAX_TIME
qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
qspi_status_t write_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi);
void flash_init(Qspi &qspi);
qspi_status_t write_enable(Qspi &qspi);
qspi_status_t write_disable(Qspi &qspi);
void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
qspi_status_t fast_mode_enable(Qspi &qspi);
qspi_status_t fast_mode_disable(Qspi &qspi);
qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);
bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
#define WAIT_FOR(timeout, q) TEST_ASSERT_EQUAL_MESSAGE(sOK, flash_wait_for(timeout, q), "flash_wait_for failed!!!")
#endif // MBED_QSPI_TEST_UTILS_H