Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
@@ -0,0 +1,298 @@
|
||||
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
|
||||
; The first line specifies a preprocessor command that the linker invokes
|
||||
; to pass a scatter file through a C preprocessor.
|
||||
|
||||
;*******************************************************************************
|
||||
;* \file cy8c6xxa_cm4_dual.sct
|
||||
;* \version 2.60
|
||||
;*
|
||||
;* Linker file for the ARMCC.
|
||||
;*
|
||||
;* The main purpose of the linker script is to describe how the sections in the
|
||||
;* input files should be mapped into the output file, and to control the memory
|
||||
;* layout of the output file.
|
||||
;*
|
||||
;* \note The entry point location is fixed and starts at 0x10000000. The valid
|
||||
;* application image should be placed there.
|
||||
;*
|
||||
;* \note The linker files included with the PDL template projects must be
|
||||
;* generic and handle all common use cases. Your project may not use every
|
||||
;* section defined in the linker files. In that case you may see the warnings
|
||||
;* during the build process: L6314W (no section matches pattern) and/or L6329W
|
||||
;* (pattern only matches removed unused sections). In your project, you can
|
||||
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
|
||||
;* the linker, simply comment out or remove the relevant code in the linker
|
||||
;* file.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* \copyright
|
||||
;* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
;* SPDX-License-Identifier: Apache-2.0
|
||||
;*
|
||||
;* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
;* you may not use this file except in compliance with the License.
|
||||
;* You may obtain a copy of the License at
|
||||
;*
|
||||
;* http://www.apache.org/licenses/LICENSE-2.0
|
||||
;*
|
||||
;* Unless required by applicable law or agreed to in writing, software
|
||||
;* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
;* See the License for the specific language governing permissions and
|
||||
;* limitations under the License.
|
||||
;******************************************************************************/
|
||||
|
||||
#if !defined(MBED_ROM_START)
|
||||
#define MBED_ROM_START 0x10180000
|
||||
#endif
|
||||
|
||||
;* MBED_APP_START is being used by the bootloader build script and
|
||||
;* will be calculate by the system. In case if MBED_APP_START address is
|
||||
;* customized by the bootloader config, the application image should not
|
||||
;* include CM0p prebuilt image.
|
||||
;*
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START (MBED_ROM_START)
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_ROM_SIZE)
|
||||
#define MBED_ROM_SIZE 0x80000
|
||||
#endif
|
||||
|
||||
;* MBED_APP_SIZE is being used by the bootloader build script and
|
||||
;* will be calculate by the system.
|
||||
;*
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE (MBED_ROM_SIZE)
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_START)
|
||||
#define MBED_RAM_START 0x08080000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_SIZE)
|
||||
#define MBED_RAM_SIZE 0x7F800
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
; Size of the stack section at the end of CM4 SRAM
|
||||
#define STACK_SIZE MBED_BOOT_STACK_SIZE
|
||||
|
||||
; The defines below describe the location and size of blocks of memory in the target.
|
||||
; Use these defines to specify the memory regions available for allocation.
|
||||
|
||||
; The following defines control RAM and flash memory allocation for the CM4 core.
|
||||
; You can change the memory allocation by editing RAM and Flash defines.
|
||||
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
|
||||
; Using this memory region for other purposes will lead to unexpected behavior.
|
||||
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
|
||||
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
|
||||
; RAM
|
||||
#define RAM_START MBED_RAM_START
|
||||
#define RAM_SIZE MBED_RAM_SIZE
|
||||
; Flash
|
||||
#define FLASH_START MBED_APP_START
|
||||
#define FLASH_SIZE MBED_APP_SIZE
|
||||
|
||||
; The following defines describe a 32K flash region used for EEPROM emulation.
|
||||
; This region can also be used as the general purpose flash.
|
||||
; You can assign sections to this memory region for only one of the cores.
|
||||
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
|
||||
; Therefore, repurposing this memory region will prevent such middleware from operation.
|
||||
#define EM_EEPROM_START 0x14000000
|
||||
#define EM_EEPROM_SIZE 0x8000
|
||||
|
||||
; The following defines describe device specific memory regions and must not be changed.
|
||||
; Supervisory flash: User data
|
||||
#define SFLASH_USER_DATA_START 0x16000800
|
||||
#define SFLASH_USER_DATA_SIZE 0x00000800
|
||||
|
||||
; Supervisory flash: Normal Access Restrictions (NAR)
|
||||
#define SFLASH_NAR_START 0x16001A00
|
||||
#define SFLASH_NAR_SIZE 0x00000200
|
||||
|
||||
; Supervisory flash: Public Key
|
||||
#define SFLASH_PUBLIC_KEY_START 0x16005A00
|
||||
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
|
||||
|
||||
; Supervisory flash: Table of Content # 2
|
||||
#define SFLASH_TOC_2_START 0x16007C00
|
||||
#define SFLASH_TOC_2_SIZE 0x00000200
|
||||
|
||||
; Supervisory flash: Table of Content # 2 Copy
|
||||
#define SFLASH_RTOC_2_START 0x16007E00
|
||||
#define SFLASH_RTOC_2_SIZE 0x00000200
|
||||
|
||||
; External memory
|
||||
#define XIP_START 0x18000000
|
||||
#define XIP_SIZE 0x08000000
|
||||
|
||||
; eFuse
|
||||
#define EFUSE_START 0x90700000
|
||||
#define EFUSE_SIZE 0x100000
|
||||
|
||||
; Cortex-M4 application flash area
|
||||
LR_IROM1 FLASH_START FLASH_SIZE
|
||||
{
|
||||
ER_FLASH_VECTORS +0
|
||||
{
|
||||
* (RESET, +FIRST)
|
||||
}
|
||||
|
||||
ER_FLASH_CODE +0 FIXED
|
||||
{
|
||||
* (InRoot$$Sections)
|
||||
* (+RO)
|
||||
}
|
||||
|
||||
ER_RAM_VECTORS RAM_START UNINIT
|
||||
{
|
||||
* (RESET_RAM, +FIRST)
|
||||
}
|
||||
|
||||
RW_RAM_DATA +0
|
||||
{
|
||||
* (.cy_ramfunc)
|
||||
* (+RW, +ZI)
|
||||
}
|
||||
|
||||
; Place variables in the section that should not be initialized during the
|
||||
; device startup.
|
||||
RW_IRAM1 +0 UNINIT
|
||||
{
|
||||
* (.noinit)
|
||||
}
|
||||
|
||||
; Application heap area (HEAP)
|
||||
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
|
||||
{
|
||||
}
|
||||
|
||||
; Stack region growing down
|
||||
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
|
||||
{
|
||||
}
|
||||
|
||||
; Used for the digital signature of the secure application and the
|
||||
; Bootloader SDK application. The size of the section depends on the required
|
||||
; data size.
|
||||
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
|
||||
{
|
||||
* (.cy_app_signature)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
; Emulated EEPROM Flash area
|
||||
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
|
||||
{
|
||||
.cy_em_eeprom +0
|
||||
{
|
||||
* (.cy_em_eeprom)
|
||||
}
|
||||
}
|
||||
|
||||
; Supervisory flash: User data
|
||||
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
|
||||
{
|
||||
.cy_sflash_user_data +0
|
||||
{
|
||||
* (.cy_sflash_user_data)
|
||||
}
|
||||
}
|
||||
|
||||
; Supervisory flash: Normal Access Restrictions (NAR)
|
||||
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
|
||||
{
|
||||
.cy_sflash_nar +0
|
||||
{
|
||||
* (.cy_sflash_nar)
|
||||
}
|
||||
}
|
||||
|
||||
; Supervisory flash: Public Key
|
||||
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
|
||||
{
|
||||
.cy_sflash_public_key +0
|
||||
{
|
||||
* (.cy_sflash_public_key)
|
||||
}
|
||||
}
|
||||
|
||||
; Supervisory flash: Table of Content # 2
|
||||
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
|
||||
{
|
||||
.cy_toc_part2 +0
|
||||
{
|
||||
* (.cy_toc_part2)
|
||||
}
|
||||
}
|
||||
|
||||
; Supervisory flash: Table of Content # 2 Copy
|
||||
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
|
||||
{
|
||||
.cy_rtoc_part2 +0
|
||||
{
|
||||
* (.cy_rtoc_part2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
|
||||
LR_EROM XIP_START XIP_SIZE
|
||||
{
|
||||
.cy_xip +0
|
||||
{
|
||||
* (.cy_xip)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
; eFuse
|
||||
LR_EFUSE EFUSE_START EFUSE_SIZE
|
||||
{
|
||||
.cy_efuse +0
|
||||
{
|
||||
* (.cy_efuse)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
|
||||
CYMETA 0x90500000
|
||||
{
|
||||
.cymeta +0 { * (.cymeta) }
|
||||
}
|
||||
|
||||
/* The following symbols used by the cymcuelftool. */
|
||||
/* Flash */
|
||||
#define __cy_memory_0_start 0x10000000
|
||||
#define __cy_memory_0_length 0x00200000
|
||||
#define __cy_memory_0_row_size 0x200
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
#define __cy_memory_1_start 0x14000000
|
||||
#define __cy_memory_1_length 0x8000
|
||||
#define __cy_memory_1_row_size 0x200
|
||||
|
||||
/* Supervisory Flash */
|
||||
#define __cy_memory_2_start 0x16000000
|
||||
#define __cy_memory_2_length 0x8000
|
||||
#define __cy_memory_2_row_size 0x200
|
||||
|
||||
/* XIP */
|
||||
#define __cy_memory_3_start 0x18000000
|
||||
#define __cy_memory_3_length 0x08000000
|
||||
#define __cy_memory_3_row_size 0x200
|
||||
|
||||
/* eFuse */
|
||||
#define __cy_memory_4_start 0x90700000
|
||||
#define __cy_memory_4_length 0x100000
|
||||
#define __cy_memory_4_row_size 1
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,703 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_psoc6_02_cm4.S
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM4 Device Series
|
||||
; * @version V5.00
|
||||
; * @date 02. March 2016
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
||||
|
||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD 0x0000000D ; NMI Handler located at ROM code
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External interrupts Description
|
||||
DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
|
||||
DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
|
||||
DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
|
||||
DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
|
||||
DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
|
||||
DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
|
||||
DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
|
||||
DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
|
||||
DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
|
||||
DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
|
||||
DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
|
||||
DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
|
||||
DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
|
||||
DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
|
||||
DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
|
||||
DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
|
||||
DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
|
||||
DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
|
||||
DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
|
||||
DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
|
||||
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
|
||||
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
|
||||
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
|
||||
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
|
||||
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
|
||||
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
|
||||
DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
|
||||
DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
|
||||
DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
|
||||
DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
|
||||
DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
|
||||
DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
|
||||
DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
|
||||
DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
|
||||
DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
|
||||
DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
|
||||
DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
|
||||
DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
|
||||
DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
|
||||
DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
|
||||
DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
|
||||
DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
|
||||
DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
|
||||
DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
|
||||
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
|
||||
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
|
||||
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
|
||||
DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9
|
||||
DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10
|
||||
DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11
|
||||
DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12
|
||||
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
|
||||
DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
|
||||
DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
|
||||
DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
|
||||
DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
|
||||
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
|
||||
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
|
||||
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
|
||||
DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
|
||||
DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
|
||||
DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
|
||||
DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
|
||||
DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
|
||||
DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
|
||||
DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
|
||||
DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
|
||||
DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
|
||||
DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
|
||||
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
|
||||
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
|
||||
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
|
||||
DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16
|
||||
DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17
|
||||
DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18
|
||||
DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19
|
||||
DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20
|
||||
DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21
|
||||
DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22
|
||||
DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23
|
||||
DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24
|
||||
DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25
|
||||
DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26
|
||||
DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27
|
||||
DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28
|
||||
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
|
||||
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
|
||||
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
|
||||
DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
|
||||
DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
|
||||
DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
|
||||
DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
|
||||
DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
|
||||
DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
|
||||
DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
|
||||
DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
|
||||
DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
|
||||
DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
|
||||
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
|
||||
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
|
||||
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
|
||||
DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16
|
||||
DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17
|
||||
DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18
|
||||
DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19
|
||||
DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20
|
||||
DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21
|
||||
DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22
|
||||
DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23
|
||||
DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24
|
||||
DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25
|
||||
DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26
|
||||
DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27
|
||||
DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28
|
||||
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
|
||||
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
|
||||
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
|
||||
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
|
||||
DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault
|
||||
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
|
||||
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
|
||||
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
|
||||
DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
|
||||
DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
|
||||
DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
|
||||
DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
|
||||
DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
|
||||
DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
|
||||
DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
|
||||
DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
|
||||
DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
|
||||
DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
|
||||
DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
|
||||
DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
|
||||
DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
|
||||
DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
|
||||
DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
|
||||
DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
|
||||
DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
|
||||
DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
|
||||
DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
|
||||
DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
|
||||
DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
|
||||
DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
|
||||
DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
|
||||
DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
|
||||
DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
|
||||
DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
|
||||
DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
|
||||
DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
|
||||
DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
|
||||
DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
|
||||
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
|
||||
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
|
||||
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
|
||||
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
|
||||
DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
|
||||
DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
|
||||
DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
|
||||
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
|
||||
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
|
||||
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
|
||||
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
|
||||
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
|
||||
DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
|
||||
DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
|
||||
DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used
|
||||
DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
EXPORT __ramVectors
|
||||
AREA RESET_RAM, READWRITE, NOINIT
|
||||
__ramVectors SPACE __Vectors_Size
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Weak function for startup customization
|
||||
;
|
||||
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
|
||||
; because this function is executed as the first instruction in the ResetHandler.
|
||||
; The PDL is also not initialized to use the proper register offsets.
|
||||
; The user of this function is responsible for initializing the PDL and resources before using them.
|
||||
;
|
||||
Cy_OnResetUser PROC
|
||||
EXPORT Cy_OnResetUser [WEAK]
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
; Reset Handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT Cy_SystemInitFpuEnable
|
||||
IMPORT __main
|
||||
|
||||
; Define strong function for startup customization
|
||||
BL Cy_OnResetUser
|
||||
|
||||
; Disable global interrupts
|
||||
CPSID I
|
||||
|
||||
; Copy vectors from ROM to RAM
|
||||
LDR r1, =__Vectors
|
||||
LDR r0, =__ramVectors
|
||||
LDR r2, =__Vectors_Size
|
||||
Vectors_Copy
|
||||
LDR r3, [r1]
|
||||
STR r3, [r0]
|
||||
ADDS r0, r0, #4
|
||||
ADDS r1, r1, #4
|
||||
SUBS r2, r2, #1
|
||||
CMP r2, #0
|
||||
BNE Vectors_Copy
|
||||
|
||||
; Update Vector Table Offset Register. */
|
||||
LDR r0, =__ramVectors
|
||||
LDR r1, =0xE000ED08
|
||||
STR r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
; Enable the FPU if used
|
||||
LDR R0, =Cy_SystemInitFpuEnable
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BLX R0
|
||||
|
||||
; Should never get here
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Cy_SysLib_FaultHandler PROC
|
||||
EXPORT Cy_SysLib_FaultHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Wrapper\
|
||||
PROC
|
||||
EXPORT HardFault_Wrapper [WEAK]
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq L_MSP
|
||||
mrs r0, PSP
|
||||
bl L_API_call
|
||||
L_MSP
|
||||
mrs r0, MSP
|
||||
L_API_call
|
||||
bl Cy_SysLib_FaultHandler
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT Default_Handler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
|
||||
EXPORT lpcomp_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_8_interrupt_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
|
||||
EXPORT scb_0_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_1_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_2_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_3_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_4_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_5_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_6_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_7_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_9_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_10_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_11_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_12_interrupt_IRQHandler [WEAK]
|
||||
EXPORT csd_interrupt_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
|
||||
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
|
||||
EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK]
|
||||
EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK]
|
||||
EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK]
|
||||
EXPORT profile_interrupt_IRQHandler [WEAK]
|
||||
EXPORT smif_interrupt_IRQHandler [WEAK]
|
||||
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
|
||||
EXPORT usb_interrupt_med_IRQHandler [WEAK]
|
||||
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
|
||||
EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK]
|
||||
EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK]
|
||||
EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK]
|
||||
EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK]
|
||||
|
||||
ioss_interrupts_gpio_0_IRQHandler
|
||||
ioss_interrupts_gpio_1_IRQHandler
|
||||
ioss_interrupts_gpio_2_IRQHandler
|
||||
ioss_interrupts_gpio_3_IRQHandler
|
||||
ioss_interrupts_gpio_4_IRQHandler
|
||||
ioss_interrupts_gpio_5_IRQHandler
|
||||
ioss_interrupts_gpio_6_IRQHandler
|
||||
ioss_interrupts_gpio_7_IRQHandler
|
||||
ioss_interrupts_gpio_8_IRQHandler
|
||||
ioss_interrupts_gpio_9_IRQHandler
|
||||
ioss_interrupts_gpio_10_IRQHandler
|
||||
ioss_interrupts_gpio_11_IRQHandler
|
||||
ioss_interrupts_gpio_12_IRQHandler
|
||||
ioss_interrupts_gpio_13_IRQHandler
|
||||
ioss_interrupts_gpio_14_IRQHandler
|
||||
ioss_interrupt_gpio_IRQHandler
|
||||
ioss_interrupt_vdd_IRQHandler
|
||||
lpcomp_interrupt_IRQHandler
|
||||
scb_8_interrupt_IRQHandler
|
||||
srss_interrupt_mcwdt_0_IRQHandler
|
||||
srss_interrupt_mcwdt_1_IRQHandler
|
||||
srss_interrupt_backup_IRQHandler
|
||||
srss_interrupt_IRQHandler
|
||||
cpuss_interrupts_ipc_0_IRQHandler
|
||||
cpuss_interrupts_ipc_1_IRQHandler
|
||||
cpuss_interrupts_ipc_2_IRQHandler
|
||||
cpuss_interrupts_ipc_3_IRQHandler
|
||||
cpuss_interrupts_ipc_4_IRQHandler
|
||||
cpuss_interrupts_ipc_5_IRQHandler
|
||||
cpuss_interrupts_ipc_6_IRQHandler
|
||||
cpuss_interrupts_ipc_7_IRQHandler
|
||||
cpuss_interrupts_ipc_8_IRQHandler
|
||||
cpuss_interrupts_ipc_9_IRQHandler
|
||||
cpuss_interrupts_ipc_10_IRQHandler
|
||||
cpuss_interrupts_ipc_11_IRQHandler
|
||||
cpuss_interrupts_ipc_12_IRQHandler
|
||||
cpuss_interrupts_ipc_13_IRQHandler
|
||||
cpuss_interrupts_ipc_14_IRQHandler
|
||||
cpuss_interrupts_ipc_15_IRQHandler
|
||||
scb_0_interrupt_IRQHandler
|
||||
scb_1_interrupt_IRQHandler
|
||||
scb_2_interrupt_IRQHandler
|
||||
scb_3_interrupt_IRQHandler
|
||||
scb_4_interrupt_IRQHandler
|
||||
scb_5_interrupt_IRQHandler
|
||||
scb_6_interrupt_IRQHandler
|
||||
scb_7_interrupt_IRQHandler
|
||||
scb_9_interrupt_IRQHandler
|
||||
scb_10_interrupt_IRQHandler
|
||||
scb_11_interrupt_IRQHandler
|
||||
scb_12_interrupt_IRQHandler
|
||||
csd_interrupt_IRQHandler
|
||||
cpuss_interrupts_dmac_0_IRQHandler
|
||||
cpuss_interrupts_dmac_1_IRQHandler
|
||||
cpuss_interrupts_dmac_2_IRQHandler
|
||||
cpuss_interrupts_dmac_3_IRQHandler
|
||||
cpuss_interrupts_dw0_0_IRQHandler
|
||||
cpuss_interrupts_dw0_1_IRQHandler
|
||||
cpuss_interrupts_dw0_2_IRQHandler
|
||||
cpuss_interrupts_dw0_3_IRQHandler
|
||||
cpuss_interrupts_dw0_4_IRQHandler
|
||||
cpuss_interrupts_dw0_5_IRQHandler
|
||||
cpuss_interrupts_dw0_6_IRQHandler
|
||||
cpuss_interrupts_dw0_7_IRQHandler
|
||||
cpuss_interrupts_dw0_8_IRQHandler
|
||||
cpuss_interrupts_dw0_9_IRQHandler
|
||||
cpuss_interrupts_dw0_10_IRQHandler
|
||||
cpuss_interrupts_dw0_11_IRQHandler
|
||||
cpuss_interrupts_dw0_12_IRQHandler
|
||||
cpuss_interrupts_dw0_13_IRQHandler
|
||||
cpuss_interrupts_dw0_14_IRQHandler
|
||||
cpuss_interrupts_dw0_15_IRQHandler
|
||||
cpuss_interrupts_dw0_16_IRQHandler
|
||||
cpuss_interrupts_dw0_17_IRQHandler
|
||||
cpuss_interrupts_dw0_18_IRQHandler
|
||||
cpuss_interrupts_dw0_19_IRQHandler
|
||||
cpuss_interrupts_dw0_20_IRQHandler
|
||||
cpuss_interrupts_dw0_21_IRQHandler
|
||||
cpuss_interrupts_dw0_22_IRQHandler
|
||||
cpuss_interrupts_dw0_23_IRQHandler
|
||||
cpuss_interrupts_dw0_24_IRQHandler
|
||||
cpuss_interrupts_dw0_25_IRQHandler
|
||||
cpuss_interrupts_dw0_26_IRQHandler
|
||||
cpuss_interrupts_dw0_27_IRQHandler
|
||||
cpuss_interrupts_dw0_28_IRQHandler
|
||||
cpuss_interrupts_dw1_0_IRQHandler
|
||||
cpuss_interrupts_dw1_1_IRQHandler
|
||||
cpuss_interrupts_dw1_2_IRQHandler
|
||||
cpuss_interrupts_dw1_3_IRQHandler
|
||||
cpuss_interrupts_dw1_4_IRQHandler
|
||||
cpuss_interrupts_dw1_5_IRQHandler
|
||||
cpuss_interrupts_dw1_6_IRQHandler
|
||||
cpuss_interrupts_dw1_7_IRQHandler
|
||||
cpuss_interrupts_dw1_8_IRQHandler
|
||||
cpuss_interrupts_dw1_9_IRQHandler
|
||||
cpuss_interrupts_dw1_10_IRQHandler
|
||||
cpuss_interrupts_dw1_11_IRQHandler
|
||||
cpuss_interrupts_dw1_12_IRQHandler
|
||||
cpuss_interrupts_dw1_13_IRQHandler
|
||||
cpuss_interrupts_dw1_14_IRQHandler
|
||||
cpuss_interrupts_dw1_15_IRQHandler
|
||||
cpuss_interrupts_dw1_16_IRQHandler
|
||||
cpuss_interrupts_dw1_17_IRQHandler
|
||||
cpuss_interrupts_dw1_18_IRQHandler
|
||||
cpuss_interrupts_dw1_19_IRQHandler
|
||||
cpuss_interrupts_dw1_20_IRQHandler
|
||||
cpuss_interrupts_dw1_21_IRQHandler
|
||||
cpuss_interrupts_dw1_22_IRQHandler
|
||||
cpuss_interrupts_dw1_23_IRQHandler
|
||||
cpuss_interrupts_dw1_24_IRQHandler
|
||||
cpuss_interrupts_dw1_25_IRQHandler
|
||||
cpuss_interrupts_dw1_26_IRQHandler
|
||||
cpuss_interrupts_dw1_27_IRQHandler
|
||||
cpuss_interrupts_dw1_28_IRQHandler
|
||||
cpuss_interrupts_fault_0_IRQHandler
|
||||
cpuss_interrupts_fault_1_IRQHandler
|
||||
cpuss_interrupt_crypto_IRQHandler
|
||||
cpuss_interrupt_fm_IRQHandler
|
||||
cpuss_interrupts_cm4_fp_IRQHandler
|
||||
cpuss_interrupts_cm0_cti_0_IRQHandler
|
||||
cpuss_interrupts_cm0_cti_1_IRQHandler
|
||||
cpuss_interrupts_cm4_cti_0_IRQHandler
|
||||
cpuss_interrupts_cm4_cti_1_IRQHandler
|
||||
tcpwm_0_interrupts_0_IRQHandler
|
||||
tcpwm_0_interrupts_1_IRQHandler
|
||||
tcpwm_0_interrupts_2_IRQHandler
|
||||
tcpwm_0_interrupts_3_IRQHandler
|
||||
tcpwm_0_interrupts_4_IRQHandler
|
||||
tcpwm_0_interrupts_5_IRQHandler
|
||||
tcpwm_0_interrupts_6_IRQHandler
|
||||
tcpwm_0_interrupts_7_IRQHandler
|
||||
tcpwm_1_interrupts_0_IRQHandler
|
||||
tcpwm_1_interrupts_1_IRQHandler
|
||||
tcpwm_1_interrupts_2_IRQHandler
|
||||
tcpwm_1_interrupts_3_IRQHandler
|
||||
tcpwm_1_interrupts_4_IRQHandler
|
||||
tcpwm_1_interrupts_5_IRQHandler
|
||||
tcpwm_1_interrupts_6_IRQHandler
|
||||
tcpwm_1_interrupts_7_IRQHandler
|
||||
tcpwm_1_interrupts_8_IRQHandler
|
||||
tcpwm_1_interrupts_9_IRQHandler
|
||||
tcpwm_1_interrupts_10_IRQHandler
|
||||
tcpwm_1_interrupts_11_IRQHandler
|
||||
tcpwm_1_interrupts_12_IRQHandler
|
||||
tcpwm_1_interrupts_13_IRQHandler
|
||||
tcpwm_1_interrupts_14_IRQHandler
|
||||
tcpwm_1_interrupts_15_IRQHandler
|
||||
tcpwm_1_interrupts_16_IRQHandler
|
||||
tcpwm_1_interrupts_17_IRQHandler
|
||||
tcpwm_1_interrupts_18_IRQHandler
|
||||
tcpwm_1_interrupts_19_IRQHandler
|
||||
tcpwm_1_interrupts_20_IRQHandler
|
||||
tcpwm_1_interrupts_21_IRQHandler
|
||||
tcpwm_1_interrupts_22_IRQHandler
|
||||
tcpwm_1_interrupts_23_IRQHandler
|
||||
pass_interrupt_sar_IRQHandler
|
||||
audioss_0_interrupt_i2s_IRQHandler
|
||||
audioss_0_interrupt_pdm_IRQHandler
|
||||
audioss_1_interrupt_i2s_IRQHandler
|
||||
profile_interrupt_IRQHandler
|
||||
smif_interrupt_IRQHandler
|
||||
usb_interrupt_hi_IRQHandler
|
||||
usb_interrupt_med_IRQHandler
|
||||
usb_interrupt_lo_IRQHandler
|
||||
sdhc_0_interrupt_wakeup_IRQHandler
|
||||
sdhc_0_interrupt_general_IRQHandler
|
||||
sdhc_1_interrupt_wakeup_IRQHandler
|
||||
sdhc_1_interrupt_general_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
END
|
||||
|
||||
|
||||
; [] END OF FILE
|
||||
@@ -0,0 +1,448 @@
|
||||
/***************************************************************************//**
|
||||
* \file cy8c6xxa_cm4_dual.ld
|
||||
* \version 2.60
|
||||
*
|
||||
* Linker file for the GNU C compiler.
|
||||
*
|
||||
* The main purpose of the linker script is to describe how the sections in the
|
||||
* input files should be mapped into the output file, and to control the memory
|
||||
* layout of the output file.
|
||||
*
|
||||
* \note The entry point location is fixed and starts at 0x10000000. The valid
|
||||
* application image should be placed there.
|
||||
*
|
||||
* \note The linker files included with the PDL template projects must be generic
|
||||
* and handle all common use cases. Your project may not use every section
|
||||
* defined in the linker files. In that case you may see warnings during the
|
||||
* build process. In your project, you can simply comment out or remove the
|
||||
* relevant code in the linker file.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
#if !defined(MBED_ROM_START)
|
||||
#define MBED_ROM_START 0x10180000
|
||||
#endif
|
||||
|
||||
/* MBED_APP_START is being used by the bootloader build script and
|
||||
* will be calculate by the system. In case if MBED_APP_START address is
|
||||
* customized by the bootloader config, the application image should not
|
||||
* include CM0p prebuilt image.
|
||||
*/
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START (MBED_ROM_START)
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_ROM_SIZE)
|
||||
#define MBED_ROM_SIZE 0x80000
|
||||
#endif
|
||||
|
||||
/* MBED_APP_SIZE is being used by the bootloader build script and
|
||||
* will be calculate by the system.
|
||||
*/
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE MBED_ROM_SIZE
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_START)
|
||||
#define MBED_RAM_START 0x08080000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_SIZE)
|
||||
#define MBED_RAM_SIZE 0x7F800
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
/* Size of the stack section at the end of CM4 SRAM */
|
||||
STACK_SIZE = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
/* Force symbol to be entered in the output file as an undefined symbol. Doing
|
||||
* this may, for example, trigger linking of additional modules from standard
|
||||
* libraries. You may list several symbols for each EXTERN, and you may use
|
||||
* EXTERN multiple times. This command has the same effect as the -u command-line
|
||||
* option.
|
||||
*/
|
||||
EXTERN(Reset_Handler)
|
||||
|
||||
/* The MEMORY section below describes the location and size of blocks of memory in the target.
|
||||
* Use this section to specify the memory regions available for allocation.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
|
||||
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
|
||||
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
|
||||
* Using this memory region for other purposes will lead to unexpected behavior.
|
||||
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
|
||||
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
|
||||
*/
|
||||
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
|
||||
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
|
||||
|
||||
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
|
||||
* You can assign sections to this memory region for only one of the cores.
|
||||
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
|
||||
* Therefore, repurposing this memory region will prevent such middleware from operation.
|
||||
*/
|
||||
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
|
||||
|
||||
/* The following regions define device specific memory regions and must not be changed. */
|
||||
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
|
||||
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
|
||||
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
|
||||
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
|
||||
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
|
||||
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
|
||||
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
*/
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Cortex-M4 application flash area */
|
||||
.text ORIGIN(flash) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__Vectors = . ;
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
__end__ = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
/* Read-only code (constants). */
|
||||
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > flash
|
||||
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > flash
|
||||
__exidx_end = .;
|
||||
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
|
||||
/* Copy interrupt vectors from flash to RAM */
|
||||
LONG (__Vectors) /* From */
|
||||
LONG (__ram_vectors_start__) /* To */
|
||||
LONG (__Vectors_End - __Vectors) /* Size */
|
||||
|
||||
/* Copy data section to RAM */
|
||||
LONG (__etext) /* From */
|
||||
LONG (__data_start__) /* To */
|
||||
LONG (__data_end__ - __data_start__) /* Size */
|
||||
|
||||
__copy_table_end__ = .;
|
||||
} > flash
|
||||
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > flash
|
||||
|
||||
__etext = . ;
|
||||
|
||||
|
||||
.ramVectors (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
__ram_vectors_start__ = .;
|
||||
KEEP(*(.ram_vectors))
|
||||
__ram_vectors_end__ = .;
|
||||
} > ram
|
||||
|
||||
|
||||
.data __ram_vectors_end__ : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
|
||||
KEEP(*(.cy_ramfunc*))
|
||||
. = ALIGN(4);
|
||||
|
||||
__data_end__ = .;
|
||||
|
||||
} > ram
|
||||
|
||||
|
||||
/* Place variables in the section that should not be initialized during the
|
||||
* device startup.
|
||||
*/
|
||||
.noinit (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
KEEP(*(.noinit))
|
||||
} > ram
|
||||
|
||||
|
||||
/* The uninitialized global or static variables are placed in this section.
|
||||
*
|
||||
* The NOLOAD attribute tells linker that .bss section does not consume
|
||||
* any space in the image. The NOLOAD attribute changes the .bss type to
|
||||
* NOBITS, and that makes linker to A) not allocate section in memory, and
|
||||
* A) put information to clear the section with all zeros during application
|
||||
* loading.
|
||||
*
|
||||
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
|
||||
* This makes linker to A) allocate zeroed section in memory, and B) copy
|
||||
* this section to RAM during application loading.
|
||||
*/
|
||||
.bss (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > ram
|
||||
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
__HeapBase = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
KEEP(*(.heap*))
|
||||
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
|
||||
__HeapLimit = .;
|
||||
} > ram
|
||||
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(ram) + LENGTH(ram);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
|
||||
/* Used for the digital signature of the secure application and the Bootloader SDK application.
|
||||
* The size of the section depends on the required data size. */
|
||||
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
|
||||
{
|
||||
KEEP(*(.cy_app_signature))
|
||||
} > flash
|
||||
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
.cy_em_eeprom :
|
||||
{
|
||||
KEEP(*(.cy_em_eeprom))
|
||||
} > em_eeprom
|
||||
|
||||
|
||||
/* Supervisory Flash: User data */
|
||||
.cy_sflash_user_data :
|
||||
{
|
||||
KEEP(*(.cy_sflash_user_data))
|
||||
} > sflash_user_data
|
||||
|
||||
|
||||
/* Supervisory Flash: Normal Access Restrictions (NAR) */
|
||||
.cy_sflash_nar :
|
||||
{
|
||||
KEEP(*(.cy_sflash_nar))
|
||||
} > sflash_nar
|
||||
|
||||
|
||||
/* Supervisory Flash: Public Key */
|
||||
.cy_sflash_public_key :
|
||||
{
|
||||
KEEP(*(.cy_sflash_public_key))
|
||||
} > sflash_public_key
|
||||
|
||||
|
||||
/* Supervisory Flash: Table of Content # 2 */
|
||||
.cy_toc_part2 :
|
||||
{
|
||||
KEEP(*(.cy_toc_part2))
|
||||
} > sflash_toc_2
|
||||
|
||||
|
||||
/* Supervisory Flash: Table of Content # 2 Copy */
|
||||
.cy_rtoc_part2 :
|
||||
{
|
||||
KEEP(*(.cy_rtoc_part2))
|
||||
} > sflash_rtoc_2
|
||||
|
||||
|
||||
/* Places the code in the Execute in Place (XIP) section. See the smif driver
|
||||
* documentation for details.
|
||||
*/
|
||||
.cy_xip :
|
||||
{
|
||||
KEEP(*(.cy_xip))
|
||||
} > xip
|
||||
|
||||
|
||||
/* eFuse */
|
||||
.cy_efuse :
|
||||
{
|
||||
KEEP(*(.cy_efuse))
|
||||
} > efuse
|
||||
|
||||
|
||||
/* These sections are used for additional metadata (silicon revision,
|
||||
* Silicon/JTAG ID, etc.) storage.
|
||||
*/
|
||||
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
|
||||
}
|
||||
|
||||
|
||||
/* The following symbols used by the cymcuelftool. */
|
||||
/* Flash */
|
||||
__cy_memory_0_start = 0x10000000;
|
||||
__cy_memory_0_length = 0x00200000;
|
||||
__cy_memory_0_row_size = 0x200;
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
__cy_memory_1_start = 0x14000000;
|
||||
__cy_memory_1_length = 0x8000;
|
||||
__cy_memory_1_row_size = 0x200;
|
||||
|
||||
/* Supervisory Flash */
|
||||
__cy_memory_2_start = 0x16000000;
|
||||
__cy_memory_2_length = 0x8000;
|
||||
__cy_memory_2_row_size = 0x200;
|
||||
|
||||
/* XIP */
|
||||
__cy_memory_3_start = 0x18000000;
|
||||
__cy_memory_3_length = 0x08000000;
|
||||
__cy_memory_3_row_size = 0x200;
|
||||
|
||||
/* eFuse */
|
||||
__cy_memory_4_start = 0x90700000;
|
||||
__cy_memory_4_length = 0x100000;
|
||||
__cy_memory_4_row_size = 1;
|
||||
|
||||
/* EOF */
|
||||
@@ -0,0 +1,673 @@
|
||||
/**************************************************************************//**
|
||||
* @file startup_psoc6_02_cm4.S
|
||||
* @brief CMSIS Core Device Startup File for
|
||||
* ARMCM4 Device Series
|
||||
* @version V5.00
|
||||
* @date 02. March 2016
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Address of the NMI handler */
|
||||
#define CY_NMI_HANLDER_ADDR 0x0000000D
|
||||
|
||||
/* The CPU VTOR register */
|
||||
#define CY_CPU_VTOR_ADDR 0xE000ED08
|
||||
|
||||
/* Copy flash vectors and data section to RAM */
|
||||
#define __STARTUP_COPY_MULTIPLE
|
||||
|
||||
/* Clear single BSS section */
|
||||
#define __STARTUP_CLEAR_BSS
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00001000
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000400
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts Description */
|
||||
.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
|
||||
.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
|
||||
.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
|
||||
.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
|
||||
.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
|
||||
.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
|
||||
.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
|
||||
.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
|
||||
.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
|
||||
.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
|
||||
.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
|
||||
.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
|
||||
.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
|
||||
.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
|
||||
.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
|
||||
.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
|
||||
.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
|
||||
.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
|
||||
.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
|
||||
.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
|
||||
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
|
||||
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
|
||||
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
|
||||
.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
|
||||
.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
|
||||
.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
|
||||
.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
|
||||
.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
|
||||
.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
|
||||
.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
|
||||
.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
|
||||
.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
|
||||
.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
|
||||
.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
|
||||
.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
|
||||
.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
|
||||
.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
|
||||
.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
|
||||
.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
|
||||
.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
|
||||
.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
|
||||
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
|
||||
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
|
||||
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
|
||||
.long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
|
||||
.long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
|
||||
.long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
|
||||
.long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
|
||||
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
|
||||
.long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
|
||||
.long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
|
||||
.long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
|
||||
.long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
|
||||
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
|
||||
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
|
||||
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
|
||||
.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
|
||||
.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
|
||||
.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
|
||||
.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
|
||||
.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
|
||||
.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
|
||||
.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
|
||||
.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
|
||||
.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
|
||||
.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
|
||||
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
|
||||
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
|
||||
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
|
||||
.long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
|
||||
.long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
|
||||
.long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
|
||||
.long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
|
||||
.long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
|
||||
.long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
|
||||
.long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
|
||||
.long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
|
||||
.long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
|
||||
.long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
|
||||
.long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
|
||||
.long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
|
||||
.long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
|
||||
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
|
||||
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
|
||||
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
|
||||
.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
|
||||
.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
|
||||
.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
|
||||
.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
|
||||
.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
|
||||
.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
|
||||
.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
|
||||
.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
|
||||
.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
|
||||
.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
|
||||
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
|
||||
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
|
||||
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
|
||||
.long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
|
||||
.long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
|
||||
.long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
|
||||
.long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
|
||||
.long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
|
||||
.long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
|
||||
.long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
|
||||
.long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
|
||||
.long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
|
||||
.long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
|
||||
.long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
|
||||
.long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
|
||||
.long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
|
||||
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
|
||||
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
|
||||
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
|
||||
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
|
||||
.long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
|
||||
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
|
||||
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
|
||||
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
|
||||
.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
|
||||
.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
|
||||
.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
|
||||
.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
|
||||
.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
|
||||
.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
|
||||
.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
|
||||
.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
|
||||
.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
|
||||
.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
|
||||
.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
|
||||
.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
|
||||
.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
|
||||
.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
|
||||
.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
|
||||
.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
|
||||
.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
|
||||
.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
|
||||
.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
|
||||
.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
|
||||
.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
|
||||
.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
|
||||
.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
|
||||
.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
|
||||
.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
|
||||
.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
|
||||
.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
|
||||
.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
|
||||
.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
|
||||
.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
|
||||
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
|
||||
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
|
||||
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
|
||||
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
|
||||
.long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
|
||||
.long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
|
||||
.long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
|
||||
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
|
||||
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
|
||||
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
|
||||
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
|
||||
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
|
||||
.long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
|
||||
.long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
|
||||
.long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
|
||||
.long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
|
||||
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
.equ __VectorsSize, . - __Vectors
|
||||
|
||||
.section .ram_vectors
|
||||
.align 2
|
||||
.globl __ramVectors
|
||||
__ramVectors:
|
||||
.space __VectorsSize
|
||||
.size __ramVectors, . - __ramVectors
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
|
||||
/*
|
||||
* Device startup customization
|
||||
*
|
||||
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
|
||||
* because this function is executed as the first instruction in the ResetHandler.
|
||||
* The PDL is also not initialized to use the proper register offsets.
|
||||
* The user of this function is responsible for initializing the PDL and resources before using them.
|
||||
*/
|
||||
.weak Cy_OnResetUser
|
||||
.func Cy_OnResetUser, Cy_OnResetUser
|
||||
.type Cy_OnResetUser, %function
|
||||
|
||||
Cy_OnResetUser:
|
||||
bx lr
|
||||
.size Cy_OnResetUser, . - Cy_OnResetUser
|
||||
.endfunc
|
||||
|
||||
/* Reset handler */
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
Reset_Handler:
|
||||
bl Cy_OnResetUser
|
||||
cpsid i
|
||||
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Update Vector Table Offset Register. */
|
||||
ldr r0, =__ramVectors
|
||||
ldr r1, =CY_CPU_VTOR_ADDR
|
||||
str r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
/* Enable the FPU if used */
|
||||
bl Cy_SystemInitFpuEnable
|
||||
|
||||
bl _start
|
||||
|
||||
/* Should never get here */
|
||||
b .
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
|
||||
.weak Cy_SysLib_FaultHandler
|
||||
.type Cy_SysLib_FaultHandler, %function
|
||||
|
||||
Cy_SysLib_FaultHandler:
|
||||
b .
|
||||
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
|
||||
.type Fault_Handler, %function
|
||||
|
||||
Fault_Handler:
|
||||
/* Storing LR content for Creator call stack trace */
|
||||
push {LR}
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq .L_MSP
|
||||
mrs r0, PSP
|
||||
b .L_API_call
|
||||
.L_MSP:
|
||||
mrs r0, MSP
|
||||
.L_API_call:
|
||||
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
|
||||
adds r0, r0, #4
|
||||
bl Cy_SysLib_FaultHandler
|
||||
b .
|
||||
.size Fault_Handler, . - Fault_Handler
|
||||
|
||||
.macro def_fault_Handler fault_handler_name
|
||||
.weak \fault_handler_name
|
||||
.set \fault_handler_name, Fault_Handler
|
||||
.endm
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
|
||||
def_fault_Handler HardFault_Handler
|
||||
def_fault_Handler MemManage_Handler
|
||||
def_fault_Handler BusFault_Handler
|
||||
def_fault_Handler UsageFault_Handler
|
||||
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
|
||||
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
|
||||
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
|
||||
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
|
||||
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
|
||||
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
|
||||
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
|
||||
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
|
||||
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
|
||||
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
|
||||
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
|
||||
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
|
||||
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
|
||||
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
|
||||
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
|
||||
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
|
||||
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
|
||||
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
|
||||
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
|
||||
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
|
||||
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
|
||||
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
|
||||
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
|
||||
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
|
||||
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
|
||||
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
|
||||
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
|
||||
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
|
||||
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
|
||||
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
|
||||
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
|
||||
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
|
||||
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
|
||||
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
|
||||
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
|
||||
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
|
||||
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
|
||||
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
|
||||
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
|
||||
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
|
||||
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
|
||||
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
|
||||
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
|
||||
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
|
||||
def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
|
||||
def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
|
||||
def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
|
||||
def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
|
||||
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
|
||||
def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
|
||||
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
|
||||
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
|
||||
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
|
||||
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
|
||||
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
|
||||
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
|
||||
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
|
||||
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
|
||||
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
|
||||
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
|
||||
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
|
||||
def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
|
||||
def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
|
||||
def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
|
||||
def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
|
||||
def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
|
||||
def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
|
||||
def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
|
||||
def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
|
||||
def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
|
||||
def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
|
||||
def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
|
||||
def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
|
||||
def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
|
||||
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
|
||||
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
|
||||
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
|
||||
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
|
||||
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
|
||||
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
|
||||
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
|
||||
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
|
||||
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
|
||||
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
|
||||
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
|
||||
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
|
||||
def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
|
||||
def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
|
||||
def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
|
||||
def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
|
||||
def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
|
||||
def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
|
||||
def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
|
||||
def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
|
||||
def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
|
||||
def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
|
||||
def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
|
||||
def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
|
||||
def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
|
||||
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
|
||||
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
|
||||
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
|
||||
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
|
||||
def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
|
||||
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
|
||||
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
|
||||
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
|
||||
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
|
||||
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
|
||||
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
|
||||
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
|
||||
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
|
||||
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
|
||||
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
|
||||
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
|
||||
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
|
||||
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
|
||||
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
|
||||
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
|
||||
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
|
||||
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
|
||||
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
|
||||
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
|
||||
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
|
||||
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
|
||||
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
|
||||
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
|
||||
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
|
||||
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
|
||||
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
|
||||
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
|
||||
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
|
||||
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
|
||||
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
|
||||
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
|
||||
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
|
||||
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
|
||||
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
|
||||
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
|
||||
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
|
||||
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
|
||||
def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
|
||||
def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
|
||||
def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
|
||||
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
|
||||
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
|
||||
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
|
||||
def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
|
||||
def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
|
||||
def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
|
||||
|
||||
.end
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,274 @@
|
||||
/***************************************************************************//**
|
||||
* \file cy8c6xxa_cm4_dual.icf
|
||||
* \version 2.60
|
||||
*
|
||||
* Linker file for the IAR compiler.
|
||||
*
|
||||
* The main purpose of the linker script is to describe how the sections in the
|
||||
* input files should be mapped into the output file, and to control the memory
|
||||
* layout of the output file.
|
||||
*
|
||||
* \note The entry point is fixed and starts at 0x10000000. The valid application
|
||||
* image should be placed there.
|
||||
*
|
||||
* \note The linker files included with the PDL template projects must be generic
|
||||
* and handle all common use cases. Your project may not use every section
|
||||
* defined in the linker files. In that case you may see warnings during the
|
||||
* build process. In your project, you can simply comment out or remove the
|
||||
* relevant code in the linker file.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
|
||||
if (!isdefinedsymbol(MBED_ROM_START)) {
|
||||
define symbol MBED_ROM_START = 0x10180000;
|
||||
}
|
||||
|
||||
/* MBED_APP_START is being used by the bootloader build script and
|
||||
* will be calculate by the system. In case if MBED_APP_START address is
|
||||
* customized by the bootloader config, the application image should not
|
||||
* include CM0p prebuilt image.
|
||||
*/
|
||||
if (!isdefinedsymbol(MBED_APP_START)) {
|
||||
define symbol MBED_APP_START = (MBED_ROM_START);
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
|
||||
define symbol MBED_ROM_SIZE = 0x80000;
|
||||
}
|
||||
|
||||
/* MBED_APP_SIZE is being used by the bootloader build script and
|
||||
* will be calculate by the system.
|
||||
*/
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) {
|
||||
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE);
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_RAM_START)) {
|
||||
define symbol MBED_RAM_START = 0x08080000;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
|
||||
define symbol MBED_RAM_SIZE = 0x7F800;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
|
||||
if (!isdefinedsymbol(__STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
|
||||
} else {
|
||||
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
/* The symbols below define the location and size of blocks of memory in the target.
|
||||
* Use these symbols to specify the memory regions available for allocation.
|
||||
*/
|
||||
|
||||
/* The following symbols control RAM and flash memory allocation for the CM4 core.
|
||||
* You can change the memory allocation by editing RAM and Flash symbols.
|
||||
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
|
||||
* Using this memory region for other purposes will lead to unexpected behavior.
|
||||
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
|
||||
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
|
||||
*/
|
||||
/* RAM */
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
|
||||
/* Flash */
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
|
||||
|
||||
/* The following symbols define a 32K flash region used for EEPROM emulation.
|
||||
* This region can also be used as the general purpose flash.
|
||||
* You can assign sections to this memory region for only one of the cores.
|
||||
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
|
||||
* Therefore, repurposing this memory region will prevent such middleware from operation.
|
||||
*/
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
|
||||
|
||||
/* The following symbols define device specific memory regions and must not be changed. */
|
||||
/* Supervisory FLASH - User Data */
|
||||
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
|
||||
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
|
||||
|
||||
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
|
||||
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
|
||||
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
|
||||
|
||||
/* Supervisory FLASH - Public Key */
|
||||
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
|
||||
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
|
||||
|
||||
/* Supervisory FLASH - Table of Content # 2 */
|
||||
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
|
||||
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
|
||||
|
||||
/* Supervisory FLASH - Table of Content # 2 Copy */
|
||||
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
|
||||
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
|
||||
|
||||
/* eFuse */
|
||||
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
|
||||
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
|
||||
|
||||
/* XIP */
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
|
||||
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
|
||||
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
/*-Sizes-*/
|
||||
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
|
||||
if (!isdefinedsymbol(__HEAP_SIZE)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0400;
|
||||
} else {
|
||||
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
|
||||
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
|
||||
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
|
||||
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
|
||||
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
|
||||
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
|
||||
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
|
||||
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
|
||||
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
|
||||
|
||||
define block RAM_DATA {readwrite section .data};
|
||||
define block RAM_OTHER {readwrite section * };
|
||||
define block RAM_NOINIT {readwrite section .noinit};
|
||||
define block RAM_BSS {readwrite section .bss};
|
||||
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define block RO {first section .intvec, readonly};
|
||||
|
||||
/*-Initializations-*/
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit, section .intvec_ram };
|
||||
|
||||
/*-Placement-*/
|
||||
|
||||
/* Flash - Cortex-M4 application */
|
||||
place at start of IROM1_region { block RO };
|
||||
|
||||
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
|
||||
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
|
||||
|
||||
/* Supervisory Flash - User Data */
|
||||
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
|
||||
|
||||
/* Supervisory Flash - NAR */
|
||||
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
|
||||
|
||||
/* Supervisory Flash - Public Key */
|
||||
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
|
||||
|
||||
/* Supervisory Flash - TOC2 */
|
||||
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
|
||||
|
||||
/* Supervisory Flash - RTOC2 */
|
||||
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
|
||||
|
||||
/* eFuse */
|
||||
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
|
||||
|
||||
/* Execute in Place (XIP). See the smif driver documentation for details. */
|
||||
".cy_xip" : place at start of EROM1_region { section .cy_xip };
|
||||
|
||||
/* RAM */
|
||||
place at start of IRAM1_region { readwrite section .intvec_ram};
|
||||
place in IRAM1_region { block RAM};
|
||||
place in IRAM1_region { block HEAP};
|
||||
place at end of IRAM1_region { block CSTACK };
|
||||
|
||||
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
|
||||
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
|
||||
|
||||
|
||||
keep { section .cy_app_signature,
|
||||
section .cy_em_eeprom,
|
||||
section .cy_sflash_user_data,
|
||||
section .cy_sflash_nar,
|
||||
section .cy_sflash_public_key,
|
||||
section .cy_toc_part2,
|
||||
section .cy_rtoc_part2,
|
||||
section .cy_efuse,
|
||||
section .cy_xip,
|
||||
section .cymeta,
|
||||
};
|
||||
|
||||
|
||||
/* The following symbols used by the cymcuelftool. */
|
||||
/* Flash */
|
||||
define exported symbol __cy_memory_0_start = 0x10000000;
|
||||
define exported symbol __cy_memory_0_length = 0x00200000;
|
||||
define exported symbol __cy_memory_0_row_size = 0x200;
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
define exported symbol __cy_memory_1_start = 0x14000000;
|
||||
define exported symbol __cy_memory_1_length = 0x8000;
|
||||
define exported symbol __cy_memory_1_row_size = 0x200;
|
||||
|
||||
/* Supervisory Flash */
|
||||
define exported symbol __cy_memory_2_start = 0x16000000;
|
||||
define exported symbol __cy_memory_2_length = 0x8000;
|
||||
define exported symbol __cy_memory_2_row_size = 0x200;
|
||||
|
||||
/* XIP */
|
||||
define exported symbol __cy_memory_3_start = 0x18000000;
|
||||
define exported symbol __cy_memory_3_length = 0x08000000;
|
||||
define exported symbol __cy_memory_3_row_size = 0x200;
|
||||
|
||||
/* eFuse */
|
||||
define exported symbol __cy_memory_4_start = 0x90700000;
|
||||
define exported symbol __cy_memory_4_length = 0x100000;
|
||||
define exported symbol __cy_memory_4_row_size = 1;
|
||||
|
||||
/* EOF */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,552 @@
|
||||
/***************************************************************************//**
|
||||
* \file system_psoc6_cm4.c
|
||||
* \version 2.60
|
||||
*
|
||||
* The device system-source file.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "system_psoc6.h"
|
||||
#include "cy_device.h"
|
||||
#include "cy_device_headers.h"
|
||||
#include "cy_syslib.h"
|
||||
#include "cy_wdt.h"
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
#include "cy_ipc_sema.h"
|
||||
#include "cy_ipc_pipe.h"
|
||||
#include "cy_ipc_drv.h"
|
||||
|
||||
#if defined(CY_DEVICE_PSOC6ABLE2)
|
||||
#include "cy_flash.h"
|
||||
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
|
||||
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* SystemCoreClockUpdate()
|
||||
*******************************************************************************/
|
||||
|
||||
/** Default HFClk frequency in Hz */
|
||||
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
|
||||
|
||||
/** Default PeriClk frequency in Hz */
|
||||
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
|
||||
|
||||
/** Default SlowClk system core frequency in Hz */
|
||||
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
|
||||
|
||||
/** IMO frequency in Hz */
|
||||
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
|
||||
|
||||
/** HVILO frequency in Hz */
|
||||
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
|
||||
|
||||
/** PILO frequency in Hz */
|
||||
#define CY_CLK_PILO_FREQ_HZ (32768UL)
|
||||
|
||||
/** WCO frequency in Hz */
|
||||
#define CY_CLK_WCO_FREQ_HZ (32768UL)
|
||||
|
||||
/** ALTLF frequency in Hz */
|
||||
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
|
||||
|
||||
|
||||
/**
|
||||
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
|
||||
* which is the system clock frequency supplied to the SysTick timer and the
|
||||
* processor core clock.
|
||||
* This variable implements CMSIS Core global variable.
|
||||
* Refer to the [CMSIS documentation]
|
||||
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
|
||||
* for more details.
|
||||
* This variable can be used by debuggers to query the frequency
|
||||
* of the debug timer or to configure the trace clock speed.
|
||||
*
|
||||
* \attention Compilers must be configured to avoid removing this variable in case
|
||||
* the application program is not using it. Debugging systems require the variable
|
||||
* to be physically present in memory so that it can be examined to configure the debugger. */
|
||||
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
|
||||
|
||||
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
|
||||
uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
|
||||
|
||||
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
|
||||
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
|
||||
|
||||
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
|
||||
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
|
||||
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
|
||||
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
|
||||
|
||||
/* SCB->CPACR */
|
||||
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* SystemInit()
|
||||
*******************************************************************************/
|
||||
|
||||
/* CLK_FLL_CONFIG default values */
|
||||
#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
|
||||
#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
|
||||
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
|
||||
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* SystemCoreClockUpdate (void)
|
||||
*******************************************************************************/
|
||||
|
||||
/* Do not use these definitions directly in your application */
|
||||
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
|
||||
#define CY_DELAY_1K_THRESHOLD (1000u)
|
||||
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
|
||||
#define CY_DELAY_1M_THRESHOLD (1000000u)
|
||||
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
|
||||
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
|
||||
|
||||
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
|
||||
CY_DELAY_1K_THRESHOLD;
|
||||
|
||||
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
|
||||
CY_DELAY_1M_THRESHOLD);
|
||||
|
||||
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
|
||||
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
|
||||
|
||||
#define CY_ROOT_PATH_SRC_IMO (0UL)
|
||||
#define CY_ROOT_PATH_SRC_EXT (1UL)
|
||||
#if (SRSS_ECO_PRESENT == 1U)
|
||||
#define CY_ROOT_PATH_SRC_ECO (2UL)
|
||||
#endif /* (SRSS_ECO_PRESENT == 1U) */
|
||||
#if (SRSS_ALTHF_PRESENT == 1U)
|
||||
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
|
||||
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
|
||||
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
|
||||
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
|
||||
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
|
||||
#if (SRSS_ALTLF_PRESENT == 1U)
|
||||
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
|
||||
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
|
||||
#if (SRSS_PILO_PRESENT == 1U)
|
||||
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
|
||||
#endif /* (SRSS_PILO_PRESENT == 1U) */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SystemInit
|
||||
****************************************************************************//**
|
||||
* \cond
|
||||
* Initializes the system:
|
||||
* - Restores FLL registers to the default state for single core devices.
|
||||
* - Unlocks and disables WDT.
|
||||
* - Calls Cy_PDL_Init() function to define the driver library.
|
||||
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
|
||||
* - Calls \ref SystemCoreClockUpdate().
|
||||
* \endcond
|
||||
*******************************************************************************/
|
||||
void SystemInit(void)
|
||||
{
|
||||
Cy_PDL_Init(CY_DEVICE_CFG);
|
||||
|
||||
#ifdef __CM0P_PRESENT
|
||||
#if (__CM0P_PRESENT == 0)
|
||||
/* Restore FLL registers to the default state as they are not restored by the ROM code */
|
||||
uint32_t copy = SRSS->CLK_FLL_CONFIG;
|
||||
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
|
||||
SRSS->CLK_FLL_CONFIG = copy;
|
||||
|
||||
copy = SRSS->CLK_ROOT_SELECT[0u];
|
||||
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
|
||||
SRSS->CLK_ROOT_SELECT[0u] = copy;
|
||||
|
||||
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
|
||||
|
||||
/* Unlock and disable WDT */
|
||||
Cy_WDT_Unlock();
|
||||
Cy_WDT_Disable();
|
||||
#endif /* (__CM0P_PRESENT == 0) */
|
||||
#endif /* __CM0P_PRESENT */
|
||||
|
||||
Cy_SystemInit();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
|
||||
#ifdef __CM0P_PRESENT
|
||||
#if (__CM0P_PRESENT == 0)
|
||||
/* Allocate and initialize semaphores for the system operations. */
|
||||
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
|
||||
#else
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
|
||||
#endif /* (__CM0P_PRESENT) */
|
||||
#else
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
|
||||
#endif /* __CM0P_PRESENT */
|
||||
|
||||
|
||||
/********************************************************************************
|
||||
*
|
||||
* Initializes the system pipes. The system pipes are used by BLE and Flash.
|
||||
*
|
||||
* If the default startup file is not used, or SystemInit() is not called in your
|
||||
* project, call the following three functions prior to executing any flash or
|
||||
* EmEEPROM write or erase operation:
|
||||
* -# Cy_IPC_Sema_Init()
|
||||
* -# Cy_IPC_Pipe_Config()
|
||||
* -# Cy_IPC_Pipe_Init()
|
||||
* -# Cy_Flash_Init()
|
||||
*
|
||||
*******************************************************************************/
|
||||
/* Create an array of endpoint structures */
|
||||
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
|
||||
|
||||
Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
|
||||
|
||||
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
|
||||
|
||||
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
|
||||
{
|
||||
/* .ep0ConfigData */
|
||||
{
|
||||
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
|
||||
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
|
||||
/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
|
||||
/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
|
||||
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
|
||||
},
|
||||
/* .ep1ConfigData */
|
||||
{
|
||||
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
|
||||
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
|
||||
/* .ipcNotifierMuxNumber */ 0u,
|
||||
/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
|
||||
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
|
||||
},
|
||||
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
|
||||
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
|
||||
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
|
||||
};
|
||||
|
||||
if (cy_device->flashPipeRequired != 0u)
|
||||
{
|
||||
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
|
||||
}
|
||||
|
||||
#if defined(CY_DEVICE_PSOC6ABLE2)
|
||||
Cy_Flash_Init();
|
||||
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
|
||||
|
||||
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SystemInit
|
||||
****************************************************************************//**
|
||||
*
|
||||
* The function is called during device startup. Once project compiled as part of
|
||||
* the PSoC Creator project, the Cy_SystemInit() function is generated by the
|
||||
* PSoC Creator.
|
||||
*
|
||||
* The function generated by PSoC Creator performs all of the necessary device
|
||||
* configuration based on the design settings. This includes settings from the
|
||||
* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
|
||||
* configuration that is necessary.
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK void Cy_SystemInit(void)
|
||||
{
|
||||
/* Empty weak function. The actual implementation to be in the PSoC Creator
|
||||
* generated strong function.
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SystemCoreClockUpdate
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
|
||||
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
|
||||
*
|
||||
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
|
||||
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t srcFreqHz;
|
||||
uint32_t pathFreqHz;
|
||||
uint32_t fastClkDiv;
|
||||
uint32_t periClkDiv;
|
||||
uint32_t rootPath;
|
||||
uint32_t srcClk;
|
||||
|
||||
/* Get root path clock for the high-frequency clock # 0 */
|
||||
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
|
||||
|
||||
/* Get source of the root path clock */
|
||||
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
|
||||
|
||||
/* Get frequency of the source */
|
||||
switch (srcClk)
|
||||
{
|
||||
case CY_ROOT_PATH_SRC_IMO:
|
||||
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
|
||||
break;
|
||||
|
||||
case CY_ROOT_PATH_SRC_EXT:
|
||||
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
|
||||
break;
|
||||
|
||||
#if (SRSS_ECO_PRESENT == 1U)
|
||||
case CY_ROOT_PATH_SRC_ECO:
|
||||
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
|
||||
break;
|
||||
#endif /* (SRSS_ECO_PRESENT == 1U) */
|
||||
|
||||
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
|
||||
case CY_ROOT_PATH_SRC_ALTHF:
|
||||
srcFreqHz = cy_BleEcoClockFreqHz;
|
||||
break;
|
||||
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
|
||||
|
||||
case CY_ROOT_PATH_SRC_DSI_MUX:
|
||||
{
|
||||
uint32_t dsi_src;
|
||||
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
|
||||
switch (dsi_src)
|
||||
{
|
||||
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
|
||||
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
|
||||
break;
|
||||
|
||||
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
|
||||
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
|
||||
break;
|
||||
|
||||
#if (SRSS_ALTLF_PRESENT == 1U)
|
||||
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
|
||||
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
|
||||
break;
|
||||
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
|
||||
|
||||
#if (SRSS_PILO_PRESENT == 1U)
|
||||
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
|
||||
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
|
||||
break;
|
||||
#endif /* (SRSS_PILO_PRESENT == 1U) */
|
||||
|
||||
default:
|
||||
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rootPath == 0UL)
|
||||
{
|
||||
/* FLL */
|
||||
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
|
||||
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
|
||||
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
|
||||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
|
||||
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
|
||||
{
|
||||
uint32_t fllMult;
|
||||
uint32_t refDiv;
|
||||
uint32_t outputDiv;
|
||||
|
||||
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
|
||||
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
|
||||
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
|
||||
|
||||
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
|
||||
}
|
||||
else
|
||||
{
|
||||
pathFreqHz = srcFreqHz;
|
||||
}
|
||||
}
|
||||
else if ((rootPath == 1UL) || (rootPath == 2UL))
|
||||
{
|
||||
/* PLL */
|
||||
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
|
||||
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
|
||||
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
|
||||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
|
||||
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
|
||||
{
|
||||
uint32_t feedbackDiv;
|
||||
uint32_t referenceDiv;
|
||||
uint32_t outputDiv;
|
||||
|
||||
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
|
||||
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
|
||||
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
|
||||
|
||||
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
pathFreqHz = srcFreqHz;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Direct */
|
||||
pathFreqHz = srcFreqHz;
|
||||
}
|
||||
|
||||
/* Get frequency after hf_clk pre-divider */
|
||||
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
|
||||
cy_Hfclk0FreqHz = pathFreqHz;
|
||||
|
||||
/* Fast Clock Divider */
|
||||
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
|
||||
|
||||
/* Peripheral Clock Divider */
|
||||
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
|
||||
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
|
||||
|
||||
pathFreqHz = pathFreqHz / fastClkDiv;
|
||||
SystemCoreClock = pathFreqHz;
|
||||
|
||||
/* Sets clock frequency for Delay API */
|
||||
cy_delayFreqHz = SystemCoreClock;
|
||||
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
|
||||
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
|
||||
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SystemInitFpuEnable
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Enables the FPU if it is used. The function is called from the startup file.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SystemInitFpuEnable(void)
|
||||
{
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
uint32_t interruptState;
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
|
||||
__DSB();
|
||||
__ISB();
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
|
||||
}
|
||||
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysIpcPipeIsrCm4
|
||||
****************************************************************************//**
|
||||
*
|
||||
* This is the interrupt service routine for the system pipe.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysIpcPipeIsrCm4(void)
|
||||
{
|
||||
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_MemorySymbols
|
||||
****************************************************************************//**
|
||||
*
|
||||
* The intention of the function is to declare boundaries of the memories for the
|
||||
* MDK compilers. For the rest of the supported compilers, this is done using
|
||||
* linker configuration files. The following symbols used by the cymcuelftool.
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
|
||||
__asm void Cy_MemorySymbols(void)
|
||||
{
|
||||
/* Flash */
|
||||
EXPORT __cy_memory_0_start
|
||||
EXPORT __cy_memory_0_length
|
||||
EXPORT __cy_memory_0_row_size
|
||||
|
||||
/* Working Flash */
|
||||
EXPORT __cy_memory_1_start
|
||||
EXPORT __cy_memory_1_length
|
||||
EXPORT __cy_memory_1_row_size
|
||||
|
||||
/* Supervisory Flash */
|
||||
EXPORT __cy_memory_2_start
|
||||
EXPORT __cy_memory_2_length
|
||||
EXPORT __cy_memory_2_row_size
|
||||
|
||||
/* XIP */
|
||||
EXPORT __cy_memory_3_start
|
||||
EXPORT __cy_memory_3_length
|
||||
EXPORT __cy_memory_3_row_size
|
||||
|
||||
/* eFuse */
|
||||
EXPORT __cy_memory_4_start
|
||||
EXPORT __cy_memory_4_length
|
||||
EXPORT __cy_memory_4_row_size
|
||||
|
||||
/* Flash */
|
||||
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
|
||||
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
|
||||
__cy_memory_0_row_size EQU 0x200
|
||||
|
||||
/* Flash region for EEPROM emulation */
|
||||
__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
|
||||
__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
|
||||
__cy_memory_1_row_size EQU 0x200
|
||||
|
||||
/* Supervisory Flash */
|
||||
__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
|
||||
__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
|
||||
__cy_memory_2_row_size EQU 0x200
|
||||
|
||||
/* XIP */
|
||||
__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
|
||||
__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
|
||||
__cy_memory_3_row_size EQU 0x200
|
||||
|
||||
/* eFuse */
|
||||
__cy_memory_4_start EQU __cpp(0x90700000)
|
||||
__cy_memory_4_length EQU __cpp(0x100000)
|
||||
__cy_memory_4_row_size EQU __cpp(1)
|
||||
}
|
||||
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,680 @@
|
||||
/***************************************************************************//**
|
||||
* \file system_psoc6.h
|
||||
* \version 2.60
|
||||
*
|
||||
* \brief Device system header file.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _SYSTEM_PSOC6_H_
|
||||
#define _SYSTEM_PSOC6_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config
|
||||
* \{
|
||||
* Provides device startup, system configuration, and linker script files.
|
||||
* The system startup provides the followings features:
|
||||
* - See \ref group_system_config_device_initialization for the:
|
||||
* * \ref group_system_config_dual_core_device_initialization
|
||||
* * \ref group_system_config_single_core_device_initialization
|
||||
* - \ref group_system_config_device_memory_definition
|
||||
* - \ref group_system_config_heap_stack_config
|
||||
* - \ref group_system_config_merge_apps
|
||||
* - \ref group_system_config_default_handlers
|
||||
* - \ref group_system_config_device_vector_table
|
||||
* - \ref group_system_config_cm4_functions
|
||||
*
|
||||
* \section group_system_config_configuration Configuration Considerations
|
||||
*
|
||||
* \subsection group_system_config_device_memory_definition Device Memory Definition
|
||||
* The flash and RAM allocation for each CPU is defined by the linker scripts.
|
||||
* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
|
||||
* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
|
||||
* For Single-Core devices the system reserves additional 80 bytes of RAM.
|
||||
* Using the reserved memory area for other purposes will lead to unexpected behavior.
|
||||
*
|
||||
* \note The linker files provided with the PDL are generic and handle all common
|
||||
* use cases. Your project may not use every section defined in the linker files.
|
||||
* In that case you may see warnings during the build process. To eliminate build
|
||||
* warnings in your project, you can simply comment out or remove the relevant
|
||||
* code in the linker file.
|
||||
*
|
||||
* <b>ARM GCC</b>\n
|
||||
* The flash and RAM sections for the CPU are defined in the linker files:
|
||||
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
|
||||
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
|
||||
* \note If the start of the Cortex-M4 application image is changed, the value
|
||||
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
|
||||
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
|
||||
* Cy_SysEnableCM4() function call.
|
||||
*
|
||||
* Change the flash and RAM sizes by editing the macros value in the
|
||||
* linker files for both CPUs:
|
||||
* - 'xx_cm0plus.ld', where 'xx' is the device group:
|
||||
* \code
|
||||
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
|
||||
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
|
||||
* \endcode
|
||||
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
|
||||
* \code
|
||||
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
|
||||
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
|
||||
* \endcode
|
||||
*
|
||||
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
|
||||
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
|
||||
* by either:
|
||||
* - Passing the following commands to the compiler:\n
|
||||
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
|
||||
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
|
||||
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
|
||||
*
|
||||
* <b>ARM MDK</b>\n
|
||||
* The flash and RAM sections for the CPU are defined in the linker files:
|
||||
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
|
||||
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
|
||||
* \note If the start of the Cortex-M4 application image is changed, the value
|
||||
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
|
||||
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
|
||||
* Cy_SysEnableCM4() function call.
|
||||
*
|
||||
* \note The linker files provided with the PDL are generic and handle all common
|
||||
* use cases. Your project may not use every section defined in the linker files.
|
||||
* In that case you may see the warnings during the build process:
|
||||
* L6314W (no section matches pattern) and/or L6329W
|
||||
* (pattern only matches removed unused sections). In your project, you can
|
||||
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
|
||||
* the linker. You can also comment out or remove the relevant code in the linker
|
||||
* file.
|
||||
*
|
||||
* Change the flash and RAM sizes by editing the macros value in the
|
||||
* linker files for both CPUs:
|
||||
* - 'xx_cm0plus.scat', where 'xx' is the device group:
|
||||
* \code
|
||||
* #define FLASH_START 0x10000000
|
||||
* #define FLASH_SIZE 0x00080000
|
||||
* #define RAM_START 0x08000000
|
||||
* #define RAM_SIZE 0x00024000
|
||||
* \endcode
|
||||
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
|
||||
* \code
|
||||
* #define FLASH_START 0x10080000
|
||||
* #define FLASH_SIZE 0x00080000
|
||||
* #define RAM_START 0x08024000
|
||||
* #define RAM_SIZE 0x00023800
|
||||
* \endcode
|
||||
*
|
||||
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
|
||||
* value in the 'xx_cm4_dual.scat' file,
|
||||
* where 'xx' is the device group. Do this by either:
|
||||
* - Passing the following commands to the compiler:\n
|
||||
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
|
||||
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
|
||||
* 'xx' is device family:\n
|
||||
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
|
||||
*
|
||||
* <b>IAR</b>\n
|
||||
* The flash and RAM sections for the CPU are defined in the linker files:
|
||||
* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
|
||||
* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
|
||||
* \note If the start of the Cortex-M4 application image is changed, the value
|
||||
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
|
||||
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
|
||||
* Cy_SysEnableCM4() function call.
|
||||
*
|
||||
* Change the flash and RAM sizes by editing the macros value in the
|
||||
* linker files for both CPUs:
|
||||
* - 'xx_cm0plus.icf', where 'xx' is the device group:
|
||||
* \code
|
||||
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
|
||||
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
|
||||
* \endcode
|
||||
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
|
||||
* \code
|
||||
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
|
||||
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
|
||||
* \endcode
|
||||
*
|
||||
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
|
||||
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
|
||||
* is the device group. Do this by either:
|
||||
* - Passing the following commands to the compiler:\n
|
||||
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
|
||||
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
|
||||
* 'xx' is device family:\n
|
||||
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
|
||||
*
|
||||
* \subsection group_system_config_device_initialization Device Initialization
|
||||
* After a power-on-reset (POR), the boot process is handled by the boot code
|
||||
* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
|
||||
* code passes the control to the Cortex-M0+ startup code located in flash.
|
||||
*
|
||||
* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
|
||||
* The Cortex-M0+ startup code performs the device initialization by a call to
|
||||
* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
|
||||
* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
|
||||
* See \ref group_system_config_cm4_functions for more details.
|
||||
* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
|
||||
* The function has a separate implementation on each core.
|
||||
* Both function implementations unlock and disable the WDT.
|
||||
* Therefore enable the WDT after both cores have been initialized.
|
||||
*
|
||||
* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
|
||||
* The Cortex-M0+ core is not user-accessible on these devices. In this case the
|
||||
* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
|
||||
*
|
||||
* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
|
||||
* There are two ways to adjust heap and stack configurations:
|
||||
* -# Editing source code files
|
||||
* -# Specifying via command line
|
||||
*
|
||||
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
|
||||
*
|
||||
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
|
||||
* - <b>Editing source code files</b>\n
|
||||
* The heap and stack sizes are defined in the assembler startup files
|
||||
* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
|
||||
* Change the heap and stack sizes by modifying the following lines:\n
|
||||
* \code .equ Stack_Size, 0x00001000 \endcode
|
||||
* \code .equ Heap_Size, 0x00000400 \endcode
|
||||
*
|
||||
* - <b>Specifying via command line</b>\n
|
||||
* Change the heap and stack sizes passing the following commands to the compiler:\n
|
||||
* \code -D __STACK_SIZE=0x000000400 \endcode
|
||||
* \code -D __HEAP_SIZE=0x000000100 \endcode
|
||||
*
|
||||
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
|
||||
* - <b>Editing source code files</b>\n
|
||||
* The heap and stack sizes are defined in the assembler startup files
|
||||
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
|
||||
* Change the heap and stack sizes by modifying the following lines:\n
|
||||
* \code Stack_Size EQU 0x00001000 \endcode
|
||||
* \code Heap_Size EQU 0x00000400 \endcode
|
||||
*
|
||||
* - <b>Specifying via command line</b>\n
|
||||
* Change the heap and stack sizes passing the following commands to the assembler:\n
|
||||
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
|
||||
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
|
||||
*
|
||||
* \subsubsection group_system_config_heap_stack_config_iar IAR
|
||||
* - <b>Editing source code files</b>\n
|
||||
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
|
||||
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
|
||||
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
|
||||
* Change the heap and stack sizes by modifying the following lines:\n
|
||||
* \code Stack_Size EQU 0x00001000 \endcode
|
||||
* \code Heap_Size EQU 0x00000400 \endcode
|
||||
*
|
||||
* - <b>Specifying via command line</b>\n
|
||||
* Change the heap and stack sizes passing the following commands to the
|
||||
* linker (including quotation marks):\n
|
||||
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
|
||||
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
|
||||
*
|
||||
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
|
||||
* The CM0+ project and linker script build the CM0+ application image. Similarly,
|
||||
* the CM4 linker script builds the CM4 application image. Each specifies
|
||||
* locations, sizes, and contents of sections in memory. See
|
||||
* \ref group_system_config_device_memory_definition for the symbols and default
|
||||
* values.
|
||||
*
|
||||
* The cymcuelftool is invoked by a post-build command. The precise project
|
||||
* setting is IDE-specific.
|
||||
*
|
||||
* The cymcuelftool combines the two executables. The tool examines the
|
||||
* executables to ensure that memory regions either do not overlap, or contain
|
||||
* identical bytes (shared). If there are no problems, it creates a new ELF file
|
||||
* with the merged image, without changing any of the addresses or data.
|
||||
*
|
||||
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
|
||||
* The default interrupt handler functions are defined as weak functions to a dummy
|
||||
* handler in the startup file. The naming convention for the interrupt handler names
|
||||
* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
|
||||
* user code by defining the handler function using the same name. For example:
|
||||
* \code
|
||||
* void scb_0_interrupt_IRQHandler(void)
|
||||
*{
|
||||
* ...
|
||||
*}
|
||||
* \endcode
|
||||
*
|
||||
* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
|
||||
* This process uses memory sections defined in the linker script. The startup
|
||||
* code actually defines the contents of the vector table and performs the copy.
|
||||
* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
|
||||
* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
|
||||
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
|
||||
* It defines sections and locations in memory.\n
|
||||
* Copy interrupt vectors from flash to RAM: \n
|
||||
* From: \code LONG (__Vectors) \endcode
|
||||
* To: \code LONG (__ram_vectors_start__) \endcode
|
||||
* Size: \code LONG (__Vectors_End - __Vectors) \endcode
|
||||
* The vector table address (and the vector table itself) are defined in the
|
||||
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
|
||||
* The code in these files copies the vector table from Flash to RAM.
|
||||
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
|
||||
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
|
||||
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
|
||||
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
|
||||
* (RESET_RAM) shall be first in the RAM section.\n
|
||||
* RESET_RAM represents the vector table. It is defined in the assembler startup
|
||||
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
|
||||
* The code in these files copies the vector table from Flash to RAM.
|
||||
*
|
||||
* \subsubsection group_system_config_device_vector_table_iar IAR
|
||||
* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
|
||||
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
|
||||
* This file defines the .intvec_ram section and its location.
|
||||
* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
|
||||
* The vector table address (and the vector table itself) are defined in the
|
||||
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
|
||||
* The code in these files copies the vector table from Flash to RAM.
|
||||
*
|
||||
* \section group_system_config_more_information More Information
|
||||
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
|
||||
* more details.
|
||||
*
|
||||
* \section group_system_config_MISRA MISRA Compliance
|
||||
*
|
||||
* <table class="doxtable">
|
||||
* <tr>
|
||||
* <th>MISRA Rule</th>
|
||||
* <th>Rule Class (Required/Advisory)</th>
|
||||
* <th>Rule Description</th>
|
||||
* <th>Description of Deviation(s)</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.3</td>
|
||||
* <td>R</td>
|
||||
* <td>The character sequence // shall not be used within a comment.</td>
|
||||
* <td>The comments provide a useful WEB link to the documentation.</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
* \section group_system_config_changelog Changelog
|
||||
* <table class="doxtable">
|
||||
* <tr>
|
||||
* <th>Version</th>
|
||||
* <th>Changes</th>
|
||||
* <th>Reason for Change</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.60</td>
|
||||
* <td>Updated linker scripts.</td>
|
||||
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.50</td>
|
||||
* <td>Updated assembler files, C files, linker scripts.</td>
|
||||
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.40</td>
|
||||
* <td>Updated assembler files, C files, linker scripts.</td>
|
||||
* <td>Added Arm Compiler 6 support.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td rowspan="2">2.30</td>
|
||||
* <td>Added assembler files, linker scripts for Mbed OS.</td>
|
||||
* <td>Added Arm Mbed OS embedded operating system support.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
|
||||
* <td>Enhanced PDL usability.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.20</td>
|
||||
* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
|
||||
* <td>Changed the IPC driver configuration method from compile time to run time.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td rowspan="2"> 2.10</td>
|
||||
* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
|
||||
* Removed $Sub$$main symbol for ARM MDK compiler.
|
||||
* </td>
|
||||
* <td>uVision Debugger support.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Updated description of the Startup behavior for Single-Core Devices. \n
|
||||
* Added note about WDT disabling by SystemInit() function.
|
||||
* </td>
|
||||
* <td>Documentation improvement.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td rowspan="4"> 2.0</td>
|
||||
* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
|
||||
* Single core device support.
|
||||
* </td>
|
||||
* <td></td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
|
||||
* Renamed 'wflash' memory region to 'em_eeprom'.
|
||||
* </td>
|
||||
* <td>Linker scripts usability improvement.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
|
||||
* <td>Reserved system resources for internal operations.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
|
||||
* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>1.0</td>
|
||||
* <td>Initial version</td>
|
||||
* <td></td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \defgroup group_system_config_macro Macro
|
||||
* \{
|
||||
* \defgroup group_system_config_system_macro System
|
||||
* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
|
||||
* \defgroup group_system_config_user_settings_macro User Settings
|
||||
* \}
|
||||
* \defgroup group_system_config_functions Functions
|
||||
* \{
|
||||
* \defgroup group_system_config_system_functions System
|
||||
* \defgroup group_system_config_cm4_functions Cortex-M4 Control
|
||||
* \}
|
||||
* \defgroup group_system_config_globals Global Variables
|
||||
*
|
||||
* \}
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_system_functions
|
||||
* \{
|
||||
* \details
|
||||
* The following system functions implement CMSIS Core functions.
|
||||
* Refer to the [CMSIS documentation]
|
||||
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
|
||||
* for more details.
|
||||
* \}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global preprocessor symbols/macros ('define')
|
||||
*******************************************************************************/
|
||||
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
|
||||
(defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
|
||||
#define CY_SYSTEM_CPU_CM0P 1UL
|
||||
#else
|
||||
#define CY_SYSTEM_CPU_CM0P 0UL
|
||||
#endif
|
||||
|
||||
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
|
||||
#include "cyfitter.h"
|
||||
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
|
||||
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* START OF USER SETTINGS HERE
|
||||
* ===========================
|
||||
*
|
||||
* All lines with '<<<' can be set by user.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_user_settings_macro
|
||||
* \{
|
||||
*/
|
||||
|
||||
#if defined (CYDEV_CLK_EXTCLK__HZ)
|
||||
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
|
||||
#else
|
||||
/***************************************************************************//**
|
||||
* External Clock Frequency (in Hz, [value]UL). If compiled within
|
||||
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
|
||||
* Otherwise, edit the value below.
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
|
||||
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
|
||||
|
||||
|
||||
#if defined (CYDEV_CLK_ECO__HZ)
|
||||
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
|
||||
#else
|
||||
/***************************************************************************//**
|
||||
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
|
||||
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
|
||||
* used.
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
|
||||
#endif /* (CYDEV_CLK_ECO__HZ) */
|
||||
|
||||
|
||||
#if defined (CYDEV_CLK_ALTHF__HZ)
|
||||
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
|
||||
#else
|
||||
/***************************************************************************//**
|
||||
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
|
||||
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
|
||||
* Otherwise, edit the value below.
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
|
||||
#endif /* (CYDEV_CLK_ALTHF__HZ) */
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* \brief Start address of the Cortex-M4 application ([address]UL)
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#if !defined (CY_CORTEX_M4_APPL_ADDR)
|
||||
#define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
|
||||
#endif /* (CY_CORTEX_M4_APPL_ADDR) */
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* \brief IPC Semaphores allocation ([value]UL).
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* \brief IPC Pipe definitions ([value]UL).
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* END OF USER SETTINGS HERE
|
||||
* =========================
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/** \} group_system_config_user_settings_macro */
|
||||
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_system_macro
|
||||
* \{
|
||||
*/
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
|
||||
/** The Cortex-M0+ startup driver identifier */
|
||||
#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
|
||||
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
|
||||
/** The Cortex-M4 startup driver identifier */
|
||||
#define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
|
||||
#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
|
||||
|
||||
/** \} group_system_config_system_macro */
|
||||
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_system_functions
|
||||
* \{
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/** \} group_system_config_system_functions */
|
||||
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_cm4_functions
|
||||
* \{
|
||||
*/
|
||||
extern uint32_t Cy_SysGetCM4Status(void);
|
||||
extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
|
||||
extern void Cy_SysDisableCM4(void);
|
||||
extern void Cy_SysRetainCM4(void);
|
||||
extern void Cy_SysResetCM4(void);
|
||||
/** \} group_system_config_cm4_functions */
|
||||
|
||||
|
||||
/** \cond */
|
||||
extern void Default_Handler (void);
|
||||
|
||||
void Cy_SysIpcPipeIsrCm0(void);
|
||||
void Cy_SysIpcPipeIsrCm4(void);
|
||||
|
||||
extern void Cy_SystemInit(void);
|
||||
extern void Cy_SystemInitFpuEnable(void);
|
||||
|
||||
extern uint32_t cy_delayFreqHz;
|
||||
extern uint32_t cy_delayFreqKhz;
|
||||
extern uint8_t cy_delayFreqMhz;
|
||||
extern uint32_t cy_delay32kMs;
|
||||
/** \endcond */
|
||||
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
|
||||
/**
|
||||
* \addtogroup group_system_config_cm4_status_macro
|
||||
* \{
|
||||
*/
|
||||
#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
|
||||
#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
|
||||
#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
|
||||
#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
|
||||
/** \} group_system_config_cm4_status_macro */
|
||||
|
||||
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC Configuration
|
||||
* =========================
|
||||
*******************************************************************************/
|
||||
/* IPC CY_PIPE default configuration */
|
||||
#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
|
||||
|
||||
#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
|
||||
#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
|
||||
#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
|
||||
|
||||
#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
|
||||
#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* The System pipe configuration defines the IPC channel number, interrupt
|
||||
* number, and the pipe interrupt mask for the endpoint.
|
||||
*
|
||||
* The format of the endPoint configuration
|
||||
* Bits[31:16] Interrupt Mask
|
||||
* Bits[15:8 ] IPC interrupt
|
||||
* Bits[ 7:0 ] IPC channel
|
||||
*/
|
||||
|
||||
/* System Pipe addresses */
|
||||
/* CyPipe defines */
|
||||
|
||||
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
|
||||
|
||||
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
|
||||
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
|
||||
| CY_IPC_CHAN_CYPIPE_EP0)
|
||||
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
|
||||
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
|
||||
| CY_IPC_CHAN_CYPIPE_EP1)
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
/** \addtogroup group_system_config_globals
|
||||
* \{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock;
|
||||
extern uint32_t cy_BleEcoClockFreqHz;
|
||||
extern uint32_t cy_Hfclk0FreqHz;
|
||||
extern uint32_t cy_PeriClkFreqHz;
|
||||
|
||||
/** \} group_system_config_globals */
|
||||
|
||||
|
||||
|
||||
/** \cond INTERNAL */
|
||||
/*******************************************************************************
|
||||
* Backward compatibility macro. The following code is DEPRECATED and must
|
||||
* not be used in new projects
|
||||
*******************************************************************************/
|
||||
|
||||
/* BWC defines for functions related to enter/exit critical section */
|
||||
#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
|
||||
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
|
||||
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
|
||||
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
|
||||
|
||||
/** \endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_PSOC6_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
Reference in New Issue
Block a user