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Import Mbed OS hard-float snapshot

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Beslan
2026-06-01 20:15:04 +03:00
commit d3738e2f89
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119
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
RTC_CLKIN = 2
} RTCName;
typedef enum {
UART_0 = (int)UART0_BASE,
UART_1 = (int)UART1_BASE,
UART_2 = (int)UART2_BASE
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
typedef enum {
I2C_0 = (int)I2C0_BASE,
I2C_1 = (int)I2C1_BASE,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0
PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
} PWMName;
#define CHANNELS_A_SHIFT 5
typedef enum {
ADC0_SE0 = 0,
ADC0_SE3 = 3,
ADC0_SE4a = (1 << CHANNELS_A_SHIFT) | (4),
ADC0_SE4b = 4,
ADC0_SE5b = 5,
ADC0_SE6b = 6,
ADC0_SE7a = (1 << CHANNELS_A_SHIFT) | (7),
ADC0_SE7b = 7,
ADC0_SE8 = 8,
ADC0_SE9 = 9,
ADC0_SE11 = 11,
ADC0_SE12 = 12,
ADC0_SE13 = 13,
ADC0_SE14 = 14,
ADC0_SE15 = 15,
ADC0_SE23 = 23
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = (int)SPI0_BASE,
SPI_1 = (int)SPI1_BASE,
} SPIName;
// Default peripherals
#define MBED_SPI0 PTD2, PTD3, PTD1, PTD0
#define MBED_UART0 PTC4, PTC3
#define MBED_UART1 PTD3, PTD2
#define MBED_UARTUSB PTA2, PTA1
#define MBED_I2C0 PTC9, PTC8
#define MBED_I2C1 PTE1, PTE0
#define MBED_ANALOGOUT0 PTE30
#define MBED_ANALOGIN0 PTC2
#define MBED_ANALOGIN1 PTB3
#define MBED_ANALOGIN2 PTB2
#define MBED_ANALOGIN3 PTB1
#define MBED_ANALOGIN4 PTB0
#define MBED_PWMOUT0 PTD4
#define MBED_PWMOUT1 PTA12
#define MBED_PWMOUT2 PTA4
#define MBED_PWMOUT3 PTA5
#define MBED_PWMOUT4 PTC8
#define MBED_PWMOUT5 PTC9
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralPins.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{PTC1, RTC_CLKIN, 1},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTE20, ADC0_SE0, 0},
{PTE22, ADC0_SE3, 0},
{PTE21, ADC0_SE4a, 0},
{PTE29, ADC0_SE4b, 0},
{PTE30, ADC0_SE23, 0},
{PTE23, ADC0_SE7a, 0},
{PTB0, ADC0_SE8, 0},
{PTB1, ADC0_SE9, 0},
{PTB2, ADC0_SE12, 0},
{PTB3, ADC0_SE13, 0},
{PTC0, ADC0_SE14, 0},
{PTC1, ADC0_SE15, 0},
{PTC2, ADC0_SE11, 0},
{PTD1, ADC0_SE5b, 0},
{PTD5, ADC0_SE6b, 0},
{PTD6, ADC0_SE7b, 0},
{NC, NC, 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PTE30, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTE25, I2C_0, 5},
{PTC9, I2C_0, 2},
{PTE0, I2C_1, 6},
{PTB1, I2C_0, 2},
{PTB3, I2C_0, 2},
{PTC11, I2C_1, 2},
{PTC2, I2C_1, 2},
{PTA4, I2C_1, 2},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTE24, I2C_0, 5},
{PTC8, I2C_0, 2},
{PTE1, I2C_1, 6},
{PTB0, I2C_0, 2},
{PTB2, I2C_0, 2},
{PTC10, I2C_1, 2},
{PTC1, I2C_1, 2},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTC4, UART_1, 3},
{PTA2, UART_0, 2},
{PTD5, UART_2, 3},
{PTD3, UART_2, 3},
{PTD7, UART_0, 3},
{PTE20, UART_0, 4},
{PTE22, UART_2, 4},
{PTE0, UART_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTC3, UART_1, 3},
{PTA1, UART_0, 2},
{PTD4, UART_2, 3},
{PTD2, UART_2, 3},
{PTD6, UART_0, 3},
{PTE23, UART_2, 4},
{PTE21, UART_0, 4},
{PTE1, UART_1, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTA15, SPI_0, 2},
{PTB11, SPI_1, 2},
{PTC5, SPI_0, 2},
{PTD1, SPI_0, 2},
{PTD5, SPI_1, 2},
{PTE2, SPI_1, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTA16, SPI_0, 2},
{PTA17, SPI_0, 5},
{PTB16, SPI_1, 2},
{PTB17, SPI_1, 5},
{PTC6, SPI_0, 2},
{PTC7, SPI_0, 5},
{PTD2, SPI_0, 2},
{PTD3, SPI_0, 5},
{PTD6, SPI_1, 2},
{PTD7, SPI_1, 5},
{PTE1, SPI_1, 2},
{PTE3, SPI_1, 5},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTA16, SPI_0, 5},
{PTA17, SPI_0, 2},
{PTB16, SPI_1, 5},
{PTB17, SPI_1, 2},
{PTC6, SPI_0, 5},
{PTC7, SPI_0, 2},
{PTD2, SPI_0, 5},
{PTD3, SPI_0, 2},
{PTD6, SPI_1, 5},
{PTD7, SPI_1, 2},
{PTE1, SPI_1, 5},
{PTE3, SPI_1, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTA14, SPI_0, 2},
{PTB10, SPI_1, 2},
{PTC4, SPI_0, 2},
{PTD0, SPI_0, 2},
{PTD4, SPI_1, 2},
{PTE4, SPI_1, 2},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5
{PTA1, PWM_9 , 3}, // PTA1 , TPM2 CH0
{PTA2, PWM_10, 3}, // PTA2 , TPM2 CH1
{PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0
{PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1
{PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2
{PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0
{PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1
{PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0
{PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1
{PTB2, PWM_9, 3}, // PTB2 , TPM2 CH0
{PTB3, PWM_10, 3}, // PTB3 , TPM2 CH1
{PTB18, PWM_9, 3}, // PTB18, TPM2 CH0
{PTB19, PWM_10, 3}, // PTB18, TPM2 CH1
{PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0
{PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1
{PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2
{PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3
{PTC8, PWM_5 , 3}, // PTC8 , TPM0 CH4
{PTC9, PWM_6 , 3}, // PTC9 , TPM0 CH5
{PTD0, PWM_1 , 4}, // PTD0 , TPM0 CH0
{PTD1, PWM_2 , 4}, // PTD0 , TPM0 CH1
{PTD2, PWM_3 , 4}, // PTD2 , TPM0 CH2
{PTD3, PWM_4 , 4}, // PTD3 , TPM0 CH3
{PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4
{PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5
{PTE20, PWM_7, 3}, // PTE20, TPM1 CH0
{PTE21, PWM_8, 3}, // PTE21, TPM1 CH1
{PTE22, PWM_9, 3}, // PTE22, TPM2 CH0
{PTE23, PWM_10, 3}, // PTE23, TPM2 CH1
{PTE24, PWM_1, 3}, // PTE24, TPM0 CH0
{PTE25, PWM_2, 3}, // PTE25, TPM0 CH1
{PTE26, PWM_6, 3}, // PTE26, TPM0 CH5
{PTE29, PWM_3, 3}, // PTE29, TPM0 CH2
{PTE30, PWM_4, 3}, // PTE30, TPM0 CH3
{PTE31, PWM_5, 3}, // PTE31, TPM0 CH4
{NC , NC, 0}
};

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 12
typedef enum {
PTA0 = 0x0,
PTA1 = 0x4,
PTA2 = 0x8,
PTA3 = 0xc,
PTA4 = 0x10,
PTA5 = 0x14,
PTA6 = 0x18,
PTA7 = 0x1c,
PTA8 = 0x20,
PTA9 = 0x24,
PTA10 = 0x28,
PTA11 = 0x2c,
PTA12 = 0x30,
PTA13 = 0x34,
PTA14 = 0x38,
PTA15 = 0x3c,
PTA16 = 0x40,
PTA17 = 0x44,
PTA18 = 0x48,
PTA19 = 0x4c,
PTA20 = 0x50,
PTA21 = 0x54,
PTA22 = 0x58,
PTA23 = 0x5c,
PTA24 = 0x60,
PTA25 = 0x64,
PTA26 = 0x68,
PTA27 = 0x6c,
PTA28 = 0x70,
PTA29 = 0x74,
PTA30 = 0x78,
PTA31 = 0x7c,
PTB0 = 0x1000,
PTB1 = 0x1004,
PTB2 = 0x1008,
PTB3 = 0x100c,
PTB4 = 0x1010,
PTB5 = 0x1014,
PTB6 = 0x1018,
PTB7 = 0x101c,
PTB8 = 0x1020,
PTB9 = 0x1024,
PTB10 = 0x1028,
PTB11 = 0x102c,
PTB12 = 0x1030,
PTB13 = 0x1034,
PTB14 = 0x1038,
PTB15 = 0x103c,
PTB16 = 0x1040,
PTB17 = 0x1044,
PTB18 = 0x1048,
PTB19 = 0x104c,
PTB20 = 0x1050,
PTB21 = 0x1054,
PTB22 = 0x1058,
PTB23 = 0x105c,
PTB24 = 0x1060,
PTB25 = 0x1064,
PTB26 = 0x1068,
PTB27 = 0x106c,
PTB28 = 0x1070,
PTB29 = 0x1074,
PTB30 = 0x1078,
PTB31 = 0x107c,
PTC0 = 0x2000,
PTC1 = 0x2004,
PTC2 = 0x2008,
PTC3 = 0x200c,
PTC4 = 0x2010,
PTC5 = 0x2014,
PTC6 = 0x2018,
PTC7 = 0x201c,
PTC8 = 0x2020,
PTC9 = 0x2024,
PTC10 = 0x2028,
PTC11 = 0x202c,
PTC12 = 0x2030,
PTC13 = 0x2034,
PTC14 = 0x2038,
PTC15 = 0x203c,
PTC16 = 0x2040,
PTC17 = 0x2044,
PTC18 = 0x2048,
PTC19 = 0x204c,
PTC20 = 0x2050,
PTC21 = 0x2054,
PTC22 = 0x2058,
PTC23 = 0x205c,
PTC24 = 0x2060,
PTC25 = 0x2064,
PTC26 = 0x2068,
PTC27 = 0x206c,
PTC28 = 0x2070,
PTC29 = 0x2074,
PTC30 = 0x2078,
PTC31 = 0x207c,
PTD0 = 0x3000,
PTD1 = 0x3004,
PTD2 = 0x3008,
PTD3 = 0x300c,
PTD4 = 0x3010,
PTD5 = 0x3014,
PTD6 = 0x3018,
PTD7 = 0x301c,
PTD8 = 0x3020,
PTD9 = 0x3024,
PTD10 = 0x3028,
PTD11 = 0x302c,
PTD12 = 0x3030,
PTD13 = 0x3034,
PTD14 = 0x3038,
PTD15 = 0x303c,
PTD16 = 0x3040,
PTD17 = 0x3044,
PTD18 = 0x3048,
PTD19 = 0x304c,
PTD20 = 0x3050,
PTD21 = 0x3054,
PTD22 = 0x3058,
PTD23 = 0x305c,
PTD24 = 0x3060,
PTD25 = 0x3064,
PTD26 = 0x3068,
PTD27 = 0x306c,
PTD28 = 0x3070,
PTD29 = 0x3074,
PTD30 = 0x3078,
PTD31 = 0x307c,
PTE0 = 0x4000,
PTE1 = 0x4004,
PTE2 = 0x4008,
PTE3 = 0x400c,
PTE4 = 0x4010,
PTE5 = 0x4014,
PTE6 = 0x4018,
PTE7 = 0x401c,
PTE8 = 0x4020,
PTE9 = 0x4024,
PTE10 = 0x4028,
PTE11 = 0x402c,
PTE12 = 0x4030,
PTE13 = 0x4034,
PTE14 = 0x4038,
PTE15 = 0x403c,
PTE16 = 0x4040,
PTE17 = 0x4044,
PTE18 = 0x4048,
PTE19 = 0x404c,
PTE20 = 0x4050,
PTE21 = 0x4054,
PTE22 = 0x4058,
PTE23 = 0x405c,
PTE24 = 0x4060,
PTE25 = 0x4064,
PTE26 = 0x4068,
PTE27 = 0x406c,
PTE28 = 0x4070,
PTE29 = 0x4074,
PTE30 = 0x4078,
PTE31 = 0x407c,
LED_RED = PTB18,
LED_GREEN = PTB19,
LED_BLUE = PTD1,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_BLUE,
// USB Pins
USBTX = PTA2,
USBRX = PTA1,
// Arduino Headers
D0 = PTA1,
D1 = PTA2,
D2 = PTD4,
D3 = PTA12,
D4 = PTA4,
D5 = PTA5,
D6 = PTC8,
D7 = PTC9,
D8 = PTA13,
D9 = PTD5,
D10 = PTD0,
D11 = PTD2,
D12 = PTD3,
D13 = PTD1,
D14 = PTE0,
D15 = PTE1,
A0 = PTB0,
A1 = PTB1,
A2 = PTB2,
A3 = PTB3,
A4 = PTC2,
A5 = PTC1,
I2C_SCL = D15,
I2C_SDA = D14,
TSI_ELEC0 = PTB16,
TSI_ELEC1 = PTB17,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
/* PullDown not available for KL25 */
typedef enum {
PullNone = 0,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device.h Normal file
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/MKL25Z4.h Normal file
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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct Normal file
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#! armcc -E
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x20000
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 1FFFF000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x4000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
#define VECTOR_SIZE 0xC0
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S Normal file
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;/*****************************************************************************
; * @file: startup_MKL25Z4.s
; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
; * MKL25Z4
; * @version: 1.1
; * @date: 2012-6-21
; *
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
; *****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD Reserved20_IRQHandler ; Reserved interrupt 20
DCD FTFA_IRQHandler ; FTFA interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C0 interrupt 25
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD UART0_IRQHandler ; UART0 status/error interrupt
DCD UART1_IRQHandler ; UART1 status/error interrupt
DCD UART2_IRQHandler ; UART2 status/error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT_IRQHandler ; PIT timer interrupt
DCD Reserved39_IRQHandler ; Reserved interrupt 39
DCD USB0_IRQHandler ; USB0 interrupt
DCD DAC0_IRQHandler ; DAC interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved45_IRQHandler ; Reserved interrupt 45
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTD_IRQHandler ; Port D interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
; <1=> RESET pin is dedicated
; <o.3> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved39_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
DefaultISR
B .
ENDP
ALIGN
END

28
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/MKL25Z4.sct Normal file
View File

@@ -0,0 +1,28 @@
#! armcc -E
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
ER_IROM1 0x00000000 0x20000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 0x4000 - 0xC0 = 0x3F40
RW_IRAM1 0x1FFFF0C0 0x3F40 {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFFF000+0x4000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
}
ARM_LIB_STACK 0x1FFFF000+0x4000 EMPTY -Stack_Size { ; Stack region growing down
}
}

331
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_STD/startup_MKL25Z4.S Normal file
View File

@@ -0,0 +1,331 @@
;/*****************************************************************************
; * @file: startup_MKL25Z4.s
; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
; * MKL25Z4
; * @version: 1.1
; * @date: 2012-6-21
; *
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
;*
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD Reserved20_IRQHandler ; Reserved interrupt 20
DCD FTFA_IRQHandler ; FTFA interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C0 interrupt 25
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD UART0_IRQHandler ; UART0 status/error interrupt
DCD UART1_IRQHandler ; UART1 status/error interrupt
DCD UART2_IRQHandler ; UART2 status/error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT_IRQHandler ; PIT timer interrupt
DCD Reserved39_IRQHandler ; Reserved interrupt 39
DCD USB0_IRQHandler ; USB0 interrupt
DCD DAC0_IRQHandler ; DAC interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved45_IRQHandler ; Reserved interrupt 45
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTD_IRQHandler ; Port D interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
; <1=> RESET pin is dedicated
; <o.3> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved39_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
DefaultISR
B .
ENDP
ALIGN
END

170
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_ARM/MKL25Z4.ld Normal file
View File

@@ -0,0 +1,170 @@
/*
* KL25Z ARM GCC linker script file
*/
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
*(.text.Reset_Handler)
*(.text.System_Init)
. = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
. = ALIGN(8);
} > FLASH_PROTECTION
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

239
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.S Normal file
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/* KL25Z startup ARM GCC
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.2
* Date: 15 Nov 2011
*
* Copyright (c) 2011, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv6-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x80
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x80
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
.long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
.long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
.long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
.long Default_Handler /* Reserved interrupt 20 */
.long FTFA_IRQHandler /* FTFA interrupt */
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
.long LLW_IRQHandler /* Low Leakage Wakeup */
.long I2C0_IRQHandler /* I2C0 interrupt */
.long I2C1_IRQHandler /* I2C0 interrupt 25 */
.long SPI0_IRQHandler /* SPI0 interrupt */
.long SPI1_IRQHandler /* SPI1 interrupt */
.long UART0_IRQHandler /* UART0 status/error interrupt */
.long UART1_IRQHandler /* UART1 status/error interrupt */
.long UART2_IRQHandler /* UART2 status/error interrupt */
.long ADC0_IRQHandler /* ADC0 interrupt */
.long CMP0_IRQHandler /* CMP0 interrupt */
.long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
.long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
.long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
.long RTC_IRQHandler /* RTC interrupt */
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
.long PIT_IRQHandler /* PIT timer interrupt */
.long Default_Handler /* Reserved interrupt 39 */
.long USB0_IRQHandler /* USB0 interrupt */
.long DAC0_IRQHandler /* DAC interrupt */
.long TSI0_IRQHandler /* TSI0 interrupt */
.long MCG_IRQHandler /* MCG interrupt */
.long LPTimer_IRQHandler /* LPTimer interrupt */
.long Default_Handler /* Reserved interrupt 45 */
.long PORTA_IRQHandler /* Port A interrupt */
.long PORTD_IRQHandler /* Port D interrupt */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler FTFA_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler TPM0_IRQHandler
def_irq_default_handler TPM1_IRQHandler
def_irq_default_handler TPM2_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler DAC0_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler DEF_IRQHandler
/* Flash protection region, placed at 0x400 */
.text
.thumb
.align 2
.section .kinetis_flash_config_field,"a",%progbits
kinetis_flash_config:
.long 0xffffffff
.long 0xffffffff
.long 0xffffffff
.long 0xfffffffe
.end

45
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_IAR/MKL25Z4.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffff000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffff0bf;
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0;
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
/*-Sizes-*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0xC00;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_RAM2_start__ = 0x20000000;
define symbol __region_RAM2_end__ = 0x20002fff;
define symbol __FlashConfig_start__ = 0x00000400;
define symbol __FlashConfig_end__ = 0x0000040f;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in FlashConfig_region {section FlashConfig};
place in ROM_region { readonly };
place in RAM_region { readwrite, block HEAP, block CSTACK };

213
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_IAR/startup_MKL25Z4.S Normal file
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/**************************************************
*
* Copyright 2012 IAR Systems. All rights reserved.
*
* $Revision: 16 $
*
**************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:ROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
DCD FTFA_IRQHandler ; 5: FTFA
DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
DCD SPI0_IRQHandler ;10: SPI0 intertrupt
DCD SPI1_IRQHandler ;11: SPI1 intertrupt
DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
DCD ADC0_IRQHandler ;15: ADC 0 interrupt
DCD CMP0_IRQHandler ;16: CMP 0 interrupt
DCD TPM0_IRQHandler ;17: TPM 0 interrupt
DCD TPM1_IRQHandler ;18: TPM 1 interrupt
DCD TPM2_IRQHandler ;19: TPM 2 interrupt
DCD RTC_IRQHandler ;20: RTC Alarm interrupt
DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
DCD 0 ;23: Reserved
DCD USB0_IRQHandler ;24: USB OTG intertrupt
DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
DCD TSI0_IRQHandler ;26: TSI 0 interrupt
DCD MCG_IRQHandler ;27: MCG intertrupt
DCD LPTimer_IRQHandler ;28: LPTMR0 intertrupt
DCD 0 ;29: Reserved
DCD PORTA_IRQHandler ;30: PORT A interrupt
DCD PORTD_IRQHandler ;31: PORT D interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Flash Configuration
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
;;and security information that allows the MCU to restrict acces to the FTFL module.
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0^0xFF
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1^0xFF
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2^0xFF
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3^0xFF
FOPT EQU 0xFF
FSEC EQU 0xFE
SECTION FlashConfig:CONST:REORDER:ROOT(2)
Config:
DATA
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK SVC_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK DMA0_IRQHandler
PUBWEAK DMA1_IRQHandler
PUBWEAK DMA2_IRQHandler
PUBWEAK DMA3_IRQHandler
PUBWEAK FTFA_IRQHandler
PUBWEAK LVD_LVW_IRQHandler
PUBWEAK LLW_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK TPM0_IRQHandler
PUBWEAK TPM1_IRQHandler
PUBWEAK TPM2_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK RTC_Seconds_IRQHandler
PUBWEAK PIT_IRQHandler
PUBWEAK USB0_IRQHandler
PUBWEAK DAC0_IRQHandler
PUBWEAK TSI0_IRQHandler
PUBWEAK MCG_IRQHandler
PUBWEAK LPTimer_IRQHandler
PUBWEAK PORTA_IRQHandler
PUBWEAK PORTD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
THUMB
NMI_Handler
HardFault_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
Default_Handler
B Default_Handler
END

13
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/cmsis.h Normal file
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MKL25Z4.h"
#include "cmsis_nvic.h"
#endif

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFF000 // Vectors positioned at start of RAM
#endif

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/system_MKL25Z4.c Normal file
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/*
** ###################################################################
** Processor: MKL25Z128VLK4
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL25RM, Rev.1, Jun 2012
** Version: rev. 1.1, 2012-06-21
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-13)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
**
** ###################################################################
*/
/**
* @file MKL25Z4
* @version 1.1
* @date 2012-06-21
* @brief Device specific configuration file for MKL25Z4 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MKL25Z4.h"
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 13.98MHz
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 8MHz
Core clock = 48MHz, BusClock = 24MHz
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
Core clock = 8MHz, BusClock = 8MHz
3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
Reference clock source for MCG module is an external crystal 32.768kHz
Core clock = 47.97MHz, BusClock = 23.98MHz
This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
accuracy durring the reset period. RTC will reset on power down.
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
#elif (CLOCK_SETUP == 3)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
#endif /* (CLOCK_SETUP == 3) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
SIM->COPC = (uint32_t)0x00u;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x06U;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x00U;
/* MCG->C4: DMX32=0,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = (uint8_t)0x80U;
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00U;
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00U;
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 1)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
/* PORTA->PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
/* PORTA->PCR19: ISF=0,MUX=0 */
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
OSC0->CR = (uint8_t)0x89U;
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x24U;
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x9AU;
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
MCG->C5 = (uint8_t)0x01U;
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00U;
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x40U;
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x1AU;
while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
#elif (CLOCK_SETUP == 2)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
/* PORTA->PCR18: ISF=0,MUX=0 */
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
/* PORTA->PCR19: ISF=0,MUX=0 */
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
OSC0->CR = (uint8_t)0x89U;
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x24U;
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (uint8_t)0x9AU;
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00U;
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00U;
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to BLPE Mode */
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
MCG->C2 = (uint8_t)0x26U;
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
#elif (CLOCK_SETUP == 3)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* PORTA->PCR[3]: ISF=0,MUX=0 */
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA->PCR[4]: ISF=0,MUX=0 */
PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FEE Mode */
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=1,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
MCG_C4_DRST_DRS(0x02)
)) | (uint8_t)(
MCG_C4_DMX32_MASK |
MCG_C4_DRST_DRS(0x01)
));
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#endif /* (CLOCK_SETUP == 3) */
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
/* PLL is selected */
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/system_MKL25Z4.h Normal file
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/*
** ###################################################################
** Processor: MKL25Z128VLK4
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL25RM, Rev.1, Jun 2012
** Version: rev. 1.1, 2012-06-21
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-13)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
**
** ###################################################################
*/
/**
* @file MKL25Z4
* @version 1.1
* @date 2012-06-21
* @brief Device specific configuration file for MKL25Z4 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MKL25Z4_H_
#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "gpio_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 64
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
#define IRQ_DISABLED (0)
#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001};
static void handle_interrupt_in(PORT_Type *port, int ch_base) {
uint32_t isfr;
uint8_t location;
while((isfr = port->ISFR) != 0) {
location = 0;
for (int i = 0; i < 5; i++) {
if (!(isfr & (search_bits[i] << location)))
location += 1 << (4 - i);
}
uint32_t id = channel_ids[ch_base + location];
if (id == 0) {
continue;
}
FGPIO_Type *gpio;
gpio_irq_event event = IRQ_NONE;
switch (port->PCR[location] & PORT_PCR_IRQC_MASK) {
case IRQ_RAISING_EDGE:
event = IRQ_RISE;
break;
case IRQ_FALLING_EDGE:
event = IRQ_FALL;
break;
case IRQ_EITHER_EDGE:
gpio = (port == PORTA) ? (FPTA) : (FPTD);
event = (gpio->PDIR & (1 << location)) ? (IRQ_RISE) : (IRQ_FALL);
break;
}
if (event != IRQ_NONE) {
irq_handler(id, event);
}
port->ISFR = 1 << location;
}
}
void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);}
void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) return -1;
irq_handler = handler;
obj->port = pin >> PORT_SHIFT;
obj->pin = (pin & 0x7F) >> 2;
uint32_t ch_base, vector;
IRQn_Type irq_n;
switch (obj->port) {
case PortA:
ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
break;
case PortD:
ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD;
break;
default:
error("gpio_irq only supported on port A and D");
break;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
obj->ch = ch_base + obj->pin;
channel_ids[obj->ch] = id;
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
uint32_t irq_settings = IRQ_DISABLED;
switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
case IRQ_DISABLED:
if (enable) {
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
}
break;
case IRQ_RAISING_EDGE:
if (enable) {
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
} else {
if (event == IRQ_FALL)
irq_settings = IRQ_RAISING_EDGE;
}
break;
case IRQ_FALLING_EDGE:
if (enable) {
irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
} else {
if (event == IRQ_RISE)
irq_settings = IRQ_FALLING_EDGE;
}
break;
case IRQ_EITHER_EDGE:
if (enable) {
irq_settings = IRQ_EITHER_EDGE;
} else {
irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
}
break;
}
// Interrupt configuration and clear interrupt
port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
}
void gpio_irq_enable(gpio_irq_t *obj) {
if (obj->port == PortA) {
NVIC_EnableIRQ(PORTA_IRQn);
} else if (obj->port == PortD) {
NVIC_EnableIRQ(PORTD_IRQn);
}
}
void gpio_irq_disable(gpio_irq_t *obj) {
if (obj->port == PortA) {
NVIC_DisableIRQ(PORTA_IRQn);
} else if (obj->port == PortD) {
NVIC_DisableIRQ(PORTD_IRQn);
}
}

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/mbed_overrides.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
// called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//void mbed_sdk_init()
//{
//
//}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void)
{
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "serial_api.h"
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <string.h>
#include "cmsis.h"
#include "pinmap.h"
#include "clk_freqs.h"
#include "PeripheralPins.h"
//Devices either user UART0 or UARTLP
#ifndef UARTLP_BASES
#define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
#define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
#define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
#define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
#define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
#define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
#define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
#define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
#define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
#endif
#ifdef UART2
#define UART_NUM 3
#else
#define UART_NUM 1
#endif
/******************************************************************************
* INITIALIZATION
******************************************************************************/
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
void serial_init(serial_t *obj, PinName tx, PinName rx) {
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
obj->uart = (UARTLP_Type *)uart;
// enable clk
switch (uart) {
case UART_0: if (mcgpllfll_frequency() != 0) //PLL/FLL is selected
SIM->SOPT2 |= (1<<SIM_SOPT2_UART0SRC_SHIFT);
else
SIM->SOPT2 |= (2<<SIM_SOPT2_UART0SRC_SHIFT);
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
#if UART_NUM > 1
case UART_1: SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
case UART_2: SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
#endif
}
// Disable UART before changing registers
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
// Enable UART transmitter to ensure TX activity is finished
obj->uart->C2 |= UARTLP_C2_TE_MASK;
// Wait for TX activity to finish
while(!(obj->uart->S1 & UARTLP_S1_TC_MASK));
// Disbale UARTs again
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
switch (uart) {
case UART_0: obj->index = 0; break;
#if UART_NUM > 1
case UART_1: obj->index = 1; break;
case UART_2: obj->index = 2; break;
#endif
}
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// set rx/tx pins in PullUp mode and enable TX/RX
if (tx != NC) {
obj->uart->C2 |= UARTLP_C2_TE_MASK;
pin_mode(tx, PullUp);
}
if (rx != NC) {
obj->uart->C2 |= UARTLP_C2_RE_MASK;
pin_mode(rx, PullUp);
}
if (uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
serial_irq_ids[obj->index] = 0;
}
// serial_baud
//
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
// save C2 state
uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK));
// Disable UART before changing registers
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
uint32_t PCLK;
if (obj->uart == UART0) {
if (mcgpllfll_frequency() != 0)
PCLK = mcgpllfll_frequency();
else
PCLK = extosc_frequency();
} else
PCLK = bus_frequency();
// First we check to see if the basic divide with no DivAddVal/MulVal
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
// MulVal = 1. Otherwise, we search the valid ratio value range to find
// the closest match. This could be more elegant, using search methods
// and/or lookup tables, but the brute force method is not that much
// slower, and is more maintainable.
uint16_t DL = PCLK / (16 * baudrate);
// set BDH and BDL
obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
// restore C2 state
obj->uart->C2 |= c2_state;
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
MBED_ASSERT(data_bits == 8); // TODO: Support other number of data bits (also in the write method!)
// save C2 state
uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK));
// Disable UART before changing registers
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
uint8_t parity_enable, parity_select;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
default:
break;
}
stop_bits -= 1;
// data bits, parity and parity mode
obj->uart->C1 = ((parity_enable << 1)
| (parity_select << 0));
// stop bits
obj->uart->BDH &= ~UARTLP_BDH_SBNS_MASK;
obj->uart->BDH |= (stop_bits << UARTLP_BDH_SBNS_SHIFT);
// restore C2 state
obj->uart->C2 |= c2_state;
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint8_t status, uint32_t index) {
if (serial_irq_ids[index] != 0) {
if (status & UARTLP_S1_TDRE_MASK)
irq_handler(serial_irq_ids[index], TxIrq);
if (status & UARTLP_S1_RDRF_MASK)
irq_handler(serial_irq_ids[index], RxIrq);
}
}
void uart0_irq() {
uart_irq(UART0->S1, 0);
if (UART0->S1 & UARTLP_S1_OR_MASK)
UART0->S1 |= UARTLP_S1_OR_MASK;
}
#if UART_NUM > 1
void uart1_irq() {uart_irq(UART1->S1, 1);}
void uart2_irq() {uart_irq(UART2->S1, 2);}
#endif
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
#if UART_NUM > 1
case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
#endif
}
if (enable) {
switch (irq) {
case RxIrq: obj->uart->C2 |= (UARTLP_C2_RIE_MASK); break;
case TxIrq: obj->uart->C2 |= (UARTLP_C2_TIE_MASK); break;
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
switch (irq) {
case RxIrq: obj->uart->C2 &= ~(UARTLP_C2_RIE_MASK); break;
case TxIrq: obj->uart->C2 &= ~(UARTLP_C2_TIE_MASK); break;
}
switch (other_irq) {
case RxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_RIE_MASK)) == 0; break;
case TxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_TIE_MASK)) == 0; break;
}
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
return obj->uart->D;
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
obj->uart->D = c;
}
int serial_readable(serial_t *obj) {
// check overrun
if (obj->uart->S1 & UARTLP_S1_OR_MASK) {
obj->uart->S1 |= UARTLP_S1_OR_MASK;
}
return (obj->uart->S1 & UARTLP_S1_RDRF_MASK);
}
int serial_writable(serial_t *obj) {
// check overrun
if (obj->uart->S1 & UARTLP_S1_OR_MASK) {
obj->uart->S1 |= UARTLP_S1_OR_MASK;
}
return (obj->uart->S1 & UARTLP_S1_TDRE_MASK);
}
void serial_clear(serial_t *obj) {
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
obj->uart->C2 |= UARTLP_C2_SBK_MASK;
}
void serial_break_clear(serial_t *obj) {
obj->uart->C2 &= ~UARTLP_C2_SBK_MASK;
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_RTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_RTS;
}

189
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c Normal file
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@@ -0,0 +1,189 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "spi_api.h"
#include <math.h>
#include "cmsis.h"
#include "pinmap.h"
#include "clk_freqs.h"
#include "PeripheralPins.h"
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
// enable power and clocking
switch ((int)obj->spi) {
case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
}
// enable SPI
obj->spi->C1 |= SPI_C1_SPE_MASK;
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {
// [TODO]
}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
MBED_ASSERT(bits == 8);
MBED_ASSERT((mode >= 0) && (mode <= 3));
uint8_t polarity = (mode & 0x2) ? 1 : 0;
uint8_t phase = (mode & 0x1) ? 1 : 0;
uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
// clear MSTR, CPOL and CPHA bits
obj->spi->C1 &= ~(0x7 << 2);
// write new value
obj->spi->C1 |= c1_data;
}
void spi_frequency(spi_t *obj, int hz) {
uint32_t error = 0;
uint32_t p_error = 0xffffffff;
uint32_t ref = 0;
uint8_t spr = 0;
uint8_t ref_spr = 0;
uint8_t ref_prescaler = 0;
// bus clk
uint32_t PCLK = bus_frequency();
uint8_t prescaler = 1;
uint8_t divisor = 2;
for (prescaler = 1; prescaler <= 8; prescaler++) {
divisor = 2;
for (spr = 0; spr <= 8; spr++, divisor *= 2) {
ref = PCLK / (prescaler*divisor);
if (ref > (uint32_t)hz)
continue;
error = hz - ref;
if (error < p_error) {
ref_spr = spr;
ref_prescaler = prescaler - 1;
p_error = error;
}
}
}
// set SPPR and SPR
obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
}
static inline int spi_writeable(spi_t * obj) {
return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
}
static inline int spi_readable(spi_t * obj) {
return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
obj->spi->D = (value & 0xff);
// wait rx buffer full
while (!spi_readable(obj));
return obj->spi->D & 0xff;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) {
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj) {
return spi_readable(obj);
}
int spi_slave_read(spi_t *obj) {
return obj->spi->D;
}
void spi_slave_write(spi_t *obj, int value) {
while (!spi_writeable(obj));
obj->spi->D = value;
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SSEL;
}