Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
4155
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/MKL25Z4.h
Normal file
4155
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/MKL25Z4.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,46 @@
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#! armcc -E
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x00000000
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x20000
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#endif
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 1FFFF000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x4000
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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#define VECTOR_SIZE 0xC0
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#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
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}
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}
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@@ -0,0 +1,328 @@
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;/*****************************************************************************
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; * @file: startup_MKL25Z4.s
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; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
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; * MKL25Z4
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; * @version: 1.1
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; * @date: 2012-6-21
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; *
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; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
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; *****************************************************************************/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
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DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
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DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
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DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
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DCD Reserved20_IRQHandler ; Reserved interrupt 20
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DCD FTFA_IRQHandler ; FTFA interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD I2C1_IRQHandler ; I2C0 interrupt 25
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD SPI1_IRQHandler ; SPI1 interrupt
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DCD UART0_IRQHandler ; UART0 status/error interrupt
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DCD UART1_IRQHandler ; UART1 status/error interrupt
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DCD UART2_IRQHandler ; UART2 status/error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
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DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
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DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT_IRQHandler ; PIT timer interrupt
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DCD Reserved39_IRQHandler ; Reserved interrupt 39
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DCD USB0_IRQHandler ; USB0 interrupt
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DCD DAC0_IRQHandler ; DAC interrupt
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DCD TSI0_IRQHandler ; TSI0 interrupt
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DCD MCG_IRQHandler ; MCG interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD Reserved45_IRQHandler ; Reserved interrupt 45
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTD_IRQHandler ; Port D interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT0
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
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; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
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; <o.4> LPBOOT1
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
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; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI pin/interrupts reset default to enabled
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; <o.3> RESET_PIN_CFG
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; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
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; <1=> RESET pin is dedicated
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; <o.3> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <i> This bits define the security state of the MCU.
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <i> This bits define the security state of the MCU.
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <i> Mass Erase Enable Bits
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; <i> Enables and disables mass erase capability of the FTFL module
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor key Security Enable
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; <i> These bits enable and disable backdoor key access to the FTFL module.
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FSEC EQU 0xFE
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, 0xFF, 0xFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DMA0_IRQHandler [WEAK]
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EXPORT DMA1_IRQHandler [WEAK]
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EXPORT DMA2_IRQHandler [WEAK]
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EXPORT DMA3_IRQHandler [WEAK]
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EXPORT Reserved20_IRQHandler [WEAK]
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EXPORT FTFA_IRQHandler [WEAK]
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EXPORT LVD_LVW_IRQHandler [WEAK]
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EXPORT LLW_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT CMP0_IRQHandler [WEAK]
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EXPORT TPM0_IRQHandler [WEAK]
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EXPORT TPM1_IRQHandler [WEAK]
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EXPORT TPM2_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT RTC_Seconds_IRQHandler [WEAK]
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EXPORT PIT_IRQHandler [WEAK]
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EXPORT Reserved39_IRQHandler [WEAK]
|
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EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT TSI0_IRQHandler [WEAK]
|
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EXPORT MCG_IRQHandler [WEAK]
|
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EXPORT LPTimer_IRQHandler [WEAK]
|
||||
EXPORT Reserved45_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
|
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DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
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DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
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Reserved20_IRQHandler
|
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FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
Reserved39_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
Reserved45_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
DefaultISR
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
@@ -0,0 +1,28 @@
|
||||
#! armcc -E
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#define Stack_Size MBED_BOOT_STACK_SIZE
|
||||
|
||||
LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
|
||||
ER_IROM1 0x00000000 0x20000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||
; 0x4000 - 0xC0 = 0x3F40
|
||||
RW_IRAM1 0x1FFFF0C0 0x3F40 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFFF000+0x4000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
|
||||
}
|
||||
|
||||
ARM_LIB_STACK 0x1FFFF000+0x4000 EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,331 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_MKL25Z4.s
|
||||
; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
|
||||
; * MKL25Z4
|
||||
; * @version: 1.1
|
||||
; * @date: 2012-6-21
|
||||
; *
|
||||
; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
;*
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
||||
|
||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
|
||||
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
|
||||
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
|
||||
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
|
||||
DCD Reserved20_IRQHandler ; Reserved interrupt 20
|
||||
DCD FTFA_IRQHandler ; FTFA interrupt
|
||||
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
|
||||
DCD LLW_IRQHandler ; Low Leakage Wakeup
|
||||
DCD I2C0_IRQHandler ; I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; I2C0 interrupt 25
|
||||
DCD SPI0_IRQHandler ; SPI0 interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 interrupt
|
||||
DCD UART0_IRQHandler ; UART0 status/error interrupt
|
||||
DCD UART1_IRQHandler ; UART1 status/error interrupt
|
||||
DCD UART2_IRQHandler ; UART2 status/error interrupt
|
||||
DCD ADC0_IRQHandler ; ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ; CMP0 interrupt
|
||||
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
|
||||
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
|
||||
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
|
||||
DCD RTC_IRQHandler ; RTC interrupt
|
||||
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
|
||||
DCD PIT_IRQHandler ; PIT timer interrupt
|
||||
DCD Reserved39_IRQHandler ; Reserved interrupt 39
|
||||
DCD USB0_IRQHandler ; USB0 interrupt
|
||||
DCD DAC0_IRQHandler ; DAC interrupt
|
||||
DCD TSI0_IRQHandler ; TSI0 interrupt
|
||||
DCD MCG_IRQHandler ; MCG interrupt
|
||||
DCD LPTimer_IRQHandler ; LPTimer interrupt
|
||||
DCD Reserved45_IRQHandler ; Reserved interrupt 45
|
||||
DCD PORTA_IRQHandler ; Port A interrupt
|
||||
DCD PORTD_IRQHandler ; Port D interrupt
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Key 0 <0x0-0xFF:2>
|
||||
; <o1> Backdoor Key 1 <0x0-0xFF:2>
|
||||
; <o2> Backdoor Key 2 <0x0-0xFF:2>
|
||||
; <o3> Backdoor Key 3 <0x0-0xFF:2>
|
||||
; <o4> Backdoor Key 4 <0x0-0xFF:2>
|
||||
; <o5> Backdoor Key 5 <0x0-0xFF:2>
|
||||
; <o6> Backdoor Key 6 <0x0-0xFF:2>
|
||||
; <o7> Backdoor Key 7 <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program flash protection bytes
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT0
|
||||
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
|
||||
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
|
||||
; <o.4> LPBOOT1
|
||||
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
|
||||
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
|
||||
; <o.2> NMI_DIS
|
||||
; <0=> NMI interrupts are always blocked
|
||||
; <1=> NMI pin/interrupts reset default to enabled
|
||||
; <o.3> RESET_PIN_CFG
|
||||
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
|
||||
; <1=> RESET pin is dedicated
|
||||
; <o.3> FAST_INIT
|
||||
; <0=> Slower initialization
|
||||
; <1=> Fast Initialization
|
||||
FOPT EQU 0xFF
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <i> Mass Erase Enable Bits
|
||||
; <i> Enables and disables mass erase capability of the FTFL module
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor key Security Enable
|
||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, 0xFF, 0xFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DMA0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_IRQHandler [WEAK]
|
||||
EXPORT DMA3_IRQHandler [WEAK]
|
||||
EXPORT Reserved20_IRQHandler [WEAK]
|
||||
EXPORT FTFA_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT LLW_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT TPM0_IRQHandler [WEAK]
|
||||
EXPORT TPM1_IRQHandler [WEAK]
|
||||
EXPORT TPM2_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||
EXPORT PIT_IRQHandler [WEAK]
|
||||
EXPORT Reserved39_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT TSI0_IRQHandler [WEAK]
|
||||
EXPORT MCG_IRQHandler [WEAK]
|
||||
EXPORT LPTimer_IRQHandler [WEAK]
|
||||
EXPORT Reserved45_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
Reserved20_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
Reserved39_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
Reserved45_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
DefaultISR
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
END
|
||||
@@ -0,0 +1,170 @@
|
||||
/*
|
||||
* KL25Z ARM GCC linker script file
|
||||
*/
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
STACK_SIZE = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
||||
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
|
||||
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
|
||||
RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* _reset_init : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.isr_vector :
|
||||
{
|
||||
__vector_table = .;
|
||||
KEEP(*(.vector_table))
|
||||
*(.text.Reset_Handler)
|
||||
*(.text.System_Init)
|
||||
. = ALIGN(8);
|
||||
} > VECTORS
|
||||
|
||||
.flash_protect :
|
||||
{
|
||||
KEEP(*(.kinetis_flash_config_field))
|
||||
. = ALIGN(8);
|
||||
} > FLASH_PROTECTION
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
@@ -0,0 +1,239 @@
|
||||
/* KL25Z startup ARM GCC
|
||||
* Purpose: startup file for Cortex-M0 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V1.2
|
||||
* Date: 15 Nov 2011
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the ARM Limited nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
/* Memory Model
|
||||
The HEAP starts at the end of the DATA section and grows upward.
|
||||
|
||||
The STACK starts at the end of the RAM and grows downward.
|
||||
|
||||
The HEAP and stack STACK are only checked at compile time:
|
||||
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
|
||||
|
||||
This is just a check for the bare minimum for the Heap+Stack area before
|
||||
aborting compilation, it is not the run time limit:
|
||||
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
|
||||
*/
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x80
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x80
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.space Heap_Size
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vector_table,"a",%progbits
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
|
||||
.long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
|
||||
.long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
|
||||
.long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
|
||||
.long Default_Handler /* Reserved interrupt 20 */
|
||||
.long FTFA_IRQHandler /* FTFA interrupt */
|
||||
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
|
||||
.long LLW_IRQHandler /* Low Leakage Wakeup */
|
||||
.long I2C0_IRQHandler /* I2C0 interrupt */
|
||||
.long I2C1_IRQHandler /* I2C0 interrupt 25 */
|
||||
.long SPI0_IRQHandler /* SPI0 interrupt */
|
||||
.long SPI1_IRQHandler /* SPI1 interrupt */
|
||||
.long UART0_IRQHandler /* UART0 status/error interrupt */
|
||||
.long UART1_IRQHandler /* UART1 status/error interrupt */
|
||||
.long UART2_IRQHandler /* UART2 status/error interrupt */
|
||||
.long ADC0_IRQHandler /* ADC0 interrupt */
|
||||
.long CMP0_IRQHandler /* CMP0 interrupt */
|
||||
.long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
|
||||
.long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
|
||||
.long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
|
||||
.long RTC_IRQHandler /* RTC interrupt */
|
||||
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
|
||||
.long PIT_IRQHandler /* PIT timer interrupt */
|
||||
.long Default_Handler /* Reserved interrupt 39 */
|
||||
.long USB0_IRQHandler /* USB0 interrupt */
|
||||
.long DAC0_IRQHandler /* DAC interrupt */
|
||||
.long TSI0_IRQHandler /* TSI0 interrupt */
|
||||
.long MCG_IRQHandler /* MCG interrupt */
|
||||
.long LPTimer_IRQHandler /* LPTimer interrupt */
|
||||
.long Default_Handler /* Reserved interrupt 45 */
|
||||
.long PORTA_IRQHandler /* Port A interrupt */
|
||||
.long PORTD_IRQHandler /* Port D interrupt */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .Lflash_to_ram_loop_end
|
||||
|
||||
movs r4, 0
|
||||
.Lflash_to_ram_loop:
|
||||
ldr r0, [r1,r4]
|
||||
str r0, [r2,r4]
|
||||
adds r4, 4
|
||||
cmp r4, r3
|
||||
blt .Lflash_to_ram_loop
|
||||
.Lflash_to_ram_loop_end:
|
||||
|
||||
ldr r0, =SystemInit
|
||||
blx r0
|
||||
ldr r0, =_start
|
||||
bx r0
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.text
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_default_handler handler_name
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak \handler_name
|
||||
.type \handler_name, %function
|
||||
\handler_name :
|
||||
b .
|
||||
.size \handler_name, . - \handler_name
|
||||
.endm
|
||||
|
||||
def_default_handler NMI_Handler
|
||||
def_default_handler HardFault_Handler
|
||||
def_default_handler SVC_Handler
|
||||
def_default_handler PendSV_Handler
|
||||
def_default_handler SysTick_Handler
|
||||
def_default_handler Default_Handler
|
||||
|
||||
.macro def_irq_default_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_default_handler DMA0_IRQHandler
|
||||
def_irq_default_handler DMA1_IRQHandler
|
||||
def_irq_default_handler DMA2_IRQHandler
|
||||
def_irq_default_handler DMA3_IRQHandler
|
||||
def_irq_default_handler FTFA_IRQHandler
|
||||
def_irq_default_handler LVD_LVW_IRQHandler
|
||||
def_irq_default_handler LLW_IRQHandler
|
||||
def_irq_default_handler I2C0_IRQHandler
|
||||
def_irq_default_handler I2C1_IRQHandler
|
||||
def_irq_default_handler SPI0_IRQHandler
|
||||
def_irq_default_handler SPI1_IRQHandler
|
||||
def_irq_default_handler UART0_IRQHandler
|
||||
def_irq_default_handler UART1_IRQHandler
|
||||
def_irq_default_handler UART2_IRQHandler
|
||||
def_irq_default_handler ADC0_IRQHandler
|
||||
def_irq_default_handler CMP0_IRQHandler
|
||||
def_irq_default_handler TPM0_IRQHandler
|
||||
def_irq_default_handler TPM1_IRQHandler
|
||||
def_irq_default_handler TPM2_IRQHandler
|
||||
def_irq_default_handler RTC_IRQHandler
|
||||
def_irq_default_handler RTC_Seconds_IRQHandler
|
||||
def_irq_default_handler PIT_IRQHandler
|
||||
def_irq_default_handler USB0_IRQHandler
|
||||
def_irq_default_handler DAC0_IRQHandler
|
||||
def_irq_default_handler TSI0_IRQHandler
|
||||
def_irq_default_handler MCG_IRQHandler
|
||||
def_irq_default_handler LPTimer_IRQHandler
|
||||
def_irq_default_handler PORTA_IRQHandler
|
||||
def_irq_default_handler PORTD_IRQHandler
|
||||
def_irq_default_handler DEF_IRQHandler
|
||||
|
||||
/* Flash protection region, placed at 0x400 */
|
||||
.text
|
||||
.thumb
|
||||
.align 2
|
||||
.section .kinetis_flash_config_field,"a",%progbits
|
||||
kinetis_flash_config:
|
||||
.long 0xffffffff
|
||||
.long 0xffffffff
|
||||
.long 0xffffffff
|
||||
.long 0xfffffffe
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,45 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
|
||||
define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffff000;
|
||||
define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffff0bf;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __ICFEDIT_size_heap__ = 0xC00;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM2_start__ = 0x20000000;
|
||||
define symbol __region_RAM2_end__ = 0x20002fff;
|
||||
|
||||
define symbol __FlashConfig_start__ = 0x00000400;
|
||||
define symbol __FlashConfig_end__ = 0x0000040f;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in FlashConfig_region {section FlashConfig};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
|
||||
place in RAM_region { readwrite, block HEAP, block CSTACK };
|
||||
@@ -0,0 +1,213 @@
|
||||
/**************************************************
|
||||
*
|
||||
* Copyright 2012 IAR Systems. All rights reserved.
|
||||
*
|
||||
* $Revision: 16 $
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:ROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
|
||||
DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
|
||||
DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
|
||||
DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
|
||||
DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
|
||||
DCD FTFA_IRQHandler ; 5: FTFA
|
||||
DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
|
||||
DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
|
||||
DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
|
||||
DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
|
||||
DCD SPI0_IRQHandler ;10: SPI0 intertrupt
|
||||
DCD SPI1_IRQHandler ;11: SPI1 intertrupt
|
||||
DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
|
||||
DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
|
||||
DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
|
||||
DCD ADC0_IRQHandler ;15: ADC 0 interrupt
|
||||
DCD CMP0_IRQHandler ;16: CMP 0 interrupt
|
||||
DCD TPM0_IRQHandler ;17: TPM 0 interrupt
|
||||
DCD TPM1_IRQHandler ;18: TPM 1 interrupt
|
||||
DCD TPM2_IRQHandler ;19: TPM 2 interrupt
|
||||
DCD RTC_IRQHandler ;20: RTC Alarm interrupt
|
||||
DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
|
||||
DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
|
||||
DCD 0 ;23: Reserved
|
||||
DCD USB0_IRQHandler ;24: USB OTG intertrupt
|
||||
DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
|
||||
DCD TSI0_IRQHandler ;26: TSI 0 interrupt
|
||||
DCD MCG_IRQHandler ;27: MCG intertrupt
|
||||
DCD LPTimer_IRQHandler ;28: LPTMR0 intertrupt
|
||||
DCD 0 ;29: Reserved
|
||||
DCD PORTA_IRQHandler ;30: PORT A interrupt
|
||||
DCD PORTD_IRQHandler ;31: PORT D interrupt
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;Flash Configuration
|
||||
;;16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
;;and security information that allows the MCU to restrict acces to the FTFL module.
|
||||
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0^0xFF
|
||||
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1^0xFF
|
||||
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2^0xFF
|
||||
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3^0xFF
|
||||
|
||||
FOPT EQU 0xFF
|
||||
|
||||
FSEC EQU 0xFE
|
||||
SECTION FlashConfig:CONST:REORDER:ROOT(2)
|
||||
Config:
|
||||
DATA
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0, FPROT1, FPROT2, FPROT3
|
||||
DCB FSEC, FOPT, 0xFF, 0xFF
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK DMA0_IRQHandler
|
||||
PUBWEAK DMA1_IRQHandler
|
||||
PUBWEAK DMA2_IRQHandler
|
||||
PUBWEAK DMA3_IRQHandler
|
||||
PUBWEAK FTFA_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLW_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK UART0_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK TPM0_IRQHandler
|
||||
PUBWEAK TPM1_IRQHandler
|
||||
PUBWEAK TPM2_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK TSI0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTimer_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
THUMB
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLW_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTimer_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
END
|
||||
@@ -0,0 +1,13 @@
|
||||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC11U24 specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "MKL25Z4.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,37 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFFF000 // Vectors positioned at start of RAM
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,300 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processor: MKL25Z128VLK4
|
||||
** Compilers: ARM Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL25RM, Rev.1, Jun 2012
|
||||
** Version: rev. 1.1, 2012-06-21
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2012-06-13)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2012-06-21)
|
||||
** Update according to reference manual rev. 1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file MKL25Z4
|
||||
* @version 1.1
|
||||
* @date 2012-06-21
|
||||
* @brief Device specific configuration file for MKL25Z4 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "MKL25Z4.h"
|
||||
|
||||
#define DISABLE_WDOG 1
|
||||
|
||||
#define CLOCK_SETUP 1
|
||||
/* Predefined clock setups
|
||||
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
||||
Reference clock source for MCG module is the slow internal clock source 32.768kHz
|
||||
Core clock = 41.94MHz, BusClock = 13.98MHz
|
||||
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
|
||||
Reference clock source for MCG module is an external crystal 8MHz
|
||||
Core clock = 48MHz, BusClock = 24MHz
|
||||
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
|
||||
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
|
||||
Core clock = 8MHz, BusClock = 8MHz
|
||||
3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
|
||||
Reference clock source for MCG module is an external crystal 32.768kHz
|
||||
Core clock = 47.97MHz, BusClock = 23.98MHz
|
||||
This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
|
||||
RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
|
||||
accuracy durring the reset period. RTC will reset on power down.
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clock source values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
|
||||
#elif (CLOCK_SETUP == 3)
|
||||
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
|
||||
#endif /* (CLOCK_SETUP == 3) */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if (DISABLE_WDOG)
|
||||
/* Disable the WDOG module */
|
||||
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
|
||||
SIM->COPC = (uint32_t)0x00u;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
#if (CLOCK_SETUP == 0)
|
||||
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
|
||||
/* Switch to FEI Mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x06U;
|
||||
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x00U;
|
||||
/* MCG->C4: DMX32=0,DRST_DRS=1 */
|
||||
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
|
||||
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0->CR = (uint8_t)0x80U;
|
||||
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
MCG->C5 = (uint8_t)0x00U;
|
||||
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
|
||||
}
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
/* SIM->SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
|
||||
/* PORTA->PCR18: ISF=0,MUX=0 */
|
||||
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
|
||||
/* PORTA->PCR19: ISF=0,MUX=0 */
|
||||
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
|
||||
OSC0->CR = (uint8_t)0x89U;
|
||||
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24U;
|
||||
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x9AU;
|
||||
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
|
||||
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
|
||||
MCG->C5 = (uint8_t)0x01U;
|
||||
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to PBE Mode */
|
||||
/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x40U;
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
|
||||
}
|
||||
/* Switch to PEE Mode */
|
||||
/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x1AU;
|
||||
while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
|
||||
}
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
/* SIM->SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
|
||||
/* PORTA->PCR18: ISF=0,MUX=0 */
|
||||
PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
|
||||
/* PORTA->PCR19: ISF=0,MUX=0 */
|
||||
PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
|
||||
/* Switch to FBE Mode */
|
||||
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
|
||||
OSC0->CR = (uint8_t)0x89U;
|
||||
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x24U;
|
||||
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (uint8_t)0x9AU;
|
||||
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||||
MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
|
||||
/* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||||
MCG->C5 = (uint8_t)0x00U;
|
||||
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||||
MCG->C6 = (uint8_t)0x00U;
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
/* Switch to BLPE Mode */
|
||||
/* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
|
||||
MCG->C2 = (uint8_t)0x26U;
|
||||
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||||
}
|
||||
#elif (CLOCK_SETUP == 3)
|
||||
/* SIM->SCGC5: PORTA=1 */
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
|
||||
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
||||
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
|
||||
/* PORTA->PCR[3]: ISF=0,MUX=0 */
|
||||
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
/* PORTA->PCR[4]: ISF=0,MUX=0 */
|
||||
PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
/* Switch to FEE Mode */
|
||||
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
||||
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
|
||||
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
|
||||
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
|
||||
/* MCG->C4: DMX32=1,DRST_DRS=1 */
|
||||
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
|
||||
MCG_C4_DRST_DRS(0x02)
|
||||
)) | (uint8_t)(
|
||||
MCG_C4_DMX32_MASK |
|
||||
MCG_C4_DRST_DRS(0x01)
|
||||
));
|
||||
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||||
}
|
||||
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
|
||||
}
|
||||
#endif /* (CLOCK_SETUP == 3) */
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
||||
uint8_t Divider;
|
||||
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
|
||||
/* Output of FLL or PLL is selected */
|
||||
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
|
||||
/* FLL is selected */
|
||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
|
||||
/* External reference clock is selected */
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
||||
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
|
||||
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
|
||||
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
||||
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||||
/* Select correct multiplier to calculate the MCG output clock */
|
||||
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||||
case 0x0u:
|
||||
MCGOUTClock *= 640u;
|
||||
break;
|
||||
case 0x20u:
|
||||
MCGOUTClock *= 1280u;
|
||||
break;
|
||||
case 0x40u:
|
||||
MCGOUTClock *= 1920u;
|
||||
break;
|
||||
case 0x60u:
|
||||
MCGOUTClock *= 2560u;
|
||||
break;
|
||||
case 0x80u:
|
||||
MCGOUTClock *= 732u;
|
||||
break;
|
||||
case 0xA0u:
|
||||
MCGOUTClock *= 1464u;
|
||||
break;
|
||||
case 0xC0u:
|
||||
MCGOUTClock *= 2197u;
|
||||
break;
|
||||
case 0xE0u:
|
||||
MCGOUTClock *= 2929u;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||||
/* PLL is selected */
|
||||
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
|
||||
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
||||
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
|
||||
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
||||
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
|
||||
/* Internal reference clock is selected */
|
||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
||||
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||||
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
|
||||
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
|
||||
/* External reference clock is selected */
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||||
/* Reserved value */
|
||||
return;
|
||||
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||||
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processor: MKL25Z128VLK4
|
||||
** Compilers: ARM Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL25RM, Rev.1, Jun 2012
|
||||
** Version: rev. 1.1, 2012-06-21
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2012-06-13)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2012-06-21)
|
||||
** Update according to reference manual rev. 1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file MKL25Z4
|
||||
* @version 1.1
|
||||
* @date 2012-06-21
|
||||
* @brief Device specific configuration file for MKL25Z4 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_MKL25Z4_H_
|
||||
#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
|
||||
Reference in New Issue
Block a user