beslan/mbed-os-hardfp
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Import Mbed OS hard-float snapshot

Browse Source
This commit is contained in:
Beslan
2026-06-01 20:15:04 +03:00
commit d3738e2f89
16278 changed files with 10628036 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17566
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h Normal file
View File

File diff suppressed because it is too large Load Diff

1978
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h Normal file
View File

File diff suppressed because it is too large Load Diff

128
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct Normal file
View File

@@ -0,0 +1,128 @@
#! armcc -E
/*
** ###################################################################
** Processors: MK66FN2M0VLQ18
** MK66FN2M0VMD18
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b170214
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define __ram_vector_table__ 1
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x00000400
#else
#define __ram_vector_table_size__ 0x00000000
#endif
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x200000
#endif
#define m_interrupts_start MBED_APP_START
#define m_interrupts_size 0x00000400
#define m_flash_config_start MBED_APP_START + 0x400
#define m_flash_config_size 0x00000010
#define m_text_start MBED_APP_START + 0x410
#define m_text_size MBED_APP_SIZE - 0x410
#define m_interrupts_ram_start 0x1FFF0000
#define m_interrupts_ram_size __ram_vector_table_size__
#define m_crash_report_ram_start (m_interrupts_ram_start + m_interrupts_ram_size)
#define m_crash_report_ram_size (0x100)
#define m_data_start (m_crash_report_ram_start + m_crash_report_ram_size)
#define m_data_size (0x00010000 - (m_interrupts_ram_size+m_crash_report_ram_size))
#define m_data_2_start 0x20000000
#define m_data_2_size 0x00030000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size MBED_BOOT_STACK_SIZE
#endif
LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (FlashConfig)
}
ER_IROM1 m_text_start m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__ram_vector_table__))
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
#else
VECTOR_RAM m_interrupts_start EMPTY 0 {
}
#endif
RW_m_crash_data m_crash_report_ram_start EMPTY m_crash_report_ram_size { ; RW data
}
RW_m_data m_data_start m_data_size { ; RW data
.ANY2 (+RW +ZI)
}
RW_m_data_2 m_data_2_start m_data_2_size { ; RW data
.ANY1 (+RW +ZI)
}
RW_IRAM1 ImageLimit(RW_m_data_2) EMPTY 0 {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_2_start + m_data_2_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
}
ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down
}
}

1104
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S Normal file
View File

File diff suppressed because it is too large Load Diff

283
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld Normal file
View File

@@ -0,0 +1,283 @@
/*
** ###################################################################
** Processors: MK66FN2M0VLQ18
** MK66FN2M0VMD18
**
** Compiler: GNU C Compiler
** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b170214
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Entry Point */
ENTRY(Reset_Handler)
__ram_vector_table__ = 1;
/* With the RTOS in use, this does not affect the main stack size. The size of
* the stack where main runs is determined via the RTOS. */
__stack_size__ = MBED_BOOT_STACK_SIZE;
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x200000
#endif
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
M_CRASH_DATA_RAM_SIZE = 0x100;
/* Specify the memory areas */
MEMORY
{
m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x400
m_flash_config (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10
m_text (RX) : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410
m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
. = ALIGN(8);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(8);
} > m_interrupts
.flash_config :
{
. = ALIGN(8);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(8);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(8);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.interrupts_ram :
{
. = ALIGN(8);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(8);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
.crash_data_ram :
{
. = ALIGN(8);
__CRASH_DATA_RAM__ = .;
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
KEEP(*(.keep.crash_data_ram))
*(.m_crash_data_ram) /* This is a user defined section */
. += M_CRASH_DATA_RAM_SIZE;
. = ALIGN(8);
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
} > m_data
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
.data : AT(__DATA_ROM)
{
. = ALIGN(8);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(8);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
.heap_0 :
{
. = ALIGN(8);
__mbed_sbrk_start_0 = .;
. += (ORIGIN(m_data) + LENGTH(m_data) - .);
__mbed_krbs_start_0 = .;
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(8);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(8);
__bss_end__ = .;
__END_BSS = .;
} > m_data_2
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__mbed_sbrk_start = .;
__HeapBase = .;
. = ORIGIN(m_data_2) + LENGTH(m_data_2) - STACK_SIZE;
__mbed_krbs_start = .;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data_2
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data_2
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

1048
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S Normal file
View File

File diff suppressed because it is too large Load Diff

129
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf Normal file
View File

@@ -0,0 +1,129 @@
/*
** ###################################################################
** Processors: MK66FN2M0VLQ18
** MK66FN2M0VMD18
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b170214
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol __ram_vector_table__ = 1;
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __stack_size__=MBED_BOOT_STACK_SIZE;
define symbol __heap_size__=0x10000;
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = 0;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = 0x200000;
}
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
define symbol m_interrupts_start = MBED_APP_START;
define symbol m_interrupts_end = MBED_APP_START + 0x3FF;
define symbol m_flash_config_start = MBED_APP_START + 0x400;
define symbol m_flash_config_end = MBED_APP_START + 0x40F;
define symbol m_text_start = MBED_APP_START + 0x410;
define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol m_interrupts_ram_start = 0x1FFF0000;
define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__;
define symbol m_crash_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_crash_data_size = 0x100;
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__ + m_crash_data_size;
define symbol m_data_end = 0x1FFFFFFF;
define symbol m_data_2_start = 0x20000000;
define symbol m_data_2_end = 0x2002FFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define exported symbol __CRASH_DATA_RAM_START__ = m_crash_data_start;
define exported symbol __CRASH_DATA_RAM_END__ = m_crash_data_start + m_crash_data_size;
define memory mem with size = 4G;
define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end]
| mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in m_flash_config_region { section FlashConfig };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in m_interrupts_ram_region { section m_interrupts_ram };

919
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S Normal file
View File

@@ -0,0 +1,919 @@
; ---------------------------------------------------------------------------------------
; @file: startup_MK66F18.s
; @purpose: CMSIS Cortex-M4 Core Device Startup File
; MK66F18
; @version: 3.0
; @date: 2015-3-25
; @build: b170112
; ---------------------------------------------------------------------------------------
;
; Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
; Copyright 2016 - 2017 NXP
; Redistribution and use in source and binary forms, with or without modification,
; are permitted provided that the following conditions are met:
;
; o Redistributions of source code must retain the above copyright notice, this list
; of conditions and the following disclaimer.
;
; o Redistributions in binary form must reproduce the above copyright notice, this
; list of conditions and the following disclaimer in the documentation and/or
; other materials provided with the distribution.
;
; o Neither the name of the copyright holder nor the names of its
; contributors may be used to endorse or promote products derived from this
; software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
__vector_table_0x1c
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA Channel 0, 16 Transfer Complete
DCD DMA1_DMA17_IRQHandler ;DMA Channel 1, 17 Transfer Complete
DCD DMA2_DMA18_IRQHandler ;DMA Channel 2, 18 Transfer Complete
DCD DMA3_DMA19_IRQHandler ;DMA Channel 3, 19 Transfer Complete
DCD DMA4_DMA20_IRQHandler ;DMA Channel 4, 20 Transfer Complete
DCD DMA5_DMA21_IRQHandler ;DMA Channel 5, 21 Transfer Complete
DCD DMA6_DMA22_IRQHandler ;DMA Channel 6, 22 Transfer Complete
DCD DMA7_DMA23_IRQHandler ;DMA Channel 7, 23 Transfer Complete
DCD DMA8_DMA24_IRQHandler ;DMA Channel 8, 24 Transfer Complete
DCD DMA9_DMA25_IRQHandler ;DMA Channel 9, 25 Transfer Complete
DCD DMA10_DMA26_IRQHandler ;DMA Channel 10, 26 Transfer Complete
DCD DMA11_DMA27_IRQHandler ;DMA Channel 11, 27 Transfer Complete
DCD DMA12_DMA28_IRQHandler ;DMA Channel 12, 28 Transfer Complete
DCD DMA13_DMA29_IRQHandler ;DMA Channel 13, 29 Transfer Complete
DCD DMA14_DMA30_IRQHandler ;DMA Channel 14, 30 Transfer Complete
DCD DMA15_DMA31_IRQHandler ;DMA Channel 15, 31 Transfer Complete
DCD DMA_Error_IRQHandler ;DMA Error Interrupt
DCD MCM_IRQHandler ;Normal Interrupt
DCD FTFE_IRQHandler ;FTFE Command complete interrupt
DCD Read_Collision_IRQHandler ;Read Collision Interrupt
DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning
DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit
DCD WDOG_EWM_IRQHandler ;WDOG Interrupt
DCD RNG_IRQHandler ;RNG Interrupt
DCD I2C0_IRQHandler ;I2C0 interrupt
DCD I2C1_IRQHandler ;I2C1 interrupt
DCD SPI0_IRQHandler ;SPI0 Interrupt
DCD SPI1_IRQHandler ;SPI1 Interrupt
DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt
DCD Reserved46_IRQHandler ;Reserved interrupt 46
DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt
DCD UART0_ERR_IRQHandler ;UART0 Error interrupt
DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt
DCD UART1_ERR_IRQHandler ;UART1 Error interrupt
DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt
DCD UART2_ERR_IRQHandler ;UART2 Error interrupt
DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt
DCD UART3_ERR_IRQHandler ;UART3 Error interrupt
DCD ADC0_IRQHandler ;ADC0 interrupt
DCD CMP0_IRQHandler ;CMP0 interrupt
DCD CMP1_IRQHandler ;CMP1 interrupt
DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ;CMT interrupt
DCD RTC_IRQHandler ;RTC interrupt
DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ;PDB0 Interrupt
DCD USB0_IRQHandler ;USB0 interrupt
DCD USBDCD_IRQHandler ;USBDCD Interrupt
DCD Reserved71_IRQHandler ;Reserved interrupt 71
DCD DAC0_IRQHandler ;DAC0 interrupt
DCD MCG_IRQHandler ;MCG Interrupt
DCD LPTMR0_IRQHandler ;LPTimer interrupt
DCD PORTA_IRQHandler ;Port A interrupt
DCD PORTB_IRQHandler ;Port B interrupt
DCD PORTC_IRQHandler ;Port C interrupt
DCD PORTD_IRQHandler ;Port D interrupt
DCD PORTE_IRQHandler ;Port E interrupt
DCD SWI_IRQHandler ;Software interrupt
DCD SPI2_IRQHandler ;SPI2 Interrupt
DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt
DCD UART4_ERR_IRQHandler ;UART4 Error interrupt
DCD Reserved84_IRQHandler ;Reserved interrupt 84
DCD Reserved85_IRQHandler ;Reserved interrupt 85
DCD CMP2_IRQHandler ;CMP2 interrupt
DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt
DCD DAC1_IRQHandler ;DAC1 interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
DCD I2C2_IRQHandler ;I2C2 interrupt
DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt
DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt
DCD CAN0_Error_IRQHandler ;CAN0 error interrupt
DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt
DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt
DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt
DCD SDHC_IRQHandler ;SDHC interrupt
DCD ENET_1588_Timer_IRQHandler ;Ethernet MAC IEEE 1588 Timer Interrupt
DCD ENET_Transmit_IRQHandler ;Ethernet MAC Transmit Interrupt
DCD ENET_Receive_IRQHandler ;Ethernet MAC Receive Interrupt
DCD ENET_Error_IRQHandler ;Ethernet MAC Error and miscelaneous Interrupt
DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt
DCD TSI0_IRQHandler ;TSI0 interrupt
DCD TPM1_IRQHandler ;TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ;TPM2 fault, overflow and channels interrupt
DCD USBHSDCD_IRQHandler ;USBHSDCD, USBHS Phy Interrupt
DCD I2C3_IRQHandler ;I2C3 interrupt
DCD CMP3_IRQHandler ;CMP3 interrupt
DCD USBHS_IRQHandler ;USB high speed OTG interrupt
DCD CAN1_ORed_Message_buffer_IRQHandler ;CAN1 OR'd message buffers interrupt
DCD CAN1_Bus_Off_IRQHandler ;CAN1 bus off interrupt
DCD CAN1_Error_IRQHandler ;CAN1 error interrupt
DCD CAN1_Tx_Warning_IRQHandler ;CAN1 Tx warning interrupt
DCD CAN1_Rx_Warning_IRQHandler ;CAN1 Rx warning interrupt
DCD CAN1_Wake_Up_IRQHandler ;CAN1 wake up interrupt
DCD DefaultISR ;116
DCD DefaultISR ;117
DCD DefaultISR ;118
DCD DefaultISR ;119
DCD DefaultISR ;120
DCD DefaultISR ;121
DCD DefaultISR ;122
DCD DefaultISR ;123
DCD DefaultISR ;124
DCD DefaultISR ;125
DCD DefaultISR ;126
DCD DefaultISR ;127
DCD DefaultISR ;128
DCD DefaultISR ;129
DCD DefaultISR ;130
DCD DefaultISR ;131
DCD DefaultISR ;132
DCD DefaultISR ;133
DCD DefaultISR ;134
DCD DefaultISR ;135
DCD DefaultISR ;136
DCD DefaultISR ;137
DCD DefaultISR ;138
DCD DefaultISR ;139
DCD DefaultISR ;140
DCD DefaultISR ;141
DCD DefaultISR ;142
DCD DefaultISR ;143
DCD DefaultISR ;144
DCD DefaultISR ;145
DCD DefaultISR ;146
DCD DefaultISR ;147
DCD DefaultISR ;148
DCD DefaultISR ;149
DCD DefaultISR ;150
DCD DefaultISR ;151
DCD DefaultISR ;152
DCD DefaultISR ;153
DCD DefaultISR ;154
DCD DefaultISR ;155
DCD DefaultISR ;156
DCD DefaultISR ;157
DCD DefaultISR ;158
DCD DefaultISR ;159
DCD DefaultISR ;160
DCD DefaultISR ;161
DCD DefaultISR ;162
DCD DefaultISR ;163
DCD DefaultISR ;164
DCD DefaultISR ;165
DCD DefaultISR ;166
DCD DefaultISR ;167
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
DCD DefaultISR ;240
DCD DefaultISR ;241
DCD DefaultISR ;242
DCD DefaultISR ;243
DCD DefaultISR ;244
DCD DefaultISR ;245
DCD DefaultISR ;246
DCD DefaultISR ;247
DCD DefaultISR ;248
DCD DefaultISR ;249
DCD DefaultISR ;250
DCD DefaultISR ;251
DCD DefaultISR ;252
DCD DefaultISR ;253
DCD DefaultISR ;254
DCD 0xFFFFFFFF ; Reserved for user TRIM value
__Vectors_End
SECTION FlashConfig:CODE
__FlashConfig
DCD 0xFFFFFFFF
DCD 0xFFFFFFFF
DCD 0xFFFFFFFF
DCD 0xFFFFFFFE
__FlashConfig_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__vector_table
STR R1, [R0]
LDR R2, [R1]
MSR MSP, R2
LDR R0, =SystemInit
BLX R0
CPSIE I ; Unmask interrupts
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B .
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B .
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK DMA0_DMA16_IRQHandler
PUBWEAK DMA0_DMA16_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA0_DMA16_IRQHandler
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
PUBWEAK DMA1_DMA17_IRQHandler
PUBWEAK DMA1_DMA17_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA1_DMA17_IRQHandler
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
PUBWEAK DMA2_DMA18_IRQHandler
PUBWEAK DMA2_DMA18_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA2_DMA18_IRQHandler
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
PUBWEAK DMA3_DMA19_IRQHandler
PUBWEAK DMA3_DMA19_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA3_DMA19_IRQHandler
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
PUBWEAK DMA4_DMA20_IRQHandler
PUBWEAK DMA4_DMA20_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA4_DMA20_IRQHandler
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
PUBWEAK DMA5_DMA21_IRQHandler
PUBWEAK DMA5_DMA21_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA5_DMA21_IRQHandler
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
PUBWEAK DMA6_DMA22_IRQHandler
PUBWEAK DMA6_DMA22_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA6_DMA22_IRQHandler
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
PUBWEAK DMA7_DMA23_IRQHandler
PUBWEAK DMA7_DMA23_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA7_DMA23_IRQHandler
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
PUBWEAK DMA8_DMA24_IRQHandler
PUBWEAK DMA8_DMA24_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA8_DMA24_IRQHandler
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
PUBWEAK DMA9_DMA25_IRQHandler
PUBWEAK DMA9_DMA25_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA9_DMA25_IRQHandler
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
PUBWEAK DMA10_DMA26_IRQHandler
PUBWEAK DMA10_DMA26_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA10_DMA26_IRQHandler
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
PUBWEAK DMA11_DMA27_IRQHandler
PUBWEAK DMA11_DMA27_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA11_DMA27_IRQHandler
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
PUBWEAK DMA12_DMA28_IRQHandler
PUBWEAK DMA12_DMA28_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA12_DMA28_IRQHandler
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
PUBWEAK DMA13_DMA29_IRQHandler
PUBWEAK DMA13_DMA29_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA13_DMA29_IRQHandler
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
PUBWEAK DMA14_DMA30_IRQHandler
PUBWEAK DMA14_DMA30_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA14_DMA30_IRQHandler
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
PUBWEAK DMA15_DMA31_IRQHandler
PUBWEAK DMA15_DMA31_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA15_DMA31_IRQHandler
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
PUBWEAK DMA_Error_IRQHandler
PUBWEAK DMA_Error_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA_Error_IRQHandler
LDR R0, =DMA_Error_DriverIRQHandler
BX R0
PUBWEAK MCM_IRQHandler
PUBWEAK FTFE_IRQHandler
PUBWEAK Read_Collision_IRQHandler
PUBWEAK LVD_LVW_IRQHandler
PUBWEAK LLWU_IRQHandler
PUBWEAK WDOG_EWM_IRQHandler
PUBWEAK RNG_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C0_IRQHandler
LDR R0, =I2C0_DriverIRQHandler
BX R0
PUBWEAK I2C1_IRQHandler
PUBWEAK I2C1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C1_IRQHandler
LDR R0, =I2C1_DriverIRQHandler
BX R0
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI0_IRQHandler
LDR R0, =SPI0_DriverIRQHandler
BX R0
PUBWEAK SPI1_IRQHandler
PUBWEAK SPI1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI1_IRQHandler
LDR R0, =SPI1_DriverIRQHandler
BX R0
PUBWEAK I2S0_Tx_IRQHandler
PUBWEAK I2S0_Tx_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2S0_Tx_IRQHandler
LDR R0, =I2S0_Tx_DriverIRQHandler
BX R0
PUBWEAK I2S0_Rx_IRQHandler
PUBWEAK I2S0_Rx_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2S0_Rx_IRQHandler
LDR R0, =I2S0_Rx_DriverIRQHandler
BX R0
PUBWEAK Reserved46_IRQHandler
PUBWEAK UART0_RX_TX_IRQHandler
PUBWEAK UART0_RX_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART0_RX_TX_IRQHandler
LDR R0, =UART0_RX_TX_DriverIRQHandler
BX R0
PUBWEAK UART0_ERR_IRQHandler
PUBWEAK UART0_ERR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART0_ERR_IRQHandler
LDR R0, =UART0_ERR_DriverIRQHandler
BX R0
PUBWEAK UART1_RX_TX_IRQHandler
PUBWEAK UART1_RX_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART1_RX_TX_IRQHandler
LDR R0, =UART1_RX_TX_DriverIRQHandler
BX R0
PUBWEAK UART1_ERR_IRQHandler
PUBWEAK UART1_ERR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART1_ERR_IRQHandler
LDR R0, =UART1_ERR_DriverIRQHandler
BX R0
PUBWEAK UART2_RX_TX_IRQHandler
PUBWEAK UART2_RX_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART2_RX_TX_IRQHandler
LDR R0, =UART2_RX_TX_DriverIRQHandler
BX R0
PUBWEAK UART2_ERR_IRQHandler
PUBWEAK UART2_ERR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART2_ERR_IRQHandler
LDR R0, =UART2_ERR_DriverIRQHandler
BX R0
PUBWEAK UART3_RX_TX_IRQHandler
PUBWEAK UART3_RX_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART3_RX_TX_IRQHandler
LDR R0, =UART3_RX_TX_DriverIRQHandler
BX R0
PUBWEAK UART3_ERR_IRQHandler
PUBWEAK UART3_ERR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART3_ERR_IRQHandler
LDR R0, =UART3_ERR_DriverIRQHandler
BX R0
PUBWEAK ADC0_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK CMP1_IRQHandler
PUBWEAK FTM0_IRQHandler
PUBWEAK FTM1_IRQHandler
PUBWEAK FTM2_IRQHandler
PUBWEAK CMT_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK RTC_Seconds_IRQHandler
PUBWEAK PIT0_IRQHandler
PUBWEAK PIT1_IRQHandler
PUBWEAK PIT2_IRQHandler
PUBWEAK PIT3_IRQHandler
PUBWEAK PDB0_IRQHandler
PUBWEAK USB0_IRQHandler
PUBWEAK USBDCD_IRQHandler
PUBWEAK Reserved71_IRQHandler
PUBWEAK DAC0_IRQHandler
PUBWEAK MCG_IRQHandler
PUBWEAK LPTMR0_IRQHandler
PUBWEAK PORTA_IRQHandler
PUBWEAK PORTB_IRQHandler
PUBWEAK PORTC_IRQHandler
PUBWEAK PORTD_IRQHandler
PUBWEAK PORTE_IRQHandler
PUBWEAK SWI_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK SPI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI2_IRQHandler
LDR R0, =SPI2_DriverIRQHandler
BX R0
PUBWEAK UART4_RX_TX_IRQHandler
PUBWEAK UART4_RX_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART4_RX_TX_IRQHandler
LDR R0, =UART4_RX_TX_DriverIRQHandler
BX R0
PUBWEAK UART4_ERR_IRQHandler
PUBWEAK UART4_ERR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART4_ERR_IRQHandler
LDR R0, =UART4_ERR_DriverIRQHandler
BX R0
PUBWEAK Reserved84_IRQHandler
PUBWEAK Reserved85_IRQHandler
PUBWEAK CMP2_IRQHandler
PUBWEAK FTM3_IRQHandler
PUBWEAK DAC1_IRQHandler
PUBWEAK ADC1_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK I2C2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C2_IRQHandler
LDR R0, =I2C2_DriverIRQHandler
BX R0
PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
PUBWEAK CAN0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN0_ORed_Message_buffer_IRQHandler
LDR R0, =CAN0_DriverIRQHandler
BX R0
PUBWEAK CAN0_Bus_Off_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN0_Bus_Off_IRQHandler
LDR R0, =CAN0_DriverIRQHandler
BX R0
PUBWEAK CAN0_Error_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN0_Error_IRQHandler
LDR R0, =CAN0_DriverIRQHandler
BX R0
PUBWEAK CAN0_Tx_Warning_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN0_Tx_Warning_IRQHandler
LDR R0, =CAN0_DriverIRQHandler
BX R0
PUBWEAK CAN0_Rx_Warning_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN0_Rx_Warning_IRQHandler
LDR R0, =CAN0_DriverIRQHandler
BX R0
PUBWEAK CAN0_Wake_Up_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN0_Wake_Up_IRQHandler
LDR R0, =CAN0_DriverIRQHandler
BX R0
PUBWEAK SDHC_IRQHandler
PUBWEAK SDHC_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SDHC_IRQHandler
LDR R0, =SDHC_DriverIRQHandler
BX R0
PUBWEAK ENET_1588_Timer_IRQHandler
PUBWEAK ENET_1588_Timer_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_1588_Timer_IRQHandler
LDR R0, =ENET_1588_Timer_DriverIRQHandler
BX R0
PUBWEAK ENET_Transmit_IRQHandler
PUBWEAK ENET_Transmit_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_Transmit_IRQHandler
LDR R0, =ENET_Transmit_DriverIRQHandler
BX R0
PUBWEAK ENET_Receive_IRQHandler
PUBWEAK ENET_Receive_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_Receive_IRQHandler
LDR R0, =ENET_Receive_DriverIRQHandler
BX R0
PUBWEAK ENET_Error_IRQHandler
PUBWEAK ENET_Error_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_Error_IRQHandler
LDR R0, =ENET_Error_DriverIRQHandler
BX R0
PUBWEAK LPUART0_IRQHandler
PUBWEAK LPUART0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART0_IRQHandler
LDR R0, =LPUART0_DriverIRQHandler
BX R0
PUBWEAK TSI0_IRQHandler
PUBWEAK TPM1_IRQHandler
PUBWEAK TPM2_IRQHandler
PUBWEAK USBHSDCD_IRQHandler
PUBWEAK I2C3_IRQHandler
PUBWEAK I2C3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C3_IRQHandler
LDR R0, =I2C3_DriverIRQHandler
BX R0
PUBWEAK CMP3_IRQHandler
PUBWEAK USBHS_IRQHandler
PUBWEAK CAN1_ORed_Message_buffer_IRQHandler
PUBWEAK CAN1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_ORed_Message_buffer_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN1_Bus_Off_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_Bus_Off_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN1_Error_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_Error_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN1_Tx_Warning_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_Tx_Warning_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN1_Rx_Warning_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_Rx_Warning_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN1_Wake_Up_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_Wake_Up_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK DefaultISR
SECTION .text:CODE:REORDER:NOROOT(1)
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_Error_DriverIRQHandler
MCM_IRQHandler
FTFE_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLWU_IRQHandler
WDOG_EWM_IRQHandler
RNG_IRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
SPI0_DriverIRQHandler
SPI1_DriverIRQHandler
I2S0_Tx_DriverIRQHandler
I2S0_Rx_DriverIRQHandler
Reserved46_IRQHandler
UART0_RX_TX_DriverIRQHandler
UART0_ERR_DriverIRQHandler
UART1_RX_TX_DriverIRQHandler
UART1_ERR_DriverIRQHandler
UART2_RX_TX_DriverIRQHandler
UART2_ERR_DriverIRQHandler
UART3_RX_TX_DriverIRQHandler
UART3_ERR_DriverIRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved71_IRQHandler
DAC0_IRQHandler
MCG_IRQHandler
LPTMR0_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
SPI2_DriverIRQHandler
UART4_RX_TX_DriverIRQHandler
UART4_ERR_DriverIRQHandler
Reserved84_IRQHandler
Reserved85_IRQHandler
CMP2_IRQHandler
FTM3_IRQHandler
DAC1_IRQHandler
ADC1_IRQHandler
I2C2_DriverIRQHandler
CAN0_DriverIRQHandler
SDHC_DriverIRQHandler
ENET_1588_Timer_DriverIRQHandler
ENET_Transmit_DriverIRQHandler
ENET_Receive_DriverIRQHandler
ENET_Error_DriverIRQHandler
LPUART0_DriverIRQHandler
TSI0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
USBHSDCD_IRQHandler
I2C3_DriverIRQHandler
CMP3_IRQHandler
USBHS_IRQHandler
CAN1_DriverIRQHandler
DefaultISR
B DefaultISR
END

13
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/cmsis.h Normal file
View File

@@ -0,0 +1,13 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "fsl_device_registers.h"
#include "cmsis_nvic.h"
#endif

45
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/cmsis_nvic.h Normal file
View File

@@ -0,0 +1,45 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
extern uint32_t Image$$VECTOR_RAM$$Base[];
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#else
extern uint32_t __VECTOR_RAM[];
#endif
/* Symbols defined by the linker script */
#define NVIC_NUM_VECTORS (16 + 100) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
#endif

57
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h Normal file
View File

@@ -0,0 +1,57 @@
/*
* Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VLQ18) || \
defined(CPU_MK66FX1M0VMD18))
#define K66F18_SERIES
/* CMSIS-style register definitions */
#include "MK66F18.h"
/* CPU specific feature definitions */
#include "MK66F18_features.h"
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DEVICE_REGISTERS_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

249
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c Normal file
View File

@@ -0,0 +1,249 @@
/*
** ###################################################################
** Processors: MK66FN2M0VLQ18
** MK66FN2M0VMD18
** MK66FX1M0VLQ18
** MK66FX1M0VMD18
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b170112
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2013-09-02)
** Initial version.
** - rev. 2.0 (2014-02-17)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** Update according to reference manual rev. 2
** - rev. 2.1 (2014-04-16)
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** - rev. 2.2 (2014-10-14)
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
** - rev. 2.3 (2014-11-20)
** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
** Update of SystemInit() to use 16MHz external crystal.
** - rev. 2.4 (2015-02-19)
** Renamed interrupt vector LLW to LLWU.
** - rev. 3.0 (2015-03-25)
** Registers updated according to the reference manual revision 1, March 2015
**
** ###################################################################
*/
/*!
* @file MK66F18
* @version 3.0
* @date 2015-03-25
* @brief Device specific configuration file for MK66F18 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "fsl_device_registers.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
/* Watchdog disable */
#if (DISABLE_WDOG)
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#endif /* (DISABLE_WDOG) */
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint16_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
case 0x38U:
Divider = 1536U;
break;
case 0x30U:
Divider = 1280U;
break;
default:
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
break;
}
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
}
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x00U:
MCGOUTClock *= 640U;
break;
case 0x20U:
MCGOUTClock *= 1280U;
break;
case 0x40U:
MCGOUTClock *= 1920U;
break;
case 0x60U:
MCGOUTClock *= 2560U;
break;
case 0x80U:
MCGOUTClock *= 732U;
break;
case 0xA0U:
MCGOUTClock *= 1464U;
break;
case 0xC0U:
MCGOUTClock *= 2197U;
break;
case 0xE0U:
MCGOUTClock *= 2929U;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
if ((MCG->C11 & MCG_C11_PLLCS_MASK) == 0x00U) {
/* PLL is selected */
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
MCGOUTClock *= Divider; /* Calculate the VCO output clock */
MCGOUTClock /= 2; /* Calculate the MCG output clock */
} else {
/* External PLL is selected */
if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) {
MCGOUTClock = CPU_XTAL_CLK_HZ;
} else {
Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4);
if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) {
Divider *= 0x04U;
} else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
Divider *= 0x02U;
}
MCGOUTClock = (uint32_t)(480000000 / Divider);
MCGOUTClock *= 18;
}
}
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
/* External reference clock is selected */
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
case 0x00U:
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
break;
case 0x01U:
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
break;
case 0x02U:
default:
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
break;
}
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

154
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h Normal file
View File

@@ -0,0 +1,154 @@
/*
** ###################################################################
** Processors: MK66FN2M0VLQ18
** MK66FN2M0VMD18
** MK66FX1M0VLQ18
** MK66FX1M0VMD18
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
** Version: rev. 3.0, 2015-03-25
** Build: b170112
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright (c) 2016 Freescale Semiconductor, Inc.
** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** o Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** o Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2013-09-02)
** Initial version.
** - rev. 2.0 (2014-02-17)
** Register accessor macros added to the memory map.
** Symbols for Processor Expert memory map compatibility added to the memory map.
** Startup file for gcc has been updated according to CMSIS 3.2.
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** Update according to reference manual rev. 2
** - rev. 2.1 (2014-04-16)
** Update of SystemInit() and SystemCoreClockUpdate() functions.
** - rev. 2.2 (2014-10-14)
** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
** - rev. 2.3 (2014-11-20)
** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
** Update of SystemInit() to use 16MHz external crystal.
** - rev. 2.4 (2015-02-19)
** Renamed interrupt vector LLW to LLWU.
** - rev. 3.0 (2015-03-25)
** Registers updated according to the reference manual revision 1, March 2015
**
** ###################################################################
*/
/*!
* @file MK66F18
* @version 3.0
* @date 2015-03-25
* @brief Device specific configuration file for MK66F18 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_MK66F18_H_
#define _SYSTEM_MK66F18_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 16000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
#define CPU_XTAL32k_CLK_HZ 32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
/* RTC oscillator setting */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
#define DEFAULT_SYSTEM_CLOCK 20971520u
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MK66F18_H_ */