Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
File diff suppressed because it is too large
Load Diff
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Load Diff
@@ -0,0 +1,131 @@
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#! armcc -E
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/*
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** ###################################################################
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** Processors: MK82FN256CAx15
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** MK82FN256VDC15
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** MK82FN256VLL15
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** MK82FN256VLQ15
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
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** Version: rev. 1.2, 2015-07-29
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** Build: b160406
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**
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** Abstract:
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** Linker file for the Keil ARM C/C++ Compiler
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**
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||||
** Copyright (c) 2016 Freescale Semiconductor, Inc.
|
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** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
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||||
** ###################################################################
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*/
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#define __ram_vector_table__ 1
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#if (defined(__ram_vector_table__))
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#define __ram_vector_table_size__ 0x000003C0
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#else
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#define __ram_vector_table_size__ 0x00000000
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#endif
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#define m_interrupts_start 0x00000000
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#define m_interrupts_size 0x000003C0
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#define m_bootloader_config_start 0x000003C0
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#define m_bootloader_config_size 0x00000040
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#define m_flash_config_start 0x00000400
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#define m_flash_config_size 0x00000010
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#define m_text_start 0x00000410
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#define m_text_size 0x0003FBF0
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#define m_interrupts_ram_start 0x1FFF0000
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#define m_interrupts_ram_size __ram_vector_table_size__
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#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
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#define m_data_size (0x00010000 - m_interrupts_ram_size)
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#define m_data_2_start 0x20000000
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#define m_data_2_size 0x00030000
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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/* Sizes */
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#if (defined(__stack_size__))
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#define Stack_Size __stack_size__
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#else
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#define Stack_Size MBED_BOOT_STACK_SIZE
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#endif
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#if (defined(__heap_size__))
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#define Heap_Size __heap_size__
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#else
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#define Heap_Size 0x0400
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#endif
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LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
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VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
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* (RESET,+FIRST)
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}
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ER_m_bootloader_config m_bootloader_config_start FIXED m_bootloader_config_size { ; load address = execution address
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* (BootloaderConfig)
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}
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ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
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* (FlashConfig)
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}
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ER_IROM1 m_text_start m_text_size { ; load address = execution address
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* (InRoot$$Sections)
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.ANY (+RO)
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}
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#if (defined(__ram_vector_table__))
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VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
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}
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#else
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VECTOR_RAM m_interrupts_start EMPTY 0 {
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}
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#endif
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RW_m_data m_data_start m_data_size { ; RW data
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.ANY (+RW +ZI)
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}
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RW_m_data_2 m_data_2_start m_data_2_size { ; RW data
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.ANY (+RW +ZI)
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}
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RW_IRAM1 ImageLimit(RW_m_data_2) {
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_2_start + m_data_2_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
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}
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ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down
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}
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}
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@@ -0,0 +1,961 @@
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; * ---------------------------------------------------------------------------------------
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; * @file: startup_MK82F25615.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File
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; * MK82F25615
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; * @version: 1.0
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; * @date: 2015-4-9
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; * @build: b151210
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; * ---------------------------------------------------------------------------------------
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; *
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; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
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; * All rights reserved.
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; *
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; * Redistribution and use in source and binary forms, with or without modification,
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; * are permitted provided that the following conditions are met:
|
||||
; *
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||||
; * o Redistributions of source code must retain the above copyright notice, this list
|
||||
; * of conditions and the following disclaimer.
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||||
; *
|
||||
; * o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
; * list of conditions and the following disclaimer in the documentation and/or
|
||||
; * other materials provided with the distribution.
|
||||
; *
|
||||
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
; * contributors may be used to endorse or promote products derived from this
|
||||
; * software without specific prior written permission.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ;Top of Stack
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DCD Reset_Handler ;Reset Handler
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DCD NMI_Handler ;NMI Handler
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DCD HardFault_Handler ;Hard Fault Handler
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DCD MemManage_Handler ;MPU Fault Handler
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DCD BusFault_Handler ;Bus Fault Handler
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DCD UsageFault_Handler ;Usage Fault Handler
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD SVC_Handler ;SVCall Handler
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DCD DebugMon_Handler ;Debug Monitor Handler
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DCD 0 ;Reserved
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DCD PendSV_Handler ;PendSV Handler
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DCD SysTick_Handler ;SysTick Handler
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;External Interrupts
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DCD DMA0_DMA16_IRQHandler ;DMA channel 0,16 transfer complete
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DCD DMA1_DMA17_IRQHandler ;DMA channel 1,17 transfer complete
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DCD DMA2_DMA18_IRQHandler ;DMA channel 2,18 transfer complete
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DCD DMA3_DMA19_IRQHandler ;DMA channel 3,19 transfer complete
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DCD DMA4_DMA20_IRQHandler ;DMA channel 4,20 transfer complete
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DCD DMA5_DMA21_IRQHandler ;DMA channel 5,21 transfer complete
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DCD DMA6_DMA22_IRQHandler ;DMA channel 6,22 transfer complete
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DCD DMA7_DMA23_IRQHandler ;DMA channel 7,23 transfer complete
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DCD DMA8_DMA24_IRQHandler ;DMA channel 8,24 transfer complete
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DCD DMA9_DMA25_IRQHandler ;DMA channel 9,25 transfer complete
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DCD DMA10_DMA26_IRQHandler ;DMA channel 10,26 transfer complete
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DCD DMA11_DMA27_IRQHandler ;DMA channel 11,27 transfer complete
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DCD DMA12_DMA28_IRQHandler ;DMA channel 12,28 transfer complete
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DCD DMA13_DMA29_IRQHandler ;DMA channel 13,29 transfer complete
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DCD DMA14_DMA30_IRQHandler ;DMA channel 14,30 transfer complete
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DCD DMA15_DMA31_IRQHandler ;DMA channel 15,31 transfer complete
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DCD DMA_Error_IRQHandler ;DMA channel 0 - 31 error
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DCD MCM_IRQHandler ;MCM normal interrupt
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DCD FTFA_IRQHandler ;FTFA command complete
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DCD Read_Collision_IRQHandler ;FTFA read collision
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DCD LVD_LVW_IRQHandler ;PMC controller low-voltage detect, low-voltage warning
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DCD LLWU_IRQHandler ;Low leakage wakeup unit
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DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM
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DCD TRNG0_IRQHandler ;True randon number generator
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DCD I2C0_IRQHandler ;Inter-integrated circuit 0
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DCD I2C1_IRQHandler ;Inter-integrated circuit 1
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DCD SPI0_IRQHandler ;Serial peripheral Interface 0
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DCD SPI1_IRQHandler ;Serial peripheral Interface 1
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DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt
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DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt
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DCD LPUART0_IRQHandler ;LPUART0 receive/transmit/error interrupt
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DCD LPUART1_IRQHandler ;LPUART1 receive/transmit/error interrupt
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DCD LPUART2_IRQHandler ;LPUART2 receive/transmit/error interrupt
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DCD LPUART3_IRQHandler ;LPUART3 receive/transmit/error interrupt
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DCD LPUART4_IRQHandler ;LPUART4 receive/transmit/error interrupt
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DCD Reserved51_IRQHandler ;Reserved interrupt
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DCD Reserved52_IRQHandler ;Reserved interrupt
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DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt
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DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt
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DCD ADC0_IRQHandler ;Analog-to-digital converter 0
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DCD CMP0_IRQHandler ;Comparator 0
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DCD CMP1_IRQHandler ;Comparator 1
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DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt
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||||
DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt
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||||
DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt
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||||
DCD CMT_IRQHandler ;Carrier modulator transmitter
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DCD RTC_IRQHandler ;Real time clock
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||||
DCD RTC_Seconds_IRQHandler ;Real time clock seconds
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||||
DCD PIT0CH0_IRQHandler ;Periodic interrupt timer 0 channel 0
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||||
DCD PIT0CH1_IRQHandler ;Periodic interrupt timer 0 channel 1
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||||
DCD PIT0CH2_IRQHandler ;Periodic interrupt timer 0 channel 2
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||||
DCD PIT0CH3_IRQHandler ;Periodic interrupt timer 0 channel 3
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||||
DCD PDB0_IRQHandler ;Programmable delay block
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||||
DCD USB0_IRQHandler ;USB OTG interrupt
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||||
DCD USBDCD_IRQHandler ;USB charger detect
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||||
DCD Reserved71_IRQHandler ;Reserved interrupt
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||||
DCD DAC0_IRQHandler ;Digital-to-analog converter 0
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||||
DCD MCG_IRQHandler ;Multipurpose clock generator
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||||
DCD LPTMR0_LPTMR1_IRQHandler ;Single interrupt vector for Low Power Timer 0 and 1
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||||
DCD PORTA_IRQHandler ;Port A pin detect interrupt
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||||
DCD PORTB_IRQHandler ;Port B pin detect interrupt
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||||
DCD PORTC_IRQHandler ;Port C pin detect interrupt
|
||||
DCD PORTD_IRQHandler ;Port D pin detect interrupt
|
||||
DCD PORTE_IRQHandler ;Port E pin detect interrupt
|
||||
DCD SWI_IRQHandler ;Software interrupt
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||||
DCD SPI2_IRQHandler ;Serial peripheral Interface 2
|
||||
DCD Reserved82_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved83_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved84_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved85_IRQHandler ;Reserved interrupt
|
||||
DCD FLEXIO0_IRQHandler ;FLEXIO0
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||||
DCD FTM3_IRQHandler ;FlexTimer module 3 fault, overflow and channels interrupt
|
||||
DCD Reserved88_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved89_IRQHandler ;Reserved interrupt
|
||||
DCD I2C2_IRQHandler ;Inter-integrated circuit 2
|
||||
DCD Reserved91_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved92_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved93_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved94_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved95_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved96_IRQHandler ;Reserved interrupt
|
||||
DCD SDHC_IRQHandler ;Secured digital host controller
|
||||
DCD Reserved98_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved99_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved100_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved101_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved102_IRQHandler ;Reserved interrupt
|
||||
DCD TSI0_IRQHandler ;Touch Sensing Input
|
||||
DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
|
||||
DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
|
||||
DCD Reserved106_IRQHandler ;Reserved interrupt
|
||||
DCD I2C3_IRQHandler ;Inter-integrated circuit 3
|
||||
DCD Reserved108_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved109_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved110_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved111_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved112_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved113_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved114_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved115_IRQHandler ;Reserved interrupt
|
||||
DCD QuadSPI0_IRQHandler ;qspi
|
||||
DCD Reserved117_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved118_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved119_IRQHandler ;Reserved interrupt
|
||||
DCD LTC0_IRQHandler ;LP Trusted Cryptography
|
||||
DCD Reserved121_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved122_IRQHandler ;Reserved interrupt
|
||||
DCD DefaultISR ;123
|
||||
DCD DefaultISR ;124
|
||||
DCD DefaultISR ;125
|
||||
DCD DefaultISR ;126
|
||||
DCD DefaultISR ;127
|
||||
DCD DefaultISR ;128
|
||||
DCD DefaultISR ;129
|
||||
DCD DefaultISR ;130
|
||||
DCD DefaultISR ;131
|
||||
DCD DefaultISR ;132
|
||||
DCD DefaultISR ;133
|
||||
DCD DefaultISR ;134
|
||||
DCD DefaultISR ;135
|
||||
DCD DefaultISR ;136
|
||||
DCD DefaultISR ;137
|
||||
DCD DefaultISR ;138
|
||||
DCD DefaultISR ;139
|
||||
DCD DefaultISR ;140
|
||||
DCD DefaultISR ;141
|
||||
DCD DefaultISR ;142
|
||||
DCD DefaultISR ;143
|
||||
DCD DefaultISR ;144
|
||||
DCD DefaultISR ;145
|
||||
DCD DefaultISR ;146
|
||||
DCD DefaultISR ;147
|
||||
DCD DefaultISR ;148
|
||||
DCD DefaultISR ;149
|
||||
DCD DefaultISR ;150
|
||||
DCD DefaultISR ;151
|
||||
DCD DefaultISR ;152
|
||||
DCD DefaultISR ;153
|
||||
DCD DefaultISR ;154
|
||||
DCD DefaultISR ;155
|
||||
DCD DefaultISR ;156
|
||||
DCD DefaultISR ;157
|
||||
DCD DefaultISR ;158
|
||||
DCD DefaultISR ;159
|
||||
DCD DefaultISR ;160
|
||||
DCD DefaultISR ;161
|
||||
DCD DefaultISR ;162
|
||||
DCD DefaultISR ;163
|
||||
DCD DefaultISR ;164
|
||||
DCD DefaultISR ;165
|
||||
DCD DefaultISR ;166
|
||||
DCD DefaultISR ;167
|
||||
DCD DefaultISR ;168
|
||||
DCD DefaultISR ;169
|
||||
DCD DefaultISR ;170
|
||||
DCD DefaultISR ;171
|
||||
DCD DefaultISR ;172
|
||||
DCD DefaultISR ;173
|
||||
DCD DefaultISR ;174
|
||||
DCD DefaultISR ;175
|
||||
DCD DefaultISR ;176
|
||||
DCD DefaultISR ;177
|
||||
DCD DefaultISR ;178
|
||||
DCD DefaultISR ;179
|
||||
DCD DefaultISR ;180
|
||||
DCD DefaultISR ;181
|
||||
DCD DefaultISR ;182
|
||||
DCD DefaultISR ;183
|
||||
DCD DefaultISR ;184
|
||||
DCD DefaultISR ;185
|
||||
DCD DefaultISR ;186
|
||||
DCD DefaultISR ;187
|
||||
DCD DefaultISR ;188
|
||||
DCD DefaultISR ;189
|
||||
DCD DefaultISR ;190
|
||||
DCD DefaultISR ;191
|
||||
DCD DefaultISR ;192
|
||||
DCD DefaultISR ;193
|
||||
DCD DefaultISR ;194
|
||||
DCD DefaultISR ;195
|
||||
DCD DefaultISR ;196
|
||||
DCD DefaultISR ;197
|
||||
DCD DefaultISR ;198
|
||||
DCD DefaultISR ;199
|
||||
DCD DefaultISR ;200
|
||||
DCD DefaultISR ;201
|
||||
DCD DefaultISR ;202
|
||||
DCD DefaultISR ;203
|
||||
DCD DefaultISR ;204
|
||||
DCD DefaultISR ;205
|
||||
DCD DefaultISR ;206
|
||||
DCD DefaultISR ;207
|
||||
DCD DefaultISR ;208
|
||||
DCD DefaultISR ;209
|
||||
DCD DefaultISR ;210
|
||||
DCD DefaultISR ;211
|
||||
DCD DefaultISR ;212
|
||||
DCD DefaultISR ;213
|
||||
DCD DefaultISR ;214
|
||||
DCD DefaultISR ;215
|
||||
DCD DefaultISR ;216
|
||||
DCD DefaultISR ;217
|
||||
DCD DefaultISR ;218
|
||||
DCD DefaultISR ;219
|
||||
DCD DefaultISR ;220
|
||||
DCD DefaultISR ;221
|
||||
DCD DefaultISR ;222
|
||||
DCD DefaultISR ;223
|
||||
DCD DefaultISR ;224
|
||||
DCD DefaultISR ;225
|
||||
DCD DefaultISR ;226
|
||||
DCD DefaultISR ;227
|
||||
DCD DefaultISR ;228
|
||||
DCD DefaultISR ;229
|
||||
DCD DefaultISR ;230
|
||||
DCD DefaultISR ;231
|
||||
DCD DefaultISR ;232
|
||||
DCD DefaultISR ;233
|
||||
DCD DefaultISR ;234
|
||||
DCD DefaultISR ;235
|
||||
DCD DefaultISR ;236
|
||||
DCD DefaultISR ;237
|
||||
DCD DefaultISR ;238
|
||||
DCD DefaultISR ;239
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict access to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
|
||||
; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
|
||||
; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
|
||||
; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
|
||||
; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
|
||||
; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
|
||||
; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
|
||||
; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program Flash Region Protect Register 0
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT
|
||||
; <0=> Low-power boot
|
||||
; <1=> Normal boot
|
||||
; <o.1> BOOTPIN_OPT
|
||||
; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
|
||||
; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
|
||||
; <o.2> NMI_DIS
|
||||
; <0=> NMI interrupts are always blocked
|
||||
; <1=> NMI_b pin/interrupts reset default to enabled
|
||||
; <o.5> FAST_INIT
|
||||
; <0=> Slower initialization
|
||||
; <1=> Fast Initialization
|
||||
; <o.6..7> BOOTSRC_SEL
|
||||
; <0=> Boot from Flash
|
||||
; <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
|
||||
; <3=> Boot from ROM and enter boot loader mode.
|
||||
; <i> Boot source selection
|
||||
FOPT EQU 0x3D
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor Key Security Enable
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
AREA FlashConfig, DATA, READONLY
|
||||
__FlashConfig
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
|
||||
DCB FSEC , FOPT , 0xFF , 0xFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
REQUIRE FlashConfig
|
||||
ENDIF
|
||||
|
||||
CPSID I ; Mask interrupts
|
||||
LDR R0, =0xE000ED08
|
||||
LDR R1, =__Vectors
|
||||
STR R1, [R0]
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
CPSIE i ; Unmask interrupts
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DMA0_DMA16_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA0_DMA16_IRQHandler [WEAK]
|
||||
LDR R0, =DMA0_DMA16_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA1_DMA17_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA1_DMA17_IRQHandler [WEAK]
|
||||
LDR R0, =DMA1_DMA17_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA2_DMA18_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA2_DMA18_IRQHandler [WEAK]
|
||||
LDR R0, =DMA2_DMA18_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA3_DMA19_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA3_DMA19_IRQHandler [WEAK]
|
||||
LDR R0, =DMA3_DMA19_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA4_DMA20_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA4_DMA20_IRQHandler [WEAK]
|
||||
LDR R0, =DMA4_DMA20_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA5_DMA21_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA5_DMA21_IRQHandler [WEAK]
|
||||
LDR R0, =DMA5_DMA21_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA6_DMA22_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA6_DMA22_IRQHandler [WEAK]
|
||||
LDR R0, =DMA6_DMA22_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA7_DMA23_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA7_DMA23_IRQHandler [WEAK]
|
||||
LDR R0, =DMA7_DMA23_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA8_DMA24_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA8_DMA24_IRQHandler [WEAK]
|
||||
LDR R0, =DMA8_DMA24_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA9_DMA25_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA9_DMA25_IRQHandler [WEAK]
|
||||
LDR R0, =DMA9_DMA25_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA10_DMA26_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA10_DMA26_IRQHandler [WEAK]
|
||||
LDR R0, =DMA10_DMA26_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA11_DMA27_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA11_DMA27_IRQHandler [WEAK]
|
||||
LDR R0, =DMA11_DMA27_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA12_DMA28_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA12_DMA28_IRQHandler [WEAK]
|
||||
LDR R0, =DMA12_DMA28_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA13_DMA29_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA13_DMA29_IRQHandler [WEAK]
|
||||
LDR R0, =DMA13_DMA29_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA14_DMA30_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA14_DMA30_IRQHandler [WEAK]
|
||||
LDR R0, =DMA14_DMA30_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA15_DMA31_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA15_DMA31_IRQHandler [WEAK]
|
||||
LDR R0, =DMA15_DMA31_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
DMA_Error_IRQHandler\
|
||||
PROC
|
||||
EXPORT DMA_Error_IRQHandler [WEAK]
|
||||
LDR R0, =DMA_Error_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
I2C0_IRQHandler\
|
||||
PROC
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
LDR R0, =I2C0_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
I2C1_IRQHandler\
|
||||
PROC
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
LDR R0, =I2C1_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
SPI0_IRQHandler\
|
||||
PROC
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
LDR R0, =SPI0_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
SPI1_IRQHandler\
|
||||
PROC
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
LDR R0, =SPI1_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
I2S0_Tx_IRQHandler\
|
||||
PROC
|
||||
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
||||
LDR R0, =I2S0_Tx_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
I2S0_Rx_IRQHandler\
|
||||
PROC
|
||||
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
||||
LDR R0, =I2S0_Rx_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
LPUART0_IRQHandler\
|
||||
PROC
|
||||
EXPORT LPUART0_IRQHandler [WEAK]
|
||||
LDR R0, =LPUART0_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
LPUART1_IRQHandler\
|
||||
PROC
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
LDR R0, =LPUART1_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
LPUART2_IRQHandler\
|
||||
PROC
|
||||
EXPORT LPUART2_IRQHandler [WEAK]
|
||||
LDR R0, =LPUART2_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
LPUART3_IRQHandler\
|
||||
PROC
|
||||
EXPORT LPUART3_IRQHandler [WEAK]
|
||||
LDR R0, =LPUART3_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
LPUART4_IRQHandler\
|
||||
PROC
|
||||
EXPORT LPUART4_IRQHandler [WEAK]
|
||||
LDR R0, =LPUART4_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
SPI2_IRQHandler\
|
||||
PROC
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
LDR R0, =SPI2_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
FLEXIO0_IRQHandler\
|
||||
PROC
|
||||
EXPORT FLEXIO0_IRQHandler [WEAK]
|
||||
LDR R0, =FLEXIO0_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
I2C2_IRQHandler\
|
||||
PROC
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
LDR R0, =I2C2_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
SDHC_IRQHandler\
|
||||
PROC
|
||||
EXPORT SDHC_IRQHandler [WEAK]
|
||||
LDR R0, =SDHC_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
I2C3_IRQHandler\
|
||||
PROC
|
||||
EXPORT I2C3_IRQHandler [WEAK]
|
||||
LDR R0, =I2C3_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
QuadSPI0_IRQHandler\
|
||||
PROC
|
||||
EXPORT QuadSPI0_IRQHandler [WEAK]
|
||||
LDR R0, =QuadSPI0_DriverIRQHandler
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
Default_Handler\
|
||||
PROC
|
||||
EXPORT DMA0_DMA16_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA1_DMA17_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA2_DMA18_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA3_DMA19_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA4_DMA20_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA5_DMA21_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA6_DMA22_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA7_DMA23_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA8_DMA24_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA9_DMA25_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA10_DMA26_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA11_DMA27_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA12_DMA28_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA13_DMA29_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA14_DMA30_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA15_DMA31_DriverIRQHandler [WEAK]
|
||||
EXPORT DMA_Error_DriverIRQHandler [WEAK]
|
||||
EXPORT MCM_IRQHandler [WEAK]
|
||||
EXPORT FTFA_IRQHandler [WEAK]
|
||||
EXPORT Read_Collision_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT LLWU_IRQHandler [WEAK]
|
||||
EXPORT WDOG_EWM_IRQHandler [WEAK]
|
||||
EXPORT TRNG0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_DriverIRQHandler [WEAK]
|
||||
EXPORT I2C1_DriverIRQHandler [WEAK]
|
||||
EXPORT SPI0_DriverIRQHandler [WEAK]
|
||||
EXPORT SPI1_DriverIRQHandler [WEAK]
|
||||
EXPORT I2S0_Tx_DriverIRQHandler [WEAK]
|
||||
EXPORT I2S0_Rx_DriverIRQHandler [WEAK]
|
||||
EXPORT LPUART0_DriverIRQHandler [WEAK]
|
||||
EXPORT LPUART1_DriverIRQHandler [WEAK]
|
||||
EXPORT LPUART2_DriverIRQHandler [WEAK]
|
||||
EXPORT LPUART3_DriverIRQHandler [WEAK]
|
||||
EXPORT LPUART4_DriverIRQHandler [WEAK]
|
||||
EXPORT Reserved51_IRQHandler [WEAK]
|
||||
EXPORT Reserved52_IRQHandler [WEAK]
|
||||
EXPORT EMVSIM0_IRQHandler [WEAK]
|
||||
EXPORT EMVSIM1_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT CMP1_IRQHandler [WEAK]
|
||||
EXPORT FTM0_IRQHandler [WEAK]
|
||||
EXPORT FTM1_IRQHandler [WEAK]
|
||||
EXPORT FTM2_IRQHandler [WEAK]
|
||||
EXPORT CMT_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||
EXPORT PIT0CH0_IRQHandler [WEAK]
|
||||
EXPORT PIT0CH1_IRQHandler [WEAK]
|
||||
EXPORT PIT0CH2_IRQHandler [WEAK]
|
||||
EXPORT PIT0CH3_IRQHandler [WEAK]
|
||||
EXPORT PDB0_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USBDCD_IRQHandler [WEAK]
|
||||
EXPORT Reserved71_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT MCG_IRQHandler [WEAK]
|
||||
EXPORT LPTMR0_LPTMR1_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTB_IRQHandler [WEAK]
|
||||
EXPORT PORTC_IRQHandler [WEAK]
|
||||
EXPORT PORTD_IRQHandler [WEAK]
|
||||
EXPORT PORTE_IRQHandler [WEAK]
|
||||
EXPORT SWI_IRQHandler [WEAK]
|
||||
EXPORT SPI2_DriverIRQHandler [WEAK]
|
||||
EXPORT Reserved82_IRQHandler [WEAK]
|
||||
EXPORT Reserved83_IRQHandler [WEAK]
|
||||
EXPORT Reserved84_IRQHandler [WEAK]
|
||||
EXPORT Reserved85_IRQHandler [WEAK]
|
||||
EXPORT FLEXIO0_DriverIRQHandler [WEAK]
|
||||
EXPORT FTM3_IRQHandler [WEAK]
|
||||
EXPORT Reserved88_IRQHandler [WEAK]
|
||||
EXPORT Reserved89_IRQHandler [WEAK]
|
||||
EXPORT I2C2_DriverIRQHandler [WEAK]
|
||||
EXPORT Reserved91_IRQHandler [WEAK]
|
||||
EXPORT Reserved92_IRQHandler [WEAK]
|
||||
EXPORT Reserved93_IRQHandler [WEAK]
|
||||
EXPORT Reserved94_IRQHandler [WEAK]
|
||||
EXPORT Reserved95_IRQHandler [WEAK]
|
||||
EXPORT Reserved96_IRQHandler [WEAK]
|
||||
EXPORT SDHC_DriverIRQHandler [WEAK]
|
||||
EXPORT Reserved98_IRQHandler [WEAK]
|
||||
EXPORT Reserved99_IRQHandler [WEAK]
|
||||
EXPORT Reserved100_IRQHandler [WEAK]
|
||||
EXPORT Reserved101_IRQHandler [WEAK]
|
||||
EXPORT Reserved102_IRQHandler [WEAK]
|
||||
EXPORT TSI0_IRQHandler [WEAK]
|
||||
EXPORT TPM1_IRQHandler [WEAK]
|
||||
EXPORT TPM2_IRQHandler [WEAK]
|
||||
EXPORT Reserved106_IRQHandler [WEAK]
|
||||
EXPORT I2C3_DriverIRQHandler [WEAK]
|
||||
EXPORT Reserved108_IRQHandler [WEAK]
|
||||
EXPORT Reserved109_IRQHandler [WEAK]
|
||||
EXPORT Reserved110_IRQHandler [WEAK]
|
||||
EXPORT Reserved111_IRQHandler [WEAK]
|
||||
EXPORT Reserved112_IRQHandler [WEAK]
|
||||
EXPORT Reserved113_IRQHandler [WEAK]
|
||||
EXPORT Reserved114_IRQHandler [WEAK]
|
||||
EXPORT Reserved115_IRQHandler [WEAK]
|
||||
EXPORT QuadSPI0_DriverIRQHandler [WEAK]
|
||||
EXPORT Reserved117_IRQHandler [WEAK]
|
||||
EXPORT Reserved118_IRQHandler [WEAK]
|
||||
EXPORT Reserved119_IRQHandler [WEAK]
|
||||
EXPORT LTC0_IRQHandler [WEAK]
|
||||
EXPORT Reserved121_IRQHandler [WEAK]
|
||||
EXPORT Reserved122_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
DMA0_DMA16_DriverIRQHandler
|
||||
DMA1_DMA17_DriverIRQHandler
|
||||
DMA2_DMA18_DriverIRQHandler
|
||||
DMA3_DMA19_DriverIRQHandler
|
||||
DMA4_DMA20_DriverIRQHandler
|
||||
DMA5_DMA21_DriverIRQHandler
|
||||
DMA6_DMA22_DriverIRQHandler
|
||||
DMA7_DMA23_DriverIRQHandler
|
||||
DMA8_DMA24_DriverIRQHandler
|
||||
DMA9_DMA25_DriverIRQHandler
|
||||
DMA10_DMA26_DriverIRQHandler
|
||||
DMA11_DMA27_DriverIRQHandler
|
||||
DMA12_DMA28_DriverIRQHandler
|
||||
DMA13_DMA29_DriverIRQHandler
|
||||
DMA14_DMA30_DriverIRQHandler
|
||||
DMA15_DMA31_DriverIRQHandler
|
||||
DMA_Error_DriverIRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLWU_IRQHandler
|
||||
WDOG_EWM_IRQHandler
|
||||
TRNG0_IRQHandler
|
||||
I2C0_DriverIRQHandler
|
||||
I2C1_DriverIRQHandler
|
||||
SPI0_DriverIRQHandler
|
||||
SPI1_DriverIRQHandler
|
||||
I2S0_Tx_DriverIRQHandler
|
||||
I2S0_Rx_DriverIRQHandler
|
||||
LPUART0_DriverIRQHandler
|
||||
LPUART1_DriverIRQHandler
|
||||
LPUART2_DriverIRQHandler
|
||||
LPUART3_DriverIRQHandler
|
||||
LPUART4_DriverIRQHandler
|
||||
Reserved51_IRQHandler
|
||||
Reserved52_IRQHandler
|
||||
EMVSIM0_IRQHandler
|
||||
EMVSIM1_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0CH0_IRQHandler
|
||||
PIT0CH1_IRQHandler
|
||||
PIT0CH2_IRQHandler
|
||||
PIT0CH3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
Reserved71_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTMR0_LPTMR1_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
SWI_IRQHandler
|
||||
SPI2_DriverIRQHandler
|
||||
Reserved82_IRQHandler
|
||||
Reserved83_IRQHandler
|
||||
Reserved84_IRQHandler
|
||||
Reserved85_IRQHandler
|
||||
FLEXIO0_DriverIRQHandler
|
||||
FTM3_IRQHandler
|
||||
Reserved88_IRQHandler
|
||||
Reserved89_IRQHandler
|
||||
I2C2_DriverIRQHandler
|
||||
Reserved91_IRQHandler
|
||||
Reserved92_IRQHandler
|
||||
Reserved93_IRQHandler
|
||||
Reserved94_IRQHandler
|
||||
Reserved95_IRQHandler
|
||||
Reserved96_IRQHandler
|
||||
SDHC_DriverIRQHandler
|
||||
Reserved98_IRQHandler
|
||||
Reserved99_IRQHandler
|
||||
Reserved100_IRQHandler
|
||||
Reserved101_IRQHandler
|
||||
Reserved102_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
Reserved106_IRQHandler
|
||||
I2C3_DriverIRQHandler
|
||||
Reserved108_IRQHandler
|
||||
Reserved109_IRQHandler
|
||||
Reserved110_IRQHandler
|
||||
Reserved111_IRQHandler
|
||||
Reserved112_IRQHandler
|
||||
Reserved113_IRQHandler
|
||||
Reserved114_IRQHandler
|
||||
Reserved115_IRQHandler
|
||||
QuadSPI0_DriverIRQHandler
|
||||
Reserved117_IRQHandler
|
||||
Reserved118_IRQHandler
|
||||
Reserved119_IRQHandler
|
||||
LTC0_IRQHandler
|
||||
Reserved121_IRQHandler
|
||||
Reserved122_IRQHandler
|
||||
DefaultISR
|
||||
B DefaultISR
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,278 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK82FN256CAx15
|
||||
** MK82FN256VDC15
|
||||
** MK82FN256VLL15
|
||||
** MK82FN256VLQ15
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
|
||||
** Version: rev. 1.2, 2015-07-29
|
||||
** Build: b160613
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright (c) 2016 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__ram_vector_table__ = 1;
|
||||
|
||||
/* With the RTOS in use, this does not affect the main stack size. The size of
|
||||
* the stack where main runs is determined via the RTOS. */
|
||||
__stack_size__ = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x03C0 : 0x0;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000003C0
|
||||
m_bootloader_config (RX) : ORIGIN = 0x000003C0, LENGTH = 0x00000040
|
||||
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
|
||||
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0003FBF0
|
||||
m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
|
||||
m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into internal flash */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} > m_interrupts
|
||||
|
||||
.bootloader_config :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.BootloaderConfig)) /* Bootloader Configuration Area (BCA) */
|
||||
. = ALIGN(8);
|
||||
} > m_bootloader_config
|
||||
|
||||
.flash_config :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
|
||||
. = ALIGN(8);
|
||||
} > m_flash_config
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(8);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.interrupts_ram :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__VECTOR_RAM__ = .;
|
||||
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
|
||||
*(.m_interrupts_ram) /* This is a user defined section */
|
||||
. += M_VECTOR_RAM_SIZE;
|
||||
. = ALIGN(8);
|
||||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(8);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x00;
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(8);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
. = ALIGN(512);
|
||||
USB_RAM_START = .;
|
||||
. += USB_RAM_GAP;
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. = ORIGIN(m_data_2) + LENGTH(m_data_2) - STACK_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data_2
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data_2
|
||||
|
||||
m_usb_bdt USB_RAM_START (NOLOAD) :
|
||||
{
|
||||
*(m_usb_bdt)
|
||||
USB_RAM_BDT_END = .;
|
||||
}
|
||||
|
||||
m_usb_global USB_RAM_BDT_END (NOLOAD) :
|
||||
{
|
||||
*(m_usb_global)
|
||||
}
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
|
||||
}
|
||||
|
||||
@@ -0,0 +1,868 @@
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* @file: startup_MK82F25615.s */
|
||||
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
|
||||
/* MK82F25615 */
|
||||
/* @version: 1.0 */
|
||||
/* @date: 2015-4-9 */
|
||||
/* @build: b151210 */
|
||||
/* ---------------------------------------------------------------------------------------*/
|
||||
/* */
|
||||
/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without modification, */
|
||||
/* are permitted provided that the following conditions are met: */
|
||||
/* */
|
||||
/* o Redistributions of source code must retain the above copyright notice, this list */
|
||||
/* of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* o Redistributions in binary form must reproduce the above copyright notice, this */
|
||||
/* list of conditions and the following disclaimer in the documentation and/or */
|
||||
/* other materials provided with the distribution. */
|
||||
/* */
|
||||
/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
|
||||
/* contributors may be used to endorse or promote products derived from this */
|
||||
/* software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
|
||||
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
|
||||
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
|
||||
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
|
||||
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
|
||||
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
|
||||
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
|
||||
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
|
||||
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/*****************************************************************************/
|
||||
/* Version: GCC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .isr_vector, "a"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler*/
|
||||
.long HardFault_Handler /* Hard Fault Handler*/
|
||||
.long MemManage_Handler /* MPU Fault Handler*/
|
||||
.long BusFault_Handler /* Bus Fault Handler*/
|
||||
.long UsageFault_Handler /* Usage Fault Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long SVC_Handler /* SVCall Handler*/
|
||||
.long DebugMon_Handler /* Debug Monitor Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long PendSV_Handler /* PendSV Handler*/
|
||||
.long SysTick_Handler /* SysTick Handler*/
|
||||
|
||||
/* External Interrupts*/
|
||||
.long DMA0_DMA16_IRQHandler /* DMA channel 0,16 transfer complete*/
|
||||
.long DMA1_DMA17_IRQHandler /* DMA channel 1,17 transfer complete*/
|
||||
.long DMA2_DMA18_IRQHandler /* DMA channel 2,18 transfer complete*/
|
||||
.long DMA3_DMA19_IRQHandler /* DMA channel 3,19 transfer complete*/
|
||||
.long DMA4_DMA20_IRQHandler /* DMA channel 4,20 transfer complete*/
|
||||
.long DMA5_DMA21_IRQHandler /* DMA channel 5,21 transfer complete*/
|
||||
.long DMA6_DMA22_IRQHandler /* DMA channel 6,22 transfer complete*/
|
||||
.long DMA7_DMA23_IRQHandler /* DMA channel 7,23 transfer complete*/
|
||||
.long DMA8_DMA24_IRQHandler /* DMA channel 8,24 transfer complete*/
|
||||
.long DMA9_DMA25_IRQHandler /* DMA channel 9,25 transfer complete*/
|
||||
.long DMA10_DMA26_IRQHandler /* DMA channel 10,26 transfer complete*/
|
||||
.long DMA11_DMA27_IRQHandler /* DMA channel 11,27 transfer complete*/
|
||||
.long DMA12_DMA28_IRQHandler /* DMA channel 12,28 transfer complete*/
|
||||
.long DMA13_DMA29_IRQHandler /* DMA channel 13,29 transfer complete*/
|
||||
.long DMA14_DMA30_IRQHandler /* DMA channel 14,30 transfer complete*/
|
||||
.long DMA15_DMA31_IRQHandler /* DMA channel 15,31 transfer complete*/
|
||||
.long DMA_Error_IRQHandler /* DMA channel 0 - 31 error*/
|
||||
.long MCM_IRQHandler /* MCM normal interrupt*/
|
||||
.long FTFA_IRQHandler /* FTFA command complete*/
|
||||
.long Read_Collision_IRQHandler /* FTFA read collision*/
|
||||
.long LVD_LVW_IRQHandler /* PMC controller low-voltage detect, low-voltage warning*/
|
||||
.long LLWU_IRQHandler /* Low leakage wakeup unit*/
|
||||
.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/
|
||||
.long TRNG0_IRQHandler /* True randon number generator*/
|
||||
.long I2C0_IRQHandler /* Inter-integrated circuit 0*/
|
||||
.long I2C1_IRQHandler /* Inter-integrated circuit 1*/
|
||||
.long SPI0_IRQHandler /* Serial peripheral Interface 0*/
|
||||
.long SPI1_IRQHandler /* Serial peripheral Interface 1*/
|
||||
.long I2S0_Tx_IRQHandler /* Integrated interchip sound 0 transmit interrupt*/
|
||||
.long I2S0_Rx_IRQHandler /* Integrated interchip sound 0 receive interrupt*/
|
||||
.long LPUART0_IRQHandler /* LPUART0 receive/transmit/error interrupt*/
|
||||
.long LPUART1_IRQHandler /* LPUART1 receive/transmit/error interrupt*/
|
||||
.long LPUART2_IRQHandler /* LPUART2 receive/transmit/error interrupt*/
|
||||
.long LPUART3_IRQHandler /* LPUART3 receive/transmit/error interrupt*/
|
||||
.long LPUART4_IRQHandler /* LPUART4 receive/transmit/error interrupt*/
|
||||
.long Reserved51_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved52_IRQHandler /* Reserved interrupt*/
|
||||
.long EMVSIM0_IRQHandler /* EMVSIM0 common interrupt*/
|
||||
.long EMVSIM1_IRQHandler /* EMVSIM1 common interrupt*/
|
||||
.long ADC0_IRQHandler /* Analog-to-digital converter 0*/
|
||||
.long CMP0_IRQHandler /* Comparator 0*/
|
||||
.long CMP1_IRQHandler /* Comparator 1*/
|
||||
.long FTM0_IRQHandler /* FlexTimer module 0 fault, overflow and channels interrupt*/
|
||||
.long FTM1_IRQHandler /* FlexTimer module 1 fault, overflow and channels interrupt*/
|
||||
.long FTM2_IRQHandler /* FlexTimer module 2 fault, overflow and channels interrupt*/
|
||||
.long CMT_IRQHandler /* Carrier modulator transmitter*/
|
||||
.long RTC_IRQHandler /* Real time clock*/
|
||||
.long RTC_Seconds_IRQHandler /* Real time clock seconds*/
|
||||
.long PIT0CH0_IRQHandler /* Periodic interrupt timer 0 channel 0*/
|
||||
.long PIT0CH1_IRQHandler /* Periodic interrupt timer 0 channel 1*/
|
||||
.long PIT0CH2_IRQHandler /* Periodic interrupt timer 0 channel 2*/
|
||||
.long PIT0CH3_IRQHandler /* Periodic interrupt timer 0 channel 3*/
|
||||
.long PDB0_IRQHandler /* Programmable delay block*/
|
||||
.long USB0_IRQHandler /* USB OTG interrupt*/
|
||||
.long USBDCD_IRQHandler /* USB charger detect*/
|
||||
.long Reserved71_IRQHandler /* Reserved interrupt*/
|
||||
.long DAC0_IRQHandler /* Digital-to-analog converter 0*/
|
||||
.long MCG_IRQHandler /* Multipurpose clock generator*/
|
||||
.long LPTMR0_LPTMR1_IRQHandler /* Single interrupt vector for Low Power Timer 0 and 1*/
|
||||
.long PORTA_IRQHandler /* Port A pin detect interrupt*/
|
||||
.long PORTB_IRQHandler /* Port B pin detect interrupt*/
|
||||
.long PORTC_IRQHandler /* Port C pin detect interrupt*/
|
||||
.long PORTD_IRQHandler /* Port D pin detect interrupt*/
|
||||
.long PORTE_IRQHandler /* Port E pin detect interrupt*/
|
||||
.long SWI_IRQHandler /* Software interrupt*/
|
||||
.long SPI2_IRQHandler /* Serial peripheral Interface 2*/
|
||||
.long Reserved82_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved83_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved84_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved85_IRQHandler /* Reserved interrupt*/
|
||||
.long FLEXIO0_IRQHandler /* FLEXIO0*/
|
||||
.long FTM3_IRQHandler /* FlexTimer module 3 fault, overflow and channels interrupt*/
|
||||
.long Reserved88_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved89_IRQHandler /* Reserved interrupt*/
|
||||
.long I2C2_IRQHandler /* Inter-integrated circuit 2*/
|
||||
.long Reserved91_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved92_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved93_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved94_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved95_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved96_IRQHandler /* Reserved interrupt*/
|
||||
.long SDHC_IRQHandler /* Secured digital host controller*/
|
||||
.long Reserved98_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved99_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved100_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved101_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved102_IRQHandler /* Reserved interrupt*/
|
||||
.long TSI0_IRQHandler /* Touch Sensing Input*/
|
||||
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
|
||||
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
|
||||
.long Reserved106_IRQHandler /* Reserved interrupt*/
|
||||
.long I2C3_IRQHandler /* Inter-integrated circuit 3*/
|
||||
.long Reserved108_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved109_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved110_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved111_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved112_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved113_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved114_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved115_IRQHandler /* Reserved interrupt*/
|
||||
.long QuadSPI0_IRQHandler /* qspi*/
|
||||
.long Reserved117_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved118_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved119_IRQHandler /* Reserved interrupt*/
|
||||
.long LTC0_IRQHandler /* LP Trusted Cryptography*/
|
||||
.long Reserved121_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved122_IRQHandler /* Reserved interrupt*/
|
||||
.long DefaultISR /* 123*/
|
||||
.long DefaultISR /* 124*/
|
||||
.long DefaultISR /* 125*/
|
||||
.long DefaultISR /* 126*/
|
||||
.long DefaultISR /* 127*/
|
||||
.long DefaultISR /* 128*/
|
||||
.long DefaultISR /* 129*/
|
||||
.long DefaultISR /* 130*/
|
||||
.long DefaultISR /* 131*/
|
||||
.long DefaultISR /* 132*/
|
||||
.long DefaultISR /* 133*/
|
||||
.long DefaultISR /* 134*/
|
||||
.long DefaultISR /* 135*/
|
||||
.long DefaultISR /* 136*/
|
||||
.long DefaultISR /* 137*/
|
||||
.long DefaultISR /* 138*/
|
||||
.long DefaultISR /* 139*/
|
||||
.long DefaultISR /* 140*/
|
||||
.long DefaultISR /* 141*/
|
||||
.long DefaultISR /* 142*/
|
||||
.long DefaultISR /* 143*/
|
||||
.long DefaultISR /* 144*/
|
||||
.long DefaultISR /* 145*/
|
||||
.long DefaultISR /* 146*/
|
||||
.long DefaultISR /* 147*/
|
||||
.long DefaultISR /* 148*/
|
||||
.long DefaultISR /* 149*/
|
||||
.long DefaultISR /* 150*/
|
||||
.long DefaultISR /* 151*/
|
||||
.long DefaultISR /* 152*/
|
||||
.long DefaultISR /* 153*/
|
||||
.long DefaultISR /* 154*/
|
||||
.long DefaultISR /* 155*/
|
||||
.long DefaultISR /* 156*/
|
||||
.long DefaultISR /* 157*/
|
||||
.long DefaultISR /* 158*/
|
||||
.long DefaultISR /* 159*/
|
||||
.long DefaultISR /* 160*/
|
||||
.long DefaultISR /* 161*/
|
||||
.long DefaultISR /* 162*/
|
||||
.long DefaultISR /* 163*/
|
||||
.long DefaultISR /* 164*/
|
||||
.long DefaultISR /* 165*/
|
||||
.long DefaultISR /* 166*/
|
||||
.long DefaultISR /* 167*/
|
||||
.long DefaultISR /* 168*/
|
||||
.long DefaultISR /* 169*/
|
||||
.long DefaultISR /* 170*/
|
||||
.long DefaultISR /* 171*/
|
||||
.long DefaultISR /* 172*/
|
||||
.long DefaultISR /* 173*/
|
||||
.long DefaultISR /* 174*/
|
||||
.long DefaultISR /* 175*/
|
||||
.long DefaultISR /* 176*/
|
||||
.long DefaultISR /* 177*/
|
||||
.long DefaultISR /* 178*/
|
||||
.long DefaultISR /* 179*/
|
||||
.long DefaultISR /* 180*/
|
||||
.long DefaultISR /* 181*/
|
||||
.long DefaultISR /* 182*/
|
||||
.long DefaultISR /* 183*/
|
||||
.long DefaultISR /* 184*/
|
||||
.long DefaultISR /* 185*/
|
||||
.long DefaultISR /* 186*/
|
||||
.long DefaultISR /* 187*/
|
||||
.long DefaultISR /* 188*/
|
||||
.long DefaultISR /* 189*/
|
||||
.long DefaultISR /* 190*/
|
||||
.long DefaultISR /* 191*/
|
||||
.long DefaultISR /* 192*/
|
||||
.long DefaultISR /* 193*/
|
||||
.long DefaultISR /* 194*/
|
||||
.long DefaultISR /* 195*/
|
||||
.long DefaultISR /* 196*/
|
||||
.long DefaultISR /* 197*/
|
||||
.long DefaultISR /* 198*/
|
||||
.long DefaultISR /* 199*/
|
||||
.long DefaultISR /* 200*/
|
||||
.long DefaultISR /* 201*/
|
||||
.long DefaultISR /* 202*/
|
||||
.long DefaultISR /* 203*/
|
||||
.long DefaultISR /* 204*/
|
||||
.long DefaultISR /* 205*/
|
||||
.long DefaultISR /* 206*/
|
||||
.long DefaultISR /* 207*/
|
||||
.long DefaultISR /* 208*/
|
||||
.long DefaultISR /* 209*/
|
||||
.long DefaultISR /* 210*/
|
||||
.long DefaultISR /* 211*/
|
||||
.long DefaultISR /* 212*/
|
||||
.long DefaultISR /* 213*/
|
||||
.long DefaultISR /* 214*/
|
||||
.long DefaultISR /* 215*/
|
||||
.long DefaultISR /* 216*/
|
||||
.long DefaultISR /* 217*/
|
||||
.long DefaultISR /* 218*/
|
||||
.long DefaultISR /* 219*/
|
||||
.long DefaultISR /* 220*/
|
||||
.long DefaultISR /* 221*/
|
||||
.long DefaultISR /* 222*/
|
||||
.long DefaultISR /* 223*/
|
||||
.long DefaultISR /* 224*/
|
||||
.long DefaultISR /* 225*/
|
||||
.long DefaultISR /* 226*/
|
||||
.long DefaultISR /* 227*/
|
||||
.long DefaultISR /* 228*/
|
||||
.long DefaultISR /* 229*/
|
||||
.long DefaultISR /* 230*/
|
||||
.long DefaultISR /* 231*/
|
||||
.long DefaultISR /* 232*/
|
||||
.long DefaultISR /* 233*/
|
||||
.long DefaultISR /* 234*/
|
||||
.long DefaultISR /* 235*/
|
||||
.long DefaultISR /* 236*/
|
||||
.long DefaultISR /* 237*/
|
||||
.long DefaultISR /* 238*/
|
||||
.long DefaultISR /* 239*/
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Flash Configuration */
|
||||
.section .FlashConfig, "a"
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFF3DFE
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
.equ VTOR, 0xE000ED08
|
||||
ldr r0, =VTOR
|
||||
ldr r1, =__isr_vector
|
||||
str r1, [r0]
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
ldr r0,=SystemInit
|
||||
blx r0
|
||||
#endif
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
#if 1
|
||||
/* Here are two copies of loop implemenations. First one favors code size
|
||||
* and the second one favors performance. Default uses the first one.
|
||||
* Change to "#if 0" to use the second one */
|
||||
.LC0:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .LC0
|
||||
#else
|
||||
subs r3, r2
|
||||
ble .LC1
|
||||
.LC0:
|
||||
subs r3, #4
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
bgt .LC0
|
||||
.LC1:
|
||||
#endif
|
||||
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* Loop to zero out BSS section, which uses following symbols
|
||||
* in linker script:
|
||||
* __bss_start__: start of BSS section. Must align to 4
|
||||
* __bss_end__: end of BSS section. Must align to 4
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.LC2:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .LC2
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
cpsie i /* Unmask interrupts */
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
#ifndef __ATOLLIC__
|
||||
ldr r0,=__START
|
||||
blx r0
|
||||
#else
|
||||
ldr r0,=__libc_init_array
|
||||
blx r0
|
||||
ldr r0,=main
|
||||
bx r0
|
||||
#endif
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
b DefaultISR
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
ldr r0,=NMI_Handler
|
||||
bx r0
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
ldr r0,=HardFault_Handler
|
||||
bx r0
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
ldr r0,=SVC_Handler
|
||||
bx r0
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
ldr r0,=PendSV_Handler
|
||||
bx r0
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
ldr r0,=SysTick_Handler
|
||||
bx r0
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA0_DMA16_IRQHandler
|
||||
.type DMA0_DMA16_IRQHandler, %function
|
||||
DMA0_DMA16_IRQHandler:
|
||||
ldr r0,=DMA0_DMA16_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA1_DMA17_IRQHandler
|
||||
.type DMA1_DMA17_IRQHandler, %function
|
||||
DMA1_DMA17_IRQHandler:
|
||||
ldr r0,=DMA1_DMA17_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA2_DMA18_IRQHandler
|
||||
.type DMA2_DMA18_IRQHandler, %function
|
||||
DMA2_DMA18_IRQHandler:
|
||||
ldr r0,=DMA2_DMA18_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA3_DMA19_IRQHandler
|
||||
.type DMA3_DMA19_IRQHandler, %function
|
||||
DMA3_DMA19_IRQHandler:
|
||||
ldr r0,=DMA3_DMA19_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA4_DMA20_IRQHandler
|
||||
.type DMA4_DMA20_IRQHandler, %function
|
||||
DMA4_DMA20_IRQHandler:
|
||||
ldr r0,=DMA4_DMA20_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA5_DMA21_IRQHandler
|
||||
.type DMA5_DMA21_IRQHandler, %function
|
||||
DMA5_DMA21_IRQHandler:
|
||||
ldr r0,=DMA5_DMA21_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA6_DMA22_IRQHandler
|
||||
.type DMA6_DMA22_IRQHandler, %function
|
||||
DMA6_DMA22_IRQHandler:
|
||||
ldr r0,=DMA6_DMA22_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA7_DMA23_IRQHandler
|
||||
.type DMA7_DMA23_IRQHandler, %function
|
||||
DMA7_DMA23_IRQHandler:
|
||||
ldr r0,=DMA7_DMA23_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA8_DMA24_IRQHandler
|
||||
.type DMA8_DMA24_IRQHandler, %function
|
||||
DMA8_DMA24_IRQHandler:
|
||||
ldr r0,=DMA8_DMA24_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA9_DMA25_IRQHandler
|
||||
.type DMA9_DMA25_IRQHandler, %function
|
||||
DMA9_DMA25_IRQHandler:
|
||||
ldr r0,=DMA9_DMA25_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA10_DMA26_IRQHandler
|
||||
.type DMA10_DMA26_IRQHandler, %function
|
||||
DMA10_DMA26_IRQHandler:
|
||||
ldr r0,=DMA10_DMA26_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA11_DMA27_IRQHandler
|
||||
.type DMA11_DMA27_IRQHandler, %function
|
||||
DMA11_DMA27_IRQHandler:
|
||||
ldr r0,=DMA11_DMA27_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA12_DMA28_IRQHandler
|
||||
.type DMA12_DMA28_IRQHandler, %function
|
||||
DMA12_DMA28_IRQHandler:
|
||||
ldr r0,=DMA12_DMA28_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA13_DMA29_IRQHandler
|
||||
.type DMA13_DMA29_IRQHandler, %function
|
||||
DMA13_DMA29_IRQHandler:
|
||||
ldr r0,=DMA13_DMA29_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA14_DMA30_IRQHandler
|
||||
.type DMA14_DMA30_IRQHandler, %function
|
||||
DMA14_DMA30_IRQHandler:
|
||||
ldr r0,=DMA14_DMA30_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA15_DMA31_IRQHandler
|
||||
.type DMA15_DMA31_IRQHandler, %function
|
||||
DMA15_DMA31_IRQHandler:
|
||||
ldr r0,=DMA15_DMA31_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA_Error_IRQHandler
|
||||
.type DMA_Error_IRQHandler, %function
|
||||
DMA_Error_IRQHandler:
|
||||
ldr r0,=DMA_Error_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak I2C0_IRQHandler
|
||||
.type I2C0_IRQHandler, %function
|
||||
I2C0_IRQHandler:
|
||||
ldr r0,=I2C0_DriverIRQHandler
|
||||
bx r0
|
||||
.size I2C0_IRQHandler, . - I2C0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak I2C1_IRQHandler
|
||||
.type I2C1_IRQHandler, %function
|
||||
I2C1_IRQHandler:
|
||||
ldr r0,=I2C1_DriverIRQHandler
|
||||
bx r0
|
||||
.size I2C1_IRQHandler, . - I2C1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SPI0_IRQHandler
|
||||
.type SPI0_IRQHandler, %function
|
||||
SPI0_IRQHandler:
|
||||
ldr r0,=SPI0_DriverIRQHandler
|
||||
bx r0
|
||||
.size SPI0_IRQHandler, . - SPI0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SPI1_IRQHandler
|
||||
.type SPI1_IRQHandler, %function
|
||||
SPI1_IRQHandler:
|
||||
ldr r0,=SPI1_DriverIRQHandler
|
||||
bx r0
|
||||
.size SPI1_IRQHandler, . - SPI1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak I2S0_Tx_IRQHandler
|
||||
.type I2S0_Tx_IRQHandler, %function
|
||||
I2S0_Tx_IRQHandler:
|
||||
ldr r0,=I2S0_Tx_DriverIRQHandler
|
||||
bx r0
|
||||
.size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak I2S0_Rx_IRQHandler
|
||||
.type I2S0_Rx_IRQHandler, %function
|
||||
I2S0_Rx_IRQHandler:
|
||||
ldr r0,=I2S0_Rx_DriverIRQHandler
|
||||
bx r0
|
||||
.size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak LPUART0_IRQHandler
|
||||
.type LPUART0_IRQHandler, %function
|
||||
LPUART0_IRQHandler:
|
||||
ldr r0,=LPUART0_DriverIRQHandler
|
||||
bx r0
|
||||
.size LPUART0_IRQHandler, . - LPUART0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak LPUART1_IRQHandler
|
||||
.type LPUART1_IRQHandler, %function
|
||||
LPUART1_IRQHandler:
|
||||
ldr r0,=LPUART1_DriverIRQHandler
|
||||
bx r0
|
||||
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak LPUART2_IRQHandler
|
||||
.type LPUART2_IRQHandler, %function
|
||||
LPUART2_IRQHandler:
|
||||
ldr r0,=LPUART2_DriverIRQHandler
|
||||
bx r0
|
||||
.size LPUART2_IRQHandler, . - LPUART2_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak LPUART3_IRQHandler
|
||||
.type LPUART3_IRQHandler, %function
|
||||
LPUART3_IRQHandler:
|
||||
ldr r0,=LPUART3_DriverIRQHandler
|
||||
bx r0
|
||||
.size LPUART3_IRQHandler, . - LPUART3_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak LPUART4_IRQHandler
|
||||
.type LPUART4_IRQHandler, %function
|
||||
LPUART4_IRQHandler:
|
||||
ldr r0,=LPUART4_DriverIRQHandler
|
||||
bx r0
|
||||
.size LPUART4_IRQHandler, . - LPUART4_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SPI2_IRQHandler
|
||||
.type SPI2_IRQHandler, %function
|
||||
SPI2_IRQHandler:
|
||||
ldr r0,=SPI2_DriverIRQHandler
|
||||
bx r0
|
||||
.size SPI2_IRQHandler, . - SPI2_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXIO0_IRQHandler
|
||||
.type FLEXIO0_IRQHandler, %function
|
||||
FLEXIO0_IRQHandler:
|
||||
ldr r0,=FLEXIO0_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXIO0_IRQHandler, . - FLEXIO0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak I2C2_IRQHandler
|
||||
.type I2C2_IRQHandler, %function
|
||||
I2C2_IRQHandler:
|
||||
ldr r0,=I2C2_DriverIRQHandler
|
||||
bx r0
|
||||
.size I2C2_IRQHandler, . - I2C2_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SDHC_IRQHandler
|
||||
.type SDHC_IRQHandler, %function
|
||||
SDHC_IRQHandler:
|
||||
ldr r0,=SDHC_DriverIRQHandler
|
||||
bx r0
|
||||
.size SDHC_IRQHandler, . - SDHC_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak I2C3_IRQHandler
|
||||
.type I2C3_IRQHandler, %function
|
||||
I2C3_IRQHandler:
|
||||
ldr r0,=I2C3_DriverIRQHandler
|
||||
bx r0
|
||||
.size I2C3_IRQHandler, . - I2C3_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak QuadSPI0_IRQHandler
|
||||
.type QuadSPI0_IRQHandler, %function
|
||||
QuadSPI0_IRQHandler:
|
||||
ldr r0,=QuadSPI0_DriverIRQHandler
|
||||
bx r0
|
||||
.size QuadSPI0_IRQHandler, . - QuadSPI0_IRQHandler
|
||||
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
|
||||
/* Exception Handlers */
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler DMA0_DMA16_DriverIRQHandler
|
||||
def_irq_handler DMA1_DMA17_DriverIRQHandler
|
||||
def_irq_handler DMA2_DMA18_DriverIRQHandler
|
||||
def_irq_handler DMA3_DMA19_DriverIRQHandler
|
||||
def_irq_handler DMA4_DMA20_DriverIRQHandler
|
||||
def_irq_handler DMA5_DMA21_DriverIRQHandler
|
||||
def_irq_handler DMA6_DMA22_DriverIRQHandler
|
||||
def_irq_handler DMA7_DMA23_DriverIRQHandler
|
||||
def_irq_handler DMA8_DMA24_DriverIRQHandler
|
||||
def_irq_handler DMA9_DMA25_DriverIRQHandler
|
||||
def_irq_handler DMA10_DMA26_DriverIRQHandler
|
||||
def_irq_handler DMA11_DMA27_DriverIRQHandler
|
||||
def_irq_handler DMA12_DMA28_DriverIRQHandler
|
||||
def_irq_handler DMA13_DMA29_DriverIRQHandler
|
||||
def_irq_handler DMA14_DMA30_DriverIRQHandler
|
||||
def_irq_handler DMA15_DMA31_DriverIRQHandler
|
||||
def_irq_handler DMA_Error_DriverIRQHandler
|
||||
def_irq_handler MCM_IRQHandler
|
||||
def_irq_handler FTFA_IRQHandler
|
||||
def_irq_handler Read_Collision_IRQHandler
|
||||
def_irq_handler LVD_LVW_IRQHandler
|
||||
def_irq_handler LLWU_IRQHandler
|
||||
def_irq_handler WDOG_EWM_IRQHandler
|
||||
def_irq_handler TRNG0_IRQHandler
|
||||
def_irq_handler I2C0_DriverIRQHandler
|
||||
def_irq_handler I2C1_DriverIRQHandler
|
||||
def_irq_handler SPI0_DriverIRQHandler
|
||||
def_irq_handler SPI1_DriverIRQHandler
|
||||
def_irq_handler I2S0_Tx_DriverIRQHandler
|
||||
def_irq_handler I2S0_Rx_DriverIRQHandler
|
||||
def_irq_handler LPUART0_DriverIRQHandler
|
||||
def_irq_handler LPUART1_DriverIRQHandler
|
||||
def_irq_handler LPUART2_DriverIRQHandler
|
||||
def_irq_handler LPUART3_DriverIRQHandler
|
||||
def_irq_handler LPUART4_DriverIRQHandler
|
||||
def_irq_handler Reserved51_IRQHandler
|
||||
def_irq_handler Reserved52_IRQHandler
|
||||
def_irq_handler EMVSIM0_IRQHandler
|
||||
def_irq_handler EMVSIM1_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler CMP0_IRQHandler
|
||||
def_irq_handler CMP1_IRQHandler
|
||||
def_irq_handler FTM0_IRQHandler
|
||||
def_irq_handler FTM1_IRQHandler
|
||||
def_irq_handler FTM2_IRQHandler
|
||||
def_irq_handler CMT_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler RTC_Seconds_IRQHandler
|
||||
def_irq_handler PIT0CH0_IRQHandler
|
||||
def_irq_handler PIT0CH1_IRQHandler
|
||||
def_irq_handler PIT0CH2_IRQHandler
|
||||
def_irq_handler PIT0CH3_IRQHandler
|
||||
def_irq_handler PDB0_IRQHandler
|
||||
def_irq_handler USB0_IRQHandler
|
||||
def_irq_handler USBDCD_IRQHandler
|
||||
def_irq_handler Reserved71_IRQHandler
|
||||
def_irq_handler DAC0_IRQHandler
|
||||
def_irq_handler MCG_IRQHandler
|
||||
def_irq_handler LPTMR0_LPTMR1_IRQHandler
|
||||
def_irq_handler PORTA_IRQHandler
|
||||
def_irq_handler PORTB_IRQHandler
|
||||
def_irq_handler PORTC_IRQHandler
|
||||
def_irq_handler PORTD_IRQHandler
|
||||
def_irq_handler PORTE_IRQHandler
|
||||
def_irq_handler SWI_IRQHandler
|
||||
def_irq_handler SPI2_DriverIRQHandler
|
||||
def_irq_handler Reserved82_IRQHandler
|
||||
def_irq_handler Reserved83_IRQHandler
|
||||
def_irq_handler Reserved84_IRQHandler
|
||||
def_irq_handler Reserved85_IRQHandler
|
||||
def_irq_handler FLEXIO0_DriverIRQHandler
|
||||
def_irq_handler FTM3_IRQHandler
|
||||
def_irq_handler Reserved88_IRQHandler
|
||||
def_irq_handler Reserved89_IRQHandler
|
||||
def_irq_handler I2C2_DriverIRQHandler
|
||||
def_irq_handler Reserved91_IRQHandler
|
||||
def_irq_handler Reserved92_IRQHandler
|
||||
def_irq_handler Reserved93_IRQHandler
|
||||
def_irq_handler Reserved94_IRQHandler
|
||||
def_irq_handler Reserved95_IRQHandler
|
||||
def_irq_handler Reserved96_IRQHandler
|
||||
def_irq_handler SDHC_DriverIRQHandler
|
||||
def_irq_handler Reserved98_IRQHandler
|
||||
def_irq_handler Reserved99_IRQHandler
|
||||
def_irq_handler Reserved100_IRQHandler
|
||||
def_irq_handler Reserved101_IRQHandler
|
||||
def_irq_handler Reserved102_IRQHandler
|
||||
def_irq_handler TSI0_IRQHandler
|
||||
def_irq_handler TPM1_IRQHandler
|
||||
def_irq_handler TPM2_IRQHandler
|
||||
def_irq_handler Reserved106_IRQHandler
|
||||
def_irq_handler I2C3_DriverIRQHandler
|
||||
def_irq_handler Reserved108_IRQHandler
|
||||
def_irq_handler Reserved109_IRQHandler
|
||||
def_irq_handler Reserved110_IRQHandler
|
||||
def_irq_handler Reserved111_IRQHandler
|
||||
def_irq_handler Reserved112_IRQHandler
|
||||
def_irq_handler Reserved113_IRQHandler
|
||||
def_irq_handler Reserved114_IRQHandler
|
||||
def_irq_handler Reserved115_IRQHandler
|
||||
def_irq_handler QuadSPI0_DriverIRQHandler
|
||||
def_irq_handler Reserved117_IRQHandler
|
||||
def_irq_handler Reserved118_IRQHandler
|
||||
def_irq_handler Reserved119_IRQHandler
|
||||
def_irq_handler LTC0_IRQHandler
|
||||
def_irq_handler Reserved121_IRQHandler
|
||||
def_irq_handler Reserved122_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,126 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK82FN256CAx15
|
||||
** MK82FN256VDC15
|
||||
** MK82FN256VLL15
|
||||
** MK82FN256VLQ15
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
|
||||
** Version: rev. 1.2, 2015-07-29
|
||||
** Build: b160406
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright (c) 2016 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol __ram_vector_table__ = 1;
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
define symbol __stack_size__=MBED_BOOT_STACK_SIZE;
|
||||
define symbol __heap_size__=0x10000;
|
||||
|
||||
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003C0 : 0;
|
||||
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003BF : 0;
|
||||
|
||||
define symbol m_interrupts_start = 0x00000000;
|
||||
define symbol m_interrupts_end = 0x000003BF;
|
||||
|
||||
define symbol m_bootloader_config_start = 0x000003C0;
|
||||
define symbol m_bootloader_config_end = 0x000003FF;
|
||||
|
||||
define symbol m_flash_config_start = 0x00000400;
|
||||
define symbol m_flash_config_end = 0x0000040F;
|
||||
|
||||
define symbol m_text_start = 0x00000410;
|
||||
define symbol m_text_end = 0x0003FFFF;
|
||||
|
||||
define symbol m_interrupts_ram_start = 0x1FFF0000;
|
||||
define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__;
|
||||
|
||||
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
|
||||
define symbol m_data_end = 0x1FFFFFFF;
|
||||
|
||||
define symbol m_data_2_start = 0x20000000;
|
||||
define symbol m_data_2_end = 0x2002FFFF;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
|
||||
define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end]
|
||||
| mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
|
||||
define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
|
||||
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
place in m_bootloader_config_region { section BootloaderConfig };
|
||||
place in m_flash_config_region { section FlashConfig };
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
place in m_interrupts_ram_region { section m_interrupts_ram };
|
||||
|
||||
@@ -0,0 +1,816 @@
|
||||
; ---------------------------------------------------------------------------------------
|
||||
; @file: startup_MK82F25615.s
|
||||
; @purpose: CMSIS Cortex-M4 Core Device Startup File
|
||||
; MK82F25615
|
||||
; @version: 1.0
|
||||
; @date: 2015-4-9
|
||||
; @build: b151210
|
||||
; ---------------------------------------------------------------------------------------
|
||||
;
|
||||
; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
; are permitted provided that the following conditions are met:
|
||||
;
|
||||
; o Redistributions of source code must retain the above copyright notice, this list
|
||||
; of conditions and the following disclaimer.
|
||||
;
|
||||
; o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
; list of conditions and the following disclaimer in the documentation and/or
|
||||
; other materials provided with the distribution.
|
||||
;
|
||||
; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
; contributors may be used to endorse or promote products derived from this
|
||||
; software without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler ;NMI Handler
|
||||
DCD HardFault_Handler ;Hard Fault Handler
|
||||
DCD MemManage_Handler ;MPU Fault Handler
|
||||
DCD BusFault_Handler ;Bus Fault Handler
|
||||
DCD UsageFault_Handler ;Usage Fault Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD SVC_Handler ;SVCall Handler
|
||||
DCD DebugMon_Handler ;Debug Monitor Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD PendSV_Handler ;PendSV Handler
|
||||
DCD SysTick_Handler ;SysTick Handler
|
||||
|
||||
;External Interrupts
|
||||
DCD DMA0_DMA16_IRQHandler ;DMA channel 0,16 transfer complete
|
||||
DCD DMA1_DMA17_IRQHandler ;DMA channel 1,17 transfer complete
|
||||
DCD DMA2_DMA18_IRQHandler ;DMA channel 2,18 transfer complete
|
||||
DCD DMA3_DMA19_IRQHandler ;DMA channel 3,19 transfer complete
|
||||
DCD DMA4_DMA20_IRQHandler ;DMA channel 4,20 transfer complete
|
||||
DCD DMA5_DMA21_IRQHandler ;DMA channel 5,21 transfer complete
|
||||
DCD DMA6_DMA22_IRQHandler ;DMA channel 6,22 transfer complete
|
||||
DCD DMA7_DMA23_IRQHandler ;DMA channel 7,23 transfer complete
|
||||
DCD DMA8_DMA24_IRQHandler ;DMA channel 8,24 transfer complete
|
||||
DCD DMA9_DMA25_IRQHandler ;DMA channel 9,25 transfer complete
|
||||
DCD DMA10_DMA26_IRQHandler ;DMA channel 10,26 transfer complete
|
||||
DCD DMA11_DMA27_IRQHandler ;DMA channel 11,27 transfer complete
|
||||
DCD DMA12_DMA28_IRQHandler ;DMA channel 12,28 transfer complete
|
||||
DCD DMA13_DMA29_IRQHandler ;DMA channel 13,29 transfer complete
|
||||
DCD DMA14_DMA30_IRQHandler ;DMA channel 14,30 transfer complete
|
||||
DCD DMA15_DMA31_IRQHandler ;DMA channel 15,31 transfer complete
|
||||
DCD DMA_Error_IRQHandler ;DMA channel 0 - 31 error
|
||||
DCD MCM_IRQHandler ;MCM normal interrupt
|
||||
DCD FTFA_IRQHandler ;FTFA command complete
|
||||
DCD Read_Collision_IRQHandler ;FTFA read collision
|
||||
DCD LVD_LVW_IRQHandler ;PMC controller low-voltage detect, low-voltage warning
|
||||
DCD LLWU_IRQHandler ;Low leakage wakeup unit
|
||||
DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM
|
||||
DCD TRNG0_IRQHandler ;True randon number generator
|
||||
DCD I2C0_IRQHandler ;Inter-integrated circuit 0
|
||||
DCD I2C1_IRQHandler ;Inter-integrated circuit 1
|
||||
DCD SPI0_IRQHandler ;Serial peripheral Interface 0
|
||||
DCD SPI1_IRQHandler ;Serial peripheral Interface 1
|
||||
DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt
|
||||
DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt
|
||||
DCD LPUART0_IRQHandler ;LPUART0 receive/transmit/error interrupt
|
||||
DCD LPUART1_IRQHandler ;LPUART1 receive/transmit/error interrupt
|
||||
DCD LPUART2_IRQHandler ;LPUART2 receive/transmit/error interrupt
|
||||
DCD LPUART3_IRQHandler ;LPUART3 receive/transmit/error interrupt
|
||||
DCD LPUART4_IRQHandler ;LPUART4 receive/transmit/error interrupt
|
||||
DCD Reserved51_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved52_IRQHandler ;Reserved interrupt
|
||||
DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt
|
||||
DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt
|
||||
DCD ADC0_IRQHandler ;Analog-to-digital converter 0
|
||||
DCD CMP0_IRQHandler ;Comparator 0
|
||||
DCD CMP1_IRQHandler ;Comparator 1
|
||||
DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt
|
||||
DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt
|
||||
DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt
|
||||
DCD CMT_IRQHandler ;Carrier modulator transmitter
|
||||
DCD RTC_IRQHandler ;Real time clock
|
||||
DCD RTC_Seconds_IRQHandler ;Real time clock seconds
|
||||
DCD PIT0CH0_IRQHandler ;Periodic interrupt timer 0 channel 0
|
||||
DCD PIT0CH1_IRQHandler ;Periodic interrupt timer 0 channel 1
|
||||
DCD PIT0CH2_IRQHandler ;Periodic interrupt timer 0 channel 2
|
||||
DCD PIT0CH3_IRQHandler ;Periodic interrupt timer 0 channel 3
|
||||
DCD PDB0_IRQHandler ;Programmable delay block
|
||||
DCD USB0_IRQHandler ;USB OTG interrupt
|
||||
DCD USBDCD_IRQHandler ;USB charger detect
|
||||
DCD Reserved71_IRQHandler ;Reserved interrupt
|
||||
DCD DAC0_IRQHandler ;Digital-to-analog converter 0
|
||||
DCD MCG_IRQHandler ;Multipurpose clock generator
|
||||
DCD LPTMR0_LPTMR1_IRQHandler ;Single interrupt vector for Low Power Timer 0 and 1
|
||||
DCD PORTA_IRQHandler ;Port A pin detect interrupt
|
||||
DCD PORTB_IRQHandler ;Port B pin detect interrupt
|
||||
DCD PORTC_IRQHandler ;Port C pin detect interrupt
|
||||
DCD PORTD_IRQHandler ;Port D pin detect interrupt
|
||||
DCD PORTE_IRQHandler ;Port E pin detect interrupt
|
||||
DCD SWI_IRQHandler ;Software interrupt
|
||||
DCD SPI2_IRQHandler ;Serial peripheral Interface 2
|
||||
DCD Reserved82_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved83_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved84_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved85_IRQHandler ;Reserved interrupt
|
||||
DCD FLEXIO0_IRQHandler ;FLEXIO0
|
||||
DCD FTM3_IRQHandler ;FlexTimer module 3 fault, overflow and channels interrupt
|
||||
DCD Reserved88_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved89_IRQHandler ;Reserved interrupt
|
||||
DCD I2C2_IRQHandler ;Inter-integrated circuit 2
|
||||
DCD Reserved91_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved92_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved93_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved94_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved95_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved96_IRQHandler ;Reserved interrupt
|
||||
DCD SDHC_IRQHandler ;Secured digital host controller
|
||||
DCD Reserved98_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved99_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved100_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved101_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved102_IRQHandler ;Reserved interrupt
|
||||
DCD TSI0_IRQHandler ;Touch Sensing Input
|
||||
DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
|
||||
DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
|
||||
DCD Reserved106_IRQHandler ;Reserved interrupt
|
||||
DCD I2C3_IRQHandler ;Inter-integrated circuit 3
|
||||
DCD Reserved108_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved109_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved110_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved111_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved112_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved113_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved114_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved115_IRQHandler ;Reserved interrupt
|
||||
DCD QuadSPI0_IRQHandler ;qspi
|
||||
DCD Reserved117_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved118_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved119_IRQHandler ;Reserved interrupt
|
||||
DCD LTC0_IRQHandler ;LP Trusted Cryptography
|
||||
DCD Reserved121_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved122_IRQHandler ;Reserved interrupt
|
||||
DCD DefaultISR ;123
|
||||
DCD DefaultISR ;124
|
||||
DCD DefaultISR ;125
|
||||
DCD DefaultISR ;126
|
||||
DCD DefaultISR ;127
|
||||
DCD DefaultISR ;128
|
||||
DCD DefaultISR ;129
|
||||
DCD DefaultISR ;130
|
||||
DCD DefaultISR ;131
|
||||
DCD DefaultISR ;132
|
||||
DCD DefaultISR ;133
|
||||
DCD DefaultISR ;134
|
||||
DCD DefaultISR ;135
|
||||
DCD DefaultISR ;136
|
||||
DCD DefaultISR ;137
|
||||
DCD DefaultISR ;138
|
||||
DCD DefaultISR ;139
|
||||
DCD DefaultISR ;140
|
||||
DCD DefaultISR ;141
|
||||
DCD DefaultISR ;142
|
||||
DCD DefaultISR ;143
|
||||
DCD DefaultISR ;144
|
||||
DCD DefaultISR ;145
|
||||
DCD DefaultISR ;146
|
||||
DCD DefaultISR ;147
|
||||
DCD DefaultISR ;148
|
||||
DCD DefaultISR ;149
|
||||
DCD DefaultISR ;150
|
||||
DCD DefaultISR ;151
|
||||
DCD DefaultISR ;152
|
||||
DCD DefaultISR ;153
|
||||
DCD DefaultISR ;154
|
||||
DCD DefaultISR ;155
|
||||
DCD DefaultISR ;156
|
||||
DCD DefaultISR ;157
|
||||
DCD DefaultISR ;158
|
||||
DCD DefaultISR ;159
|
||||
DCD DefaultISR ;160
|
||||
DCD DefaultISR ;161
|
||||
DCD DefaultISR ;162
|
||||
DCD DefaultISR ;163
|
||||
DCD DefaultISR ;164
|
||||
DCD DefaultISR ;165
|
||||
DCD DefaultISR ;166
|
||||
DCD DefaultISR ;167
|
||||
DCD DefaultISR ;168
|
||||
DCD DefaultISR ;169
|
||||
DCD DefaultISR ;170
|
||||
DCD DefaultISR ;171
|
||||
DCD DefaultISR ;172
|
||||
DCD DefaultISR ;173
|
||||
DCD DefaultISR ;174
|
||||
DCD DefaultISR ;175
|
||||
DCD DefaultISR ;176
|
||||
DCD DefaultISR ;177
|
||||
DCD DefaultISR ;178
|
||||
DCD DefaultISR ;179
|
||||
DCD DefaultISR ;180
|
||||
DCD DefaultISR ;181
|
||||
DCD DefaultISR ;182
|
||||
DCD DefaultISR ;183
|
||||
DCD DefaultISR ;184
|
||||
DCD DefaultISR ;185
|
||||
DCD DefaultISR ;186
|
||||
DCD DefaultISR ;187
|
||||
DCD DefaultISR ;188
|
||||
DCD DefaultISR ;189
|
||||
DCD DefaultISR ;190
|
||||
DCD DefaultISR ;191
|
||||
DCD DefaultISR ;192
|
||||
DCD DefaultISR ;193
|
||||
DCD DefaultISR ;194
|
||||
DCD DefaultISR ;195
|
||||
DCD DefaultISR ;196
|
||||
DCD DefaultISR ;197
|
||||
DCD DefaultISR ;198
|
||||
DCD DefaultISR ;199
|
||||
DCD DefaultISR ;200
|
||||
DCD DefaultISR ;201
|
||||
DCD DefaultISR ;202
|
||||
DCD DefaultISR ;203
|
||||
DCD DefaultISR ;204
|
||||
DCD DefaultISR ;205
|
||||
DCD DefaultISR ;206
|
||||
DCD DefaultISR ;207
|
||||
DCD DefaultISR ;208
|
||||
DCD DefaultISR ;209
|
||||
DCD DefaultISR ;210
|
||||
DCD DefaultISR ;211
|
||||
DCD DefaultISR ;212
|
||||
DCD DefaultISR ;213
|
||||
DCD DefaultISR ;214
|
||||
DCD DefaultISR ;215
|
||||
DCD DefaultISR ;216
|
||||
DCD DefaultISR ;217
|
||||
DCD DefaultISR ;218
|
||||
DCD DefaultISR ;219
|
||||
DCD DefaultISR ;220
|
||||
DCD DefaultISR ;221
|
||||
DCD DefaultISR ;222
|
||||
DCD DefaultISR ;223
|
||||
DCD DefaultISR ;224
|
||||
DCD DefaultISR ;225
|
||||
DCD DefaultISR ;226
|
||||
DCD DefaultISR ;227
|
||||
DCD DefaultISR ;228
|
||||
DCD DefaultISR ;229
|
||||
DCD DefaultISR ;230
|
||||
DCD DefaultISR ;231
|
||||
DCD DefaultISR ;232
|
||||
DCD DefaultISR ;233
|
||||
DCD DefaultISR ;234
|
||||
DCD DefaultISR ;235
|
||||
DCD DefaultISR ;236
|
||||
DCD DefaultISR ;237
|
||||
DCD DefaultISR ;238
|
||||
DCD DefaultISR ;239
|
||||
__Vectors_End
|
||||
|
||||
SECTION FlashConfig:CODE
|
||||
__FlashConfig
|
||||
DCD 0xFFFFFFFF
|
||||
DCD 0xFFFFFFFF
|
||||
DCD 0xFFFFFFFF
|
||||
DCD 0xFFFF3DFE
|
||||
__FlashConfig_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
CPSID I ; Mask interrupts
|
||||
LDR R0, =0xE000ED08
|
||||
LDR R1, =__vector_table
|
||||
STR R1, [R0]
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
CPSIE I ; Unmask interrupts
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DMA0_DMA16_IRQHandler
|
||||
PUBWEAK DMA0_DMA16_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA0_DMA16_IRQHandler
|
||||
LDR R0, =DMA0_DMA16_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA1_DMA17_IRQHandler
|
||||
PUBWEAK DMA1_DMA17_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA1_DMA17_IRQHandler
|
||||
LDR R0, =DMA1_DMA17_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA2_DMA18_IRQHandler
|
||||
PUBWEAK DMA2_DMA18_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA2_DMA18_IRQHandler
|
||||
LDR R0, =DMA2_DMA18_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA3_DMA19_IRQHandler
|
||||
PUBWEAK DMA3_DMA19_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA3_DMA19_IRQHandler
|
||||
LDR R0, =DMA3_DMA19_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA4_DMA20_IRQHandler
|
||||
PUBWEAK DMA4_DMA20_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA4_DMA20_IRQHandler
|
||||
LDR R0, =DMA4_DMA20_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA5_DMA21_IRQHandler
|
||||
PUBWEAK DMA5_DMA21_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA5_DMA21_IRQHandler
|
||||
LDR R0, =DMA5_DMA21_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA6_DMA22_IRQHandler
|
||||
PUBWEAK DMA6_DMA22_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA6_DMA22_IRQHandler
|
||||
LDR R0, =DMA6_DMA22_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA7_DMA23_IRQHandler
|
||||
PUBWEAK DMA7_DMA23_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA7_DMA23_IRQHandler
|
||||
LDR R0, =DMA7_DMA23_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA8_DMA24_IRQHandler
|
||||
PUBWEAK DMA8_DMA24_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA8_DMA24_IRQHandler
|
||||
LDR R0, =DMA8_DMA24_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA9_DMA25_IRQHandler
|
||||
PUBWEAK DMA9_DMA25_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA9_DMA25_IRQHandler
|
||||
LDR R0, =DMA9_DMA25_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA10_DMA26_IRQHandler
|
||||
PUBWEAK DMA10_DMA26_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA10_DMA26_IRQHandler
|
||||
LDR R0, =DMA10_DMA26_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA11_DMA27_IRQHandler
|
||||
PUBWEAK DMA11_DMA27_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA11_DMA27_IRQHandler
|
||||
LDR R0, =DMA11_DMA27_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA12_DMA28_IRQHandler
|
||||
PUBWEAK DMA12_DMA28_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA12_DMA28_IRQHandler
|
||||
LDR R0, =DMA12_DMA28_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA13_DMA29_IRQHandler
|
||||
PUBWEAK DMA13_DMA29_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA13_DMA29_IRQHandler
|
||||
LDR R0, =DMA13_DMA29_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA14_DMA30_IRQHandler
|
||||
PUBWEAK DMA14_DMA30_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA14_DMA30_IRQHandler
|
||||
LDR R0, =DMA14_DMA30_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA15_DMA31_IRQHandler
|
||||
PUBWEAK DMA15_DMA31_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA15_DMA31_IRQHandler
|
||||
LDR R0, =DMA15_DMA31_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA_Error_IRQHandler
|
||||
PUBWEAK DMA_Error_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA_Error_IRQHandler
|
||||
LDR R0, =DMA_Error_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK MCM_IRQHandler
|
||||
PUBWEAK FTFA_IRQHandler
|
||||
PUBWEAK Read_Collision_IRQHandler
|
||||
PUBWEAK LVD_LVW_IRQHandler
|
||||
PUBWEAK LLWU_IRQHandler
|
||||
PUBWEAK WDOG_EWM_IRQHandler
|
||||
PUBWEAK TRNG0_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C0_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
I2C0_IRQHandler
|
||||
LDR R0, =I2C0_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK I2C1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
I2C1_IRQHandler
|
||||
LDR R0, =I2C1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK SPI0_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SPI0_IRQHandler
|
||||
LDR R0, =SPI0_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK SPI1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SPI1_IRQHandler
|
||||
LDR R0, =SPI1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK I2S0_Tx_IRQHandler
|
||||
PUBWEAK I2S0_Tx_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
I2S0_Tx_IRQHandler
|
||||
LDR R0, =I2S0_Tx_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK I2S0_Rx_IRQHandler
|
||||
PUBWEAK I2S0_Rx_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
I2S0_Rx_IRQHandler
|
||||
LDR R0, =I2S0_Rx_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART0_IRQHandler
|
||||
PUBWEAK LPUART0_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART0_IRQHandler
|
||||
LDR R0, =LPUART0_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
PUBWEAK LPUART1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART1_IRQHandler
|
||||
LDR R0, =LPUART1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART2_IRQHandler
|
||||
PUBWEAK LPUART2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART2_IRQHandler
|
||||
LDR R0, =LPUART2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART3_IRQHandler
|
||||
PUBWEAK LPUART3_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART3_IRQHandler
|
||||
LDR R0, =LPUART3_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART4_IRQHandler
|
||||
PUBWEAK LPUART4_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART4_IRQHandler
|
||||
LDR R0, =LPUART4_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK Reserved51_IRQHandler
|
||||
PUBWEAK Reserved52_IRQHandler
|
||||
PUBWEAK EMVSIM0_IRQHandler
|
||||
PUBWEAK EMVSIM1_IRQHandler
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
PUBWEAK CMP0_IRQHandler
|
||||
PUBWEAK CMP1_IRQHandler
|
||||
PUBWEAK FTM0_IRQHandler
|
||||
PUBWEAK FTM1_IRQHandler
|
||||
PUBWEAK FTM2_IRQHandler
|
||||
PUBWEAK CMT_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK RTC_Seconds_IRQHandler
|
||||
PUBWEAK PIT0CH0_IRQHandler
|
||||
PUBWEAK PIT0CH1_IRQHandler
|
||||
PUBWEAK PIT0CH2_IRQHandler
|
||||
PUBWEAK PIT0CH3_IRQHandler
|
||||
PUBWEAK PDB0_IRQHandler
|
||||
PUBWEAK USB0_IRQHandler
|
||||
PUBWEAK USBDCD_IRQHandler
|
||||
PUBWEAK Reserved71_IRQHandler
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
PUBWEAK MCG_IRQHandler
|
||||
PUBWEAK LPTMR0_LPTMR1_IRQHandler
|
||||
PUBWEAK PORTA_IRQHandler
|
||||
PUBWEAK PORTB_IRQHandler
|
||||
PUBWEAK PORTC_IRQHandler
|
||||
PUBWEAK PORTD_IRQHandler
|
||||
PUBWEAK PORTE_IRQHandler
|
||||
PUBWEAK SWI_IRQHandler
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
PUBWEAK SPI2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SPI2_IRQHandler
|
||||
LDR R0, =SPI2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK Reserved82_IRQHandler
|
||||
PUBWEAK Reserved83_IRQHandler
|
||||
PUBWEAK Reserved84_IRQHandler
|
||||
PUBWEAK Reserved85_IRQHandler
|
||||
PUBWEAK FLEXIO0_IRQHandler
|
||||
PUBWEAK FLEXIO0_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
FLEXIO0_IRQHandler
|
||||
LDR R0, =FLEXIO0_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK FTM3_IRQHandler
|
||||
PUBWEAK Reserved88_IRQHandler
|
||||
PUBWEAK Reserved89_IRQHandler
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
PUBWEAK I2C2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
I2C2_IRQHandler
|
||||
LDR R0, =I2C2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK Reserved91_IRQHandler
|
||||
PUBWEAK Reserved92_IRQHandler
|
||||
PUBWEAK Reserved93_IRQHandler
|
||||
PUBWEAK Reserved94_IRQHandler
|
||||
PUBWEAK Reserved95_IRQHandler
|
||||
PUBWEAK Reserved96_IRQHandler
|
||||
PUBWEAK SDHC_IRQHandler
|
||||
PUBWEAK SDHC_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SDHC_IRQHandler
|
||||
LDR R0, =SDHC_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK Reserved98_IRQHandler
|
||||
PUBWEAK Reserved99_IRQHandler
|
||||
PUBWEAK Reserved100_IRQHandler
|
||||
PUBWEAK Reserved101_IRQHandler
|
||||
PUBWEAK Reserved102_IRQHandler
|
||||
PUBWEAK TSI0_IRQHandler
|
||||
PUBWEAK TPM1_IRQHandler
|
||||
PUBWEAK TPM2_IRQHandler
|
||||
PUBWEAK Reserved106_IRQHandler
|
||||
PUBWEAK I2C3_IRQHandler
|
||||
PUBWEAK I2C3_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
I2C3_IRQHandler
|
||||
LDR R0, =I2C3_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK Reserved108_IRQHandler
|
||||
PUBWEAK Reserved109_IRQHandler
|
||||
PUBWEAK Reserved110_IRQHandler
|
||||
PUBWEAK Reserved111_IRQHandler
|
||||
PUBWEAK Reserved112_IRQHandler
|
||||
PUBWEAK Reserved113_IRQHandler
|
||||
PUBWEAK Reserved114_IRQHandler
|
||||
PUBWEAK Reserved115_IRQHandler
|
||||
PUBWEAK QuadSPI0_IRQHandler
|
||||
PUBWEAK QuadSPI0_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
QuadSPI0_IRQHandler
|
||||
LDR R0, =QuadSPI0_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK Reserved117_IRQHandler
|
||||
PUBWEAK Reserved118_IRQHandler
|
||||
PUBWEAK Reserved119_IRQHandler
|
||||
PUBWEAK LTC0_IRQHandler
|
||||
PUBWEAK Reserved121_IRQHandler
|
||||
PUBWEAK Reserved122_IRQHandler
|
||||
PUBWEAK DefaultISR
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA0_DMA16_DriverIRQHandler
|
||||
DMA1_DMA17_DriverIRQHandler
|
||||
DMA2_DMA18_DriverIRQHandler
|
||||
DMA3_DMA19_DriverIRQHandler
|
||||
DMA4_DMA20_DriverIRQHandler
|
||||
DMA5_DMA21_DriverIRQHandler
|
||||
DMA6_DMA22_DriverIRQHandler
|
||||
DMA7_DMA23_DriverIRQHandler
|
||||
DMA8_DMA24_DriverIRQHandler
|
||||
DMA9_DMA25_DriverIRQHandler
|
||||
DMA10_DMA26_DriverIRQHandler
|
||||
DMA11_DMA27_DriverIRQHandler
|
||||
DMA12_DMA28_DriverIRQHandler
|
||||
DMA13_DMA29_DriverIRQHandler
|
||||
DMA14_DMA30_DriverIRQHandler
|
||||
DMA15_DMA31_DriverIRQHandler
|
||||
DMA_Error_DriverIRQHandler
|
||||
MCM_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
Read_Collision_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
LLWU_IRQHandler
|
||||
WDOG_EWM_IRQHandler
|
||||
TRNG0_IRQHandler
|
||||
I2C0_DriverIRQHandler
|
||||
I2C1_DriverIRQHandler
|
||||
SPI0_DriverIRQHandler
|
||||
SPI1_DriverIRQHandler
|
||||
I2S0_Tx_DriverIRQHandler
|
||||
I2S0_Rx_DriverIRQHandler
|
||||
LPUART0_DriverIRQHandler
|
||||
LPUART1_DriverIRQHandler
|
||||
LPUART2_DriverIRQHandler
|
||||
LPUART3_DriverIRQHandler
|
||||
LPUART4_DriverIRQHandler
|
||||
Reserved51_IRQHandler
|
||||
Reserved52_IRQHandler
|
||||
EMVSIM0_IRQHandler
|
||||
EMVSIM1_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
CMP1_IRQHandler
|
||||
FTM0_IRQHandler
|
||||
FTM1_IRQHandler
|
||||
FTM2_IRQHandler
|
||||
CMT_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT0CH0_IRQHandler
|
||||
PIT0CH1_IRQHandler
|
||||
PIT0CH2_IRQHandler
|
||||
PIT0CH3_IRQHandler
|
||||
PDB0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USBDCD_IRQHandler
|
||||
Reserved71_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
MCG_IRQHandler
|
||||
LPTMR0_LPTMR1_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTB_IRQHandler
|
||||
PORTC_IRQHandler
|
||||
PORTD_IRQHandler
|
||||
PORTE_IRQHandler
|
||||
SWI_IRQHandler
|
||||
SPI2_DriverIRQHandler
|
||||
Reserved82_IRQHandler
|
||||
Reserved83_IRQHandler
|
||||
Reserved84_IRQHandler
|
||||
Reserved85_IRQHandler
|
||||
FLEXIO0_DriverIRQHandler
|
||||
FTM3_IRQHandler
|
||||
Reserved88_IRQHandler
|
||||
Reserved89_IRQHandler
|
||||
I2C2_DriverIRQHandler
|
||||
Reserved91_IRQHandler
|
||||
Reserved92_IRQHandler
|
||||
Reserved93_IRQHandler
|
||||
Reserved94_IRQHandler
|
||||
Reserved95_IRQHandler
|
||||
Reserved96_IRQHandler
|
||||
SDHC_DriverIRQHandler
|
||||
Reserved98_IRQHandler
|
||||
Reserved99_IRQHandler
|
||||
Reserved100_IRQHandler
|
||||
Reserved101_IRQHandler
|
||||
Reserved102_IRQHandler
|
||||
TSI0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
Reserved106_IRQHandler
|
||||
I2C3_DriverIRQHandler
|
||||
Reserved108_IRQHandler
|
||||
Reserved109_IRQHandler
|
||||
Reserved110_IRQHandler
|
||||
Reserved111_IRQHandler
|
||||
Reserved112_IRQHandler
|
||||
Reserved113_IRQHandler
|
||||
Reserved114_IRQHandler
|
||||
Reserved115_IRQHandler
|
||||
QuadSPI0_DriverIRQHandler
|
||||
Reserved117_IRQHandler
|
||||
Reserved118_IRQHandler
|
||||
Reserved119_IRQHandler
|
||||
LTC0_IRQHandler
|
||||
Reserved121_IRQHandler
|
||||
Reserved122_IRQHandler
|
||||
DefaultISR
|
||||
B DefaultISR
|
||||
|
||||
END
|
||||
@@ -0,0 +1,13 @@
|
||||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC11U24 specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#else
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#endif
|
||||
|
||||
/* Symbols defined by the linker script */
|
||||
#define NVIC_NUM_VECTORS (16 + 107) // CORE + MCU Peripherals
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
|
||||
defined(CPU_MK82FN256VLQ15))
|
||||
|
||||
#define K82F25615_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MK82F25615.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "MK82F25615_features.h"
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK82FN256CAx15
|
||||
** MK82FN256VDC15
|
||||
** MK82FN256VLL15
|
||||
** MK82FN256VLQ15
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
|
||||
** Version: rev. 1.2, 2015-07-29
|
||||
** Build: b151216
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2015-04-09)
|
||||
** Initial version
|
||||
** - rev. 1.1 (2015-05-28)
|
||||
** Update according to the reference manual Rev. 0.
|
||||
** - rev. 1.2 (2015-07-29)
|
||||
** Correction of backward compatibility.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MK82F25615
|
||||
* @version 1.2
|
||||
* @date 2015-07-29
|
||||
* @brief Device specific configuration file for MK82F25615 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
|
||||
#if (DISABLE_WDOG)
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
|
||||
/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
|
||||
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
|
||||
/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
|
||||
WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
|
||||
WDOG_STCTRLH_WAITEN_MASK |
|
||||
WDOG_STCTRLH_STOPEN_MASK |
|
||||
WDOG_STCTRLH_ALLOWUPDATE_MASK |
|
||||
WDOG_STCTRLH_CLKSRC_MASK |
|
||||
0x0100U;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
||||
uint16_t Divider;
|
||||
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
|
||||
/* Output of FLL or PLL is selected */
|
||||
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
|
||||
/* FLL is selected */
|
||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
|
||||
/* External reference clock is selected */
|
||||
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
|
||||
case 0x00U:
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
break;
|
||||
case 0x01U:
|
||||
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||||
break;
|
||||
case 0x02U:
|
||||
default:
|
||||
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
|
||||
break;
|
||||
}
|
||||
if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
|
||||
switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
|
||||
case 0x38U:
|
||||
Divider = 1536U;
|
||||
break;
|
||||
case 0x30U:
|
||||
Divider = 1280U;
|
||||
break;
|
||||
default:
|
||||
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
break;
|
||||
}
|
||||
} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
|
||||
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
}
|
||||
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
||||
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
||||
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
|
||||
/* Select correct multiplier to calculate the MCG output clock */
|
||||
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||||
case 0x00U:
|
||||
MCGOUTClock *= 640U;
|
||||
break;
|
||||
case 0x20U:
|
||||
MCGOUTClock *= 1280U;
|
||||
break;
|
||||
case 0x40U:
|
||||
MCGOUTClock *= 1920U;
|
||||
break;
|
||||
case 0x60U:
|
||||
MCGOUTClock *= 2560U;
|
||||
break;
|
||||
case 0x80U:
|
||||
MCGOUTClock *= 732U;
|
||||
break;
|
||||
case 0xA0U:
|
||||
MCGOUTClock *= 1464U;
|
||||
break;
|
||||
case 0xC0U:
|
||||
MCGOUTClock *= 2197U;
|
||||
break;
|
||||
case 0xE0U:
|
||||
MCGOUTClock *= 2929U;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
||||
/* PLL is selected */
|
||||
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
|
||||
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
||||
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
|
||||
MCGOUTClock *= Divider; /* Calculate the VCO output clock */
|
||||
MCGOUTClock /= 2; /* Calculate the MCG output clock */
|
||||
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
|
||||
/* Internal reference clock is selected */
|
||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
||||
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
|
||||
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
|
||||
MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
|
||||
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
|
||||
/* External reference clock is selected */
|
||||
switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
|
||||
case 0x00U:
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||||
break;
|
||||
case 0x01U:
|
||||
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||||
break;
|
||||
case 0x02U:
|
||||
default:
|
||||
MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
|
||||
break;
|
||||
}
|
||||
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
|
||||
/* Reserved value */
|
||||
return;
|
||||
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
|
||||
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
}
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MK82FN256CAx15
|
||||
** MK82FN256VDC15
|
||||
** MK82FN256VLL15
|
||||
** MK82FN256VLQ15
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
|
||||
** Version: rev. 1.2, 2015-07-29
|
||||
** Build: b151216
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2015 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2015-04-09)
|
||||
** Initial version
|
||||
** - rev. 1.1 (2015-05-28)
|
||||
** Update according to the reference manual Rev. 0.
|
||||
** - rev. 1.2 (2015-07-29)
|
||||
** Correction of backward compatibility.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MK82F25615
|
||||
* @version 1.2
|
||||
* @date 2015-07-29
|
||||
* @brief Device specific configuration file for MK82F25615 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MK82F25615_H_
|
||||
#define _SYSTEM_MK82F25615_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 12000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
|
||||
#define CPU_XTAL32k_CLK_HZ 32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_IRC_CLK_HZ 48000000U /* Value of the 48M internal oscillator clock frequency in Hz */
|
||||
|
||||
/* RTC oscillator setting */
|
||||
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
|
||||
#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
|
||||
#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 20971520u
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MK82F25615_H_ */
|
||||
Reference in New Issue
Block a user