Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
@@ -0,0 +1,139 @@
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#! armclang -E
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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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||||
*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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||||
* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "../../../device/partition_M2351_mem.h"
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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LR_IROM1 MBED_APP_START
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{
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/* load address = execution address */
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ER_IROM1 +0
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{
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*(RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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/* Boot stack requirement
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*
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* Secure non-PSA/Non-secure non-PSA/Non-secure PSA requires just one boot stack (MSP).
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* Secure PSA(TFM) requires two boot stacks (MSP/PSP).
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*/
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#if TFM_LVL == 0
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ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
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{
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}
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#else
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/* Stack Pointer (SP) configuration with ARM/ARMC6
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*
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* SP would go through the following configuration sequence:
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* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
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* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
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* (3.1) SP(PSP) <- ARM_LIB_STACK (C/C++ runtime initialization)
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* (3.2) SP(PSP) reconfigured in __user_setup_stackheap()
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*
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* S(3.1) or S(3.2) may cause SP(PSP) incorrectly configured. We name ARM_LIB_STACK for
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* PSP stack rather than MSP stack to get around this error. MSP stack is named separately
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* with ARM_LIB_STACK_MSP.
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*/
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#warning("Ignore MBED_BOOT_STACK_SIZE in Secure PSA build")
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ARM_LIB_STACK_MSP MBED_RAM_APP_START EMPTY 0x800
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{
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}
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ARM_LIB_STACK AlignExpr(+0, 32) EMPTY 0x800
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{
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}
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#endif
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/* Reserve for vectors
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*
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* Vector table base address is required to be 128-byte aligned at a minimum.
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* A PE might impose further restrictions on it. */
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ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
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{
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}
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#if TFM_LVL == 0
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/* 16 byte-aligned */
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RW_IRAM1 AlignExpr(+0, 16)
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{
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
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{
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}
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#elif TFM_LVL == 1
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TFM_SECURE_STACK AlignExpr(+0, 128) EMPTY 0x1000
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{
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}
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TFM_UNPRIV_SCRATCH AlignExpr(+0, 32) EMPTY 0x400
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{
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}
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/* 16 byte-aligned */
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ER_TFM_DATA AlignExpr(+0, 16)
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{
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(ER_TFM_DATA), 16))
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{
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}
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#elif TFM_LVL > 1
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#error("TFM level 2/3 are not supported yet")
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#endif
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}
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LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
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{
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ER_IROM_NSC NU_TZ_NSC_START FIXED PADVALUE 0xFFFFFFFF NU_TZ_NSC_SIZE
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{
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*(Veneer$$CMSE)
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}
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}
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/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
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ScatterAssert(ImageBase(ER_IROM_NSC) >= 0x4000)
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/* Heap must be allocated in RAM. */
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ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
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#if (TFM_LVL > 0)
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/* Application ROM code cannot overlap with TDB internal storage area. */
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ScatterAssert(LoadLimit(LR_IROM1) <= NU_TDB_INTERNAL_STORAGE_START)
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#endif
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@@ -0,0 +1,398 @@
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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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||||
* Licensed under the Apache License, Version 2.0 (the "License");
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||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
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/*
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* Nuvoton M2351 GCC linker script file
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*/
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#include "../../../device/partition_M2351_mem.h"
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#ifndef MBED_BOOT_STACK_SIZE
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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#if (TFM_LVL == 0)
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StackSize = MBED_BOOT_STACK_SIZE;
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#else
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#warning("Ignore MBED_BOOT_STACK_SIZE in Secure PSA build")
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__msp_stack_size__ = 0x00000800;
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__psp_stack_size__ = 0x00000800;
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#endif
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MEMORY
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{
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VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
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FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
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FLASH_NSC (rx) : ORIGIN = NU_TZ_NSC_START, LENGTH = NU_TZ_NSC_SIZE
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RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE
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}
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/**
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* Must match cmsis_nvic.h
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*/
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__vector_size = 4 * (16 + 102);
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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||||
* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.isr_vector :
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{
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__vector_table = .;
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KEEP(*(.vector_table))
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. = ALIGN(8);
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} > VECTORS
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#if (TFM_LVL == 0)
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.copy.table : ALIGN(4)
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{
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__copy_table_start__ = .;
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LONG (LOADADDR(.data))
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LONG (ADDR(.data))
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LONG (SIZEOF(.data))
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__copy_table_end__ = .;
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} > FLASH
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.zero.table : ALIGN(4)
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{
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__zero_table_start__ = .;
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LONG (ADDR(.bss))
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LONG (SIZEOF(.bss))
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__zero_table_end__ = .;
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} > FLASH
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#elif (TFM_LVL == 1)
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.copy.table : ALIGN(4)
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{
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__copy_table_start__ = .;
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LONG (LOADADDR(.TFM_DATA))
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LONG (ADDR(.TFM_DATA))
|
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LONG (SIZEOF(.TFM_DATA))
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__copy_table_end__ = .;
|
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} > FLASH
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.zero.table : ALIGN(4)
|
||||
{
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||||
__zero_table_start__ = .;
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LONG (ADDR(.TFM_BSS))
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LONG (SIZEOF(.TFM_BSS))
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LONG (ADDR(.TFM_SECURE_STACK))
|
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LONG (SIZEOF(.TFM_SECURE_STACK))
|
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LONG (ADDR(.TFM_UNPRIV_SCRATCH))
|
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LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
|
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__zero_table_end__ = .;
|
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} > FLASH
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#else
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||||
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#error("TFM level 2/3 are not supported yet")
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||||
|
||||
#endif
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|
||||
.text :
|
||||
{
|
||||
*(.text*)
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||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
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||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
/* Stack Pointer (SP) configuration with GCC_ARM
|
||||
*
|
||||
* SP would go through the following configuration sequence:
|
||||
* (1) SP(MSP) <- Entry 0 of vector table (on H/W reset)
|
||||
* (2) Switch SP from MSP to PSP in startup file (as TFM requests)
|
||||
* (3) SP(PSP) <- __stack (in _start(), C/C++ runtime initialization)
|
||||
*
|
||||
* S(3) may cause SP(PSP) incorrectly configured. To avoid this error, __stack
|
||||
* is assigned conditionally according to Secure PSA or not.
|
||||
*/
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
|
||||
.stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
. += StackSize;
|
||||
__StackTop = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
#else
|
||||
|
||||
.msp_stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
. += __msp_stack_size__;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack);
|
||||
Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
|
||||
__StackLimit = Image$$ARM_LIB_STACK_MSP$$ZI$$Base;
|
||||
__StackTop = Image$$ARM_LIB_STACK_MSP$$ZI$$Limit;
|
||||
|
||||
.psp_stack (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
. += __psp_stack_size__;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
|
||||
Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
|
||||
|
||||
PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
|
||||
|
||||
#endif
|
||||
|
||||
#if (TFM_LVL == 1)
|
||||
|
||||
.TFM_SECURE_STACK (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(128);
|
||||
. += 0x1000;
|
||||
} > RAM_INTERN
|
||||
Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
|
||||
Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
|
||||
|
||||
.TFM_UNPRIV_SCRATCH (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
. += 0x400;
|
||||
} > RAM_INTERN
|
||||
Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
|
||||
Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
|
||||
|
||||
#elif (TFM_LVL > 1)
|
||||
|
||||
#error("TFM level 2/3 are not supported yet")
|
||||
|
||||
#endif
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
/* Relocate vector table in SRAM */
|
||||
.isr_vector.reloc (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(1 << LOG2CEIL(__vector_size));
|
||||
PROVIDE(__start_vector_table__ = .);
|
||||
. += __vector_size;
|
||||
PROVIDE(__end_vector_table__ = .);
|
||||
} > RAM_INTERN
|
||||
|
||||
#if (TFM_LVL == 0)
|
||||
|
||||
.data :
|
||||
{
|
||||
PROVIDE( __etext = LOADADDR(.data) );
|
||||
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
/* All data end */
|
||||
. = ALIGN(32);
|
||||
__data_end__ = .;
|
||||
|
||||
} >RAM_INTERN AT>FLASH
|
||||
|
||||
.bss (NOLOAD):
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM_INTERN
|
||||
|
||||
#else
|
||||
|
||||
.TFM_DATA :
|
||||
{
|
||||
PROVIDE( __etext = LOADADDR(.TFM_DATA) );
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
__data_start__ = .;
|
||||
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM_INTERN AT>FLASH
|
||||
Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
|
||||
Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
|
||||
|
||||
.TFM_BSS (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM_INTERN
|
||||
Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
|
||||
Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
|
||||
|
||||
#endif
|
||||
|
||||
#if (TFM_LVL > 0)
|
||||
/* Application ROM code cannot overlap with TDB internal storage area. */
|
||||
ASSERT((LOADADDR(.TFM_DATA) + SIZEOF(.TFM_DATA)) <= NU_TDB_INTERNAL_STORAGE_START, "Application ROM code cannot overlap with TDB internal storage area.")
|
||||
#endif
|
||||
|
||||
/* Veneer$$CMSE : */
|
||||
.gnu.sgstubs NU_TZ_NSC_START :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
|
||||
__sgstubs_start = .;
|
||||
*(.gnu.sgstubs.*)
|
||||
__sgstubs_end = .;
|
||||
|
||||
. = ALIGN(32);
|
||||
} > FLASH_NSC
|
||||
|
||||
/* NOTE: __sgstubs_end is not updated with *(.gnu.sgstubs.*). __sgstubs_start and
|
||||
* __sgstubs_end are the same. GCC bug? */
|
||||
Image$$ER_IROM_NSC$$Base = ADDR(.gnu.sgstubs);
|
||||
ASSERT(SIZEOF(.gnu.sgstubs) <= NU_TZ_NSC_SIZE, "Size of .gnu.sgstubs region cannot exceed NU_TZ_NSC_SIZE.")
|
||||
|
||||
/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. */
|
||||
ASSERT(((__sgstubs_start % 32) == 0), "Requested by SAU, NSC region must start at 32 byte-aligned boundary.")
|
||||
ASSERT(__sgstubs_start >= 0x4000, "By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.")
|
||||
|
||||
.heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*);
|
||||
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
|
||||
__HeapLimit = .;
|
||||
} > RAM_INTERN
|
||||
Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);
|
||||
Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
|
||||
|
||||
PROVIDE(__heap_size = SIZEOF(.heap));
|
||||
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
|
||||
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
|
||||
}
|
||||
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2019, Nuvoton Technology Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
|
||||
include "../../../device/partition_M2351_mem.icf.h";
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/* FIXME: Check NSC area requirement */
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
|
||||
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
if (TFM_LVL > 0) {
|
||||
define symbol __ICFEDIT_size_cstack_msp__ = 0x800;
|
||||
}
|
||||
define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
|
||||
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
|
||||
|
||||
/* IAR has something wrong with "$$" in section/block name. So unlike other toolchains,
|
||||
* we name "ER_IROM_NSC" instead of "Image$$ER_IROM_NSC". */
|
||||
define block ER_IROM_NSC with alignment = 32 { readonly section Veneer$$CMSE };
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
if (TFM_LVL > 0) {
|
||||
define block CSTACK_MSP with alignment = 8, size = __ICFEDIT_size_cstack_msp__ { };
|
||||
}
|
||||
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
|
||||
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
|
||||
define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
|
||||
|
||||
if (TFM_LVL == 1) {
|
||||
define block TDB_INTERNAL_STORAGE with size = NU_TDB_INTERNAL_STORAGE_SIZE{ };
|
||||
define block TFM_SECURE_STACK with alignment = 128, size = 0x1000 { };
|
||||
define block TFM_UNPRIV_SCRATCH with alignment = 32, size = 0x400 { };
|
||||
define block ER_TFM_DATA with alignment = 8 { readwrite };
|
||||
} else if (TFM_LVL > 1) {
|
||||
error "TFM level 2/3 are not supported yet";
|
||||
}
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place at address mem: NU_TZ_NSC_START { block ER_IROM_NSC };
|
||||
|
||||
if (TFM_LVL == 0) {
|
||||
place at start of IRAM_region { block CSTACK };
|
||||
} else {
|
||||
place at start of IRAM_region { block CSTACK_MSP };
|
||||
place in IRAM_region { block CSTACK };
|
||||
}
|
||||
place in IRAM_region { block IRAMVEC };
|
||||
|
||||
if (TFM_LVL == 0) {
|
||||
place in IRAM_region { readwrite };
|
||||
} else if (TFM_LVL == 1) {
|
||||
place at address mem: NU_TDB_INTERNAL_STORAGE_START { block TDB_INTERNAL_STORAGE };
|
||||
place in IRAM_region { block TFM_SECURE_STACK };
|
||||
place in IRAM_region { block TFM_UNPRIV_SCRATCH };
|
||||
place in IRAM_region { block ER_TFM_DATA };
|
||||
} else {
|
||||
error "TFM level 2/3 are not supported yet";
|
||||
}
|
||||
|
||||
place in IRAM_region { block HEAP };
|
||||
|
||||
define exported symbol Image$$ER_IROM_NSC$$Base = NU_TZ_NSC_START;
|
||||
|
||||
/* TODO: Export the following symbols to support TFM secure code */
|
||||
/*
|
||||
if (TFM_LVL > 0) {
|
||||
define exported symbol Image$$ARM_LIB_STACK$$ZI$$Limit = Start of CSTACK;
|
||||
}
|
||||
if (TFM_LVL == 1) {
|
||||
define exported symbol Image$$TFM_SECURE_STACK$$ZI$$Base = Start of TFM_SECURE_STACK;
|
||||
define exported symbol Image$$TFM_SECURE_STACK$$ZI$$Limit = End of TFM_SECURE_STACK;
|
||||
define exported symbol Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = Start of TFM_UNPRIV_SCRATCH;
|
||||
define exported symbol Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = End of TFM_UNPRIV_SCRATCH;
|
||||
define exported symbol Image$$ER_TFM_DATA$$RW$$Base = Start of ER_TFM_DATA (readwrite - zeroinit);
|
||||
define exported symbol Image$$ER_TFM_DATA$$RW$$Limit = End of ER_TFM_DATA (zeroinit);
|
||||
define exported symbol Image$$ER_TFM_DATA$$ZI$$Base = End of ER_TFM_DATA (zeroinit);
|
||||
define exported symbol Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
|
||||
define exported symbol Image$$ARM_LIB_HEAP$$ZI$$Base = Start of HEAP;
|
||||
define exported symbol Image$$ARM_LIB_HEAP$$ZI$$Limit = End of HEAP;
|
||||
}
|
||||
*/
|
||||
Reference in New Issue
Block a user