Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
539
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h
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539
targets/TARGET_NUVOTON/TARGET_M2351/device/partition_M2351.h
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@@ -0,0 +1,539 @@
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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef PARTITION_M2351
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#define PARTITION_M2351
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#include "partition_M2351_mem.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#if defined(__ARMCC_VERSION)
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extern int Image$$ER_IROM_NSC$$Base;
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#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
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#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
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#elif defined(__ICCARM__)
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extern int Image$$ER_IROM_NSC$$Base;
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#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
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#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
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#elif defined(__GNUC__)
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extern int Image$$ER_IROM_NSC$$Base;
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#define NU_TZ_NSC_REGION_START ((uint32_t) &Image$$ER_IROM_NSC$$Base)
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#define NU_TZ_NSC_REGION_SIZE (NU_TZ_NSC_SIZE)
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#endif
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
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*/
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/*
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SRAMNSSET
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*/
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/*
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// Bit 0..16
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// <o.0..16> Secure SRAM Size <0=> 0 KB
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// <0x2000=> 8KB
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// <0x4000=> 16KB
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// <0x6000=> 24KB
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// <0x8000=> 32KB
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// <0xa000=> 40KB
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// <0xc000=> 48KB
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// <0xe000=> 56KB
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// <0x10000=> 64KB
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// <0x12000=> 72KB
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// <0x14000=> 80KB
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// <0x16000=> 88KB
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// <0x18000=> 96KB
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*/
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#define SCU_SECURE_SRAM_SIZE NU_RAM_SIZE_S
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#define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
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/*--------------------------------------------------------------------------------------------------------*/
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/*
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NSBA
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*/
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#define FMC_INIT_NSBA 1
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/*
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// <o>Secure Flash ROM Size <0x800-0x80000:0x800>
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*/
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#define FMC_SECURE_ROM_SIZE NU_ROM_SIZE_S
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#define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
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/*--------------------------------------------------------------------------------------------------------*/
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/*
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// <h> Peripheral Secure Attribution Configuration
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*/
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/*
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PNSSET0
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*/
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/*
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// Module 0..31
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// <o.9> USBH <0=> Secure <1=> Non-Secure
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// <o.13> SD0 <0=> Secure <1=> Non-Secure
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// <o.16> EBI <0=> Secure <1=> Non-Secure
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// <o.24> PDMA1 <0=> Secure <1=> Non-Secure
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*/
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#define SCU_INIT_PNSSET0_VAL 0xFFFFFFFF
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/*
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PNSSET1
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*/
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/*
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// Module 0..31
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// <o.17> CRC <0=> Secure <1=> Non-Secure
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// <o.18> CRPT <0=> Secure <1=> Non-Secure
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*/
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#define SCU_INIT_PNSSET1_VAL 0xFFFFFFFF
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/*
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PNSSET2
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*/
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/*
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// Module 0..31
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// <o.1> RTC <0=> Secure <1=> Non-Secure
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// <o.3> EADC <0=> Secure <1=> Non-Secure
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// <o.5> ACMP01 <0=> Secure <1=> Non-Secure
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//
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// <o.7> DAC <0=> Secure <1=> Non-Secure
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// <o.8> I2S0 <0=> Secure <1=> Non-Secure
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// <o.13> OTG <0=> Secure <1=> Non-Secure
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// <o.17> TMR23 <0=> Secure <1=> Non-Secure
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// <h> EPWM
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// <o.24> EPWM0 <0=> Secure <1=> Non-Secure
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// <o.25> EPWM1 <0=> Secure <1=> Non-Secure
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// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
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// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
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// </h>
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*/
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#define SCU_INIT_PNSSET2_VAL 0xFFFFFFFD
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/*
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PNSSET3
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*/
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/*
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// Module 0..31
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// <h> SPI
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// <o.0> QSPI0 <0=> Secure <1=> Non-Secure
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// <o.1> SPI0 <0=> Secure <1=> Non-Secure
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// <o.2> SPI1 <0=> Secure <1=> Non-Secure
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// <o.3> SPI2 <0=> Secure <1=> Non-Secure
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// <o.4> SPI3 <0=> Secure <1=> Non-Secure
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// </h>
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// <h> UART
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// <o.16> UART0 <0=> Secure <1=> Non-Secure
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// <o.17> UART1 <0=> Secure <1=> Non-Secure
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// <o.18> UART2 <0=> Secure <1=> Non-Secure
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// <o.19> UART3 <0=> Secure <1=> Non-Secure
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// <o.20> UART4 <0=> Secure <1=> Non-Secure
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// <o.21> UART5 <0=> Secure <1=> Non-Secure
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// </h>
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*/
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#define SCU_INIT_PNSSET3_VAL 0xFFFFFFFF
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/*
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PNSSET4
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*/
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/*
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// Module 0..31
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// <h> I2C
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// <o.0> I2C0 <0=> Secure <1=> Non-Secure
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// <o.1> I2C1 <0=> Secure <1=> Non-Secure
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// <o.2> I2C2 <0=> Secure <1=> Non-Secure
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// </h>
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// <h> Smart Card
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// <o.16> SC0 <0=> Secure <1=> Non-Secure
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// <o.17> SC1 <0=> Secure <1=> Non-Secure
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// <o.18> SC2 <0=> Secure <1=> Non-Secure
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// </h>
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*/
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#define SCU_INIT_PNSSET4_VAL 0xFFFFFFFF
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/*
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PNSSET5
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*/
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/*
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// Module 0..31
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// <o.0> CAN0 <0=> Secure <1=> Non-Secure
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// <h> QEI
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// <o.16> QEI0 <0=> Secure <1=> Non-Secure
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// <o.17> QEI1 <0=> Secure <1=> Non-Secure
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// </h>
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// <h> ECAP
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// <o.20> ECAP0 <0=> Secure <1=> Non-Secure
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// <o.21> ECAP1 <0=> Secure <1=> Non-Secure
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// </h>
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// <o.25> TRNG <0=> Secure <1=> Non-Secure
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*/
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#define SCU_INIT_PNSSET5_VAL 0xFDFFFFFF
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/*
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PNSSET6
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*/
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/*
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// Module 0..31
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// <o.0> USBD <0=> Secure <1=> Non-Secure
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// <h> USCI
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// <o.16> USCI0 <0=> Secure <1=> Non-Secure
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// <o.17> USCI1 <0=> Secure <1=> Non-Secure
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// </h>
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*/
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#define SCU_INIT_PNSSET6_VAL 0xFFFFFFFF
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/*
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// </h>
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*/
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/*
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// <h> GPIO Secure Attribution Configuration
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*/
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/*
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IONSSET
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*/
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/*
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// Bit 0..31
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// <o.0> PA <0=> Secure <1=> Non-Secure
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// <o.1> PB <0=> Secure <1=> Non-Secure
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// <o.2> PC <0=> Secure <1=> Non-Secure
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// <o.3> PD <0=> Secure <1=> Non-Secure
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// <o.4> PE <0=> Secure <1=> Non-Secure
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// <o.5> PF <0=> Secure <1=> Non-Secure
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// <o.6> PG <0=> Secure <1=> Non-Secure
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// <o.7> PH <0=> Secure <1=> Non-Secure
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*/
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#define SCU_INIT_IONSSET_VAL 0xFFFFFFFF
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/*
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// </h>
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*/
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/* ---------------------------------------------------------------------------------------------------- */
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/*
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// <e>Secure Attribute Unit (SAU) Control
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*/
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#define SAU_INIT_CTRL 1
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/*
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// <q> Enable SAU
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// <i> To enable Secure Attribute Unit (SAU).
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*/
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#define SAU_INIT_CTRL_ENABLE 1
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/*
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// <o> All Memory Attribute When SAU is disabled
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// <0=> All Memory is Secure
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// <1=> All Memory is Non-Secure
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// <i> To set the ALLNS bit in SAU CTRL.
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// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
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*/
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#define SAU_INIT_CTRL_ALLNS 0
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/*
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// </e>
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*/
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/*
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// <h>Enable and Set Secure/Non-Secure region
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*/
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#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
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/*
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// <e>SAU Region 0
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// <i> Setup SAU Region 0
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*/
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#define SAU_INIT_REGION0 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC0 1
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/*
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// </e>
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*/
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/*
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// <e>SAU Region 1
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// <i> Setup SAU Region 1
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*/
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#define SAU_INIT_REGION1 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START1 0x10040000
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END1 0x1007FFFF
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC1 0
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/*
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// </e>
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*/
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/*
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// <e>SAU Region 2
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// <i> Setup SAU Region 2
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*/
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#define SAU_INIT_REGION2 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START2 0x2000F000
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END2 0x2000FFFF
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/*
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// <o>Region is
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// <0=>Non-Secure
|
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// <1=>Secure, Non-Secure Callable
|
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*/
|
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#define SAU_INIT_NSC2 1
|
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/*
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// </e>
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*/
|
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|
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/*
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// <e>SAU Region 3
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// <i> Setup SAU Region 3
|
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*/
|
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#define SAU_INIT_REGION3 1
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/*
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// <o>Start Address <0-0xFFFFFFE0>
|
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*/
|
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#define SAU_INIT_START3 NU_TZ_NSC_REGION_START
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/*
|
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// <o>End Address <0x1F-0xFFFFFFFF>
|
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*/
|
||||
#define SAU_INIT_END3 (NU_TZ_NSC_REGION_START + NU_TZ_NSC_REGION_SIZE - 1)
|
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/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
<e>SAU Region 4
|
||||
<i> Setup SAU Region 4
|
||||
*/
|
||||
#define SAU_INIT_REGION4 1
|
||||
/*
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
<e>SAU Region 5
|
||||
<i> Setup SAU Region 5
|
||||
*/
|
||||
#define SAU_INIT_REGION5 1
|
||||
|
||||
/*
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x00807E00
|
||||
|
||||
/*
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x00807FFF
|
||||
|
||||
/*
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 1
|
||||
/*
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
<e>SAU Region 6
|
||||
<i> Setup SAU Region 6
|
||||
*/
|
||||
#define SAU_INIT_REGION6 1
|
||||
|
||||
/*
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 NON_SECURE_SRAM_BASE
|
||||
|
||||
/*
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x30017FFF
|
||||
|
||||
/*
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
<e>SAU Region 7
|
||||
<i> Setup SAU Region 7
|
||||
*/
|
||||
#define SAU_INIT_REGION7 1
|
||||
|
||||
/*
|
||||
<o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x50000000
|
||||
|
||||
/*
|
||||
<o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x5FFFFFFF
|
||||
|
||||
/*
|
||||
<o>Region is
|
||||
<0=>Non-Secure
|
||||
<1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
</e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behavior of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 1
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x80-0xFF
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 0
|
||||
|
||||
/* Assign HardFault to be always secure for safe */
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/*
|
||||
max 128 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#if TFM_LVL == 0
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
#else
|
||||
#define SAU_INIT_REGION(n, tfm_n) \
|
||||
SAU->RNR = (tfm_n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
#endif
|
||||
|
||||
|
||||
#if SCB_AIRCR_SYSRESETREQS_VAL == 1
|
||||
#warning ("Debugger (and other) resets fail when SCB_AIRCR_SYSRESETREQS_VAL == 1!!!")
|
||||
#endif
|
||||
|
||||
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PARTITION_M2351 */
|
||||
Reference in New Issue
Block a user