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/****************************************************************************//**
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* @file spi.c
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* @version V0.10
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* $Revision: 7 $
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* $Date: 15/05/28 1:33p $
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* @brief NANO100 series SPI driver source file
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*
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* @note
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "Nano100Series.h"
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_SPI_Driver SPI Driver
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@{
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*/
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/** @addtogroup NANO100_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
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@{
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*/
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/**
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* @brief This function make SPI module be ready to transfer.
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* By default, the SPI transfer sequence is MSB first and
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* the automatic slave select function is disabled. In
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* Slave mode, the u32BusClock must be NULL and the SPI clock
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* divider setting will be 0.
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* @param[in] spi is the base address of SPI module.
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* @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are:
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* - \ref SPI_MASTER
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* - \ref SPI_SLAVE
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* @param[in] u32SPIMode decides the transfer timing. Valid values are:
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* - \ref SPI_MODE_0
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* - \ref SPI_MODE_1
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* - \ref SPI_MODE_2
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* - \ref SPI_MODE_3
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* @param[in] u32DataWidth decides the data width of a SPI transaction.
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* @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz.
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* @return Actual frequency of SPI peripheral clock.
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*/
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uint32_t SPI_Open(SPI_T *spi,
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uint32_t u32MasterSlave,
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uint32_t u32SPIMode,
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uint32_t u32DataWidth,
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uint32_t u32BusClock)
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{
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if(u32DataWidth == 32)
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u32DataWidth = 0;
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spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
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return ( SPI_SetBusClock(spi, u32BusClock) );
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}
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/**
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* @brief Reset SPI module and disable SPI peripheral clock.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_Close(SPI_T *spi)
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{
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/* Reset SPI */
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if(spi == SPI0) {
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SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk;
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SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
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} else if(spi == SPI1) {
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SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk;
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SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
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} else {
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SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI2_RST_Msk;
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SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk;
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}
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}
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/**
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* @brief Clear Rx FIFO buffer.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_ClearRxFIFO(SPI_T *spi)
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{
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spi->FFCTL |= SPI_FFCTL_RX_CLR_Msk;
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}
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/**
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* @brief Clear Tx FIFO buffer.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_ClearTxFIFO(SPI_T *spi)
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{
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spi->FFCTL |= SPI_FFCTL_TX_CLR_Msk;
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}
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/**
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* @brief Disable the automatic slave select function.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_DisableAutoSS(SPI_T *spi)
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{
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spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
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}
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/**
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* @brief Enable the automatic slave select function. Only available in Master mode.
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* @param[in] spi is the base address of SPI module.
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* @param[in] u32SSPinMask specifies slave select pins. (SPI_SS)
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* @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
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* - \ref SPI_SS0_ACTIVE_HIGH
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* - \ref SPI_SS0_ACTIVE_LOW
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* - \ref SPI_SS1_ACTIVE_HIGH
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* - \ref SPI_SS1_ACTIVE_LOW
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* @return none
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*/
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void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
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{
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spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
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}
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/**
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* @brief Set the SPI bus clock. Only available in Master mode.
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* @param[in] spi is the base address of SPI module.
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* @param[in] u32BusClock is the expected frequency of SPI bus clock.
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* @return Actual frequency of SPI peripheral clock.
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*/
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uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
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{
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uint32_t u32ClkSrc, u32Div = 0;
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if(spi == SPI0) {
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if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
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u32ClkSrc = CLK_GetHCLKFreq();
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else
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u32ClkSrc = CLK_GetPLLClockFreq();
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} else if(spi == SPI1) {
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if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
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u32ClkSrc = CLK_GetHCLKFreq();
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else
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u32ClkSrc = CLK_GetPLLClockFreq();
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} else {
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if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
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u32ClkSrc = CLK_GetHCLKFreq();
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else
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u32ClkSrc = CLK_GetPLLClockFreq();
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}
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if(u32BusClock > u32ClkSrc)
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u32BusClock = u32ClkSrc;
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if(u32BusClock != 0 ) {
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u32Div = (u32ClkSrc / u32BusClock) - 1;
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if(u32Div > SPI_CLKDIV_DIVIDER1_Msk)
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u32Div = SPI_CLKDIV_DIVIDER1_Msk;
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} else
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u32Div = 0;
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spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
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return ( u32ClkSrc / (u32Div+1) );
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}
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/**
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* @brief Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
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* @param[in] spi is the base address of SPI module.
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* @param[in] u32TxThreshold decides the Tx FIFO threshold.
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* @param[in] u32RxThreshold decides the Rx FIFO threshold.
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* @return none
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*/
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void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
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{
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spi->FFCTL = (spi->FFCTL & ~(SPI_FFCTL_TX_THRESHOLD_Msk | SPI_FFCTL_RX_THRESHOLD_Msk) |
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(u32TxThreshold << SPI_FFCTL_TX_THRESHOLD_Pos) |
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(u32RxThreshold << SPI_FFCTL_RX_THRESHOLD_Pos));
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spi->CTL |= SPI_CTL_FIFOM_Msk;
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}
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/**
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* @brief Disable FIFO mode.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_DisableFIFO(SPI_T *spi)
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{
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spi->CTL &= ~SPI_CTL_FIFOM_Msk;
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}
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/**
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* @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
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* @param[in] spi is the base address of SPI module.
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* @return Actual SPI bus clock frequency.
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*/
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uint32_t SPI_GetBusClock(SPI_T *spi)
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{
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uint32_t u32Div;
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uint32_t u32ClkSrc;
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if(spi == SPI0) {
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if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
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u32ClkSrc = CLK_GetHCLKFreq();
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else
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u32ClkSrc = CLK_GetPLLClockFreq();
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} else if(spi == SPI1) {
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if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
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u32ClkSrc = CLK_GetHCLKFreq();
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else
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u32ClkSrc = CLK_GetPLLClockFreq();
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} else {
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if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
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u32ClkSrc = CLK_GetHCLKFreq();
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else
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u32ClkSrc = CLK_GetPLLClockFreq();
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}
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u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk;
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return (u32ClkSrc / (u32Div + 1));
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}
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/**
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* @brief Enable FIFO related interrupts specified by u32Mask parameter.
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* @param[in] spi is the base address of SPI module.
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* @param[in] u32Mask is the combination of all related interrupt enable bits.
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* Each bit corresponds to a interrupt bit.
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* This parameter decides which interrupts will be enabled. Valid values are:
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* - \ref SPI_IE_MASK
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* - \ref SPI_SSTA_INTEN_MASK
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* - \ref SPI_FIFO_TX_INTEN_MASK
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* - \ref SPI_FIFO_RX_INTEN_MASK
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* - \ref SPI_FIFO_RXOVR_INTEN_MASK
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* - \ref SPI_FIFO_TIMEOUT_INTEN_MASK
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* @return none
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*/
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void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
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{
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if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
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spi->CTL |= SPI_CTL_INTEN_Msk;
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if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
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spi->SSR |= SPI_SSR_SSTA_INTEN_Msk;
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if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
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spi->FFCTL |= SPI_FFCTL_TX_INTEN_Msk;
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if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
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spi->FFCTL |= SPI_FFCTL_RX_INTEN_Msk;
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if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
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spi->FFCTL |= SPI_FFCTL_RXOVR_INTEN_Msk;
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if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
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spi->FFCTL |= SPI_FFCTL_TIMEOUT_EN_Msk;
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}
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/**
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* @brief Disable FIFO related interrupts specified by u32Mask parameter.
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* @param[in] spi is the base address of SPI module.
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* @param[in] u32Mask is the combination of all related interrupt enable bits.
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* Each bit corresponds to a interrupt bit.
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* This parameter decides which interrupts will be enabled. Valid values are:
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* - \ref SPI_IE_MASK
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* - \ref SPI_SSTA_INTEN_MASK
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* - \ref SPI_FIFO_TX_INTEN_MASK
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* - \ref SPI_FIFO_RX_INTEN_MASK
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* - \ref SPI_FIFO_RXOVR_INTEN_MASK
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* - \ref SPI_FIFO_TIMEOUT_INTEN_MASK
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* @return none
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*/
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void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
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{
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if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
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spi->CTL &= ~SPI_CTL_INTEN_Msk;
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if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
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spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
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if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
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spi->FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk;
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if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
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spi->FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk;
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if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
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spi->FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk;
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if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
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spi->FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk;
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}
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/**
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* @brief Enable wake-up function.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_EnableWakeup(SPI_T *spi)
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{
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spi->CTL |= SPI_CTL_WKEUP_EN_Msk;
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}
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/**
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* @brief Disable wake-up function.
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* @param[in] spi is the base address of SPI module.
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* @return none
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*/
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void SPI_DisableWakeup(SPI_T *spi)
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{
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spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk;
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}
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/*@}*/ /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_SPI_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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