Import Mbed OS hard-float snapshot

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0_features.h

@@ -0,0 +1,292 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2018-08-22
+**     Build:               b190122
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**
+** ###################################################################
+*/
+
+#ifndef _LPC55S69_cm33_core0_FEATURES_H_
+#define _LPC55S69_cm33_core0_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief CASPER availability on the SoC. */
+#define FSL_FEATURE_SOC_CASPER_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (2)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief SECGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
+/* @brief HASHCRYPT availability on the SoC. */
+#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (8)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (8)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LPADC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)
+/* @brief MAILBOX availability on the SoC. */
+#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief OSTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief SECPINT availability on the SoC. */
+#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief POWERQUAD availability on the SoC. */
+#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
+/* @brief PUF availability on the SoC. */
+#define FSL_FEATURE_SOC_PUF_COUNT (1)
+/* @brief RNG1 availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (9)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief SYSCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (8)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* LPADC module features */
+
+/* @brief FIFO availability on the SoC. */
+#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
+/* @brief Has conversion resolution select  (bitfield CMDLn[MODE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+
+/* CASPER module features */
+
+/* @brief Base address of the CASPER dedicated RAM */
+#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
+/* @brief Interleaving of the CASPER dedicated RAM */
+#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+
+/* HASHCRYPT module features */
+
+/* @brief the address of alias offset */
+#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer. */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* MAILBOX module features */
+
+/* @brief Mailbox side for current core */
+#define FSL_FEATURE_MAILBOX_SIDE_A (1)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)
+
+/* POWERLIB module features */
+
+/* @brief Niobe4's Powerlib API is different with other LPC series devices. */
+#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)
+
+/* POWERQUAD module features */
+
+/* @brief Sine and Cossine fix errata */
+#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA  (1)
+
+/* PUF module features */
+
+/* @brief Number of PUF key slots available on device. */
+#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
+/* @brief the shift status value */
+#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+/* @brief support 2 cards */
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD  (1)
+
+/* SECPINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
+/* @brief Has Power Down mode */
+#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
+/* @brief CCM_ANALOG availability on the SoC.  */
+#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USB version */
+#define FSL_FEATURE_USB_VERSION (200)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBFSH version */
+#define FSL_FEATURE_USBFSH_VERSION (200)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+
+/* UTICK module features */
+
+/* @brief UTICK does not support PD configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+
+/* WWDT module features */
+
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
+/* @brief WWDT does not support power down configure */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
+#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */
+

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1_features.h

@@ -0,0 +1,292 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2018-08-22
+**     Build:               b190122
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**
+** ###################################################################
+*/
+
+#ifndef _LPC55S69_cm33_core1_FEATURES_H_
+#define _LPC55S69_cm33_core1_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief CASPER availability on the SoC. */
+#define FSL_FEATURE_SOC_CASPER_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (2)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief SECGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
+/* @brief HASHCRYPT availability on the SoC. */
+#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (8)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (8)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LPADC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)
+/* @brief MAILBOX availability on the SoC. */
+#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief OSTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief SECPINT availability on the SoC. */
+#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief POWERQUAD availability on the SoC. */
+#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
+/* @brief PUF availability on the SoC. */
+#define FSL_FEATURE_SOC_PUF_COUNT (1)
+/* @brief RNG1 availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (9)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief SYSCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (8)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* LPADC module features */
+
+/* @brief FIFO availability on the SoC. */
+#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
+/* @brief Has conversion resolution select  (bitfield CMDLn[MODE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+
+/* CASPER module features */
+
+/* @brief Base address of the CASPER dedicated RAM */
+#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
+/* @brief Interleaving of the CASPER dedicated RAM */
+#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+
+/* HASHCRYPT module features */
+
+/* @brief the address of alias offset */
+#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer. */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* MAILBOX module features */
+
+/* @brief Mailbox side for current core */
+#define FSL_FEATURE_MAILBOX_SIDE_B (1)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)
+
+/* POWERLIB module features */
+
+/* @brief Niobe4's Powerlib API is different with other LPC series devices. */
+#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)
+
+/* POWERQUAD module features */
+
+/* @brief Sine and Cossine fix errata */
+#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA  (1)
+
+/* PUF module features */
+
+/* @brief Number of PUF key slots available on device. */
+#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
+/* @brief the shift status value */
+#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+/* @brief support 2 cards */
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD  (1)
+
+/* SECPINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
+/* @brief Has Power Down mode */
+#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
+/* @brief CCM_ANALOG availability on the SoC.  */
+#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USB version */
+#define FSL_FEATURE_USB_VERSION (200)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBFSH version */
+#define FSL_FEATURE_USBFSH_VERSION (200)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+
+/* UTICK module features */
+
+/* @brief UTICK does not support PD configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+
+/* WWDT module features */
+
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
+/* @brief WWDT does not support power down configure */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
+#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */
+

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/cmsis.h

@@ -0,0 +1,18 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC54608 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "fsl_device_registers.h"
+#include "platform_regs.h"              /* Platform registers */
+#include "platform_retarget.h"          /* Peripherals base addresses */
+
+#if defined(TARGET_LPC55S69_NS)
+#include "cmsis_nvic.h"
+#endif
+
+#endif

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/fsl_device_registers.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0))
+
+#define LPC55S69_cm33_core0_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC55S69_cm33_core0.h"
+/* CPU specific feature definitions */
+#include "LPC55S69_cm33_core0_features.h"
+
+#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1))
+
+#define LPC55S69_cm33_core1_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC55S69_cm33_core1.h"
+/* CPU specific feature definitions */
+#include "LPC55S69_cm33_core1_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_regs.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2018 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ARM_LTD_NIOBE_REGS_H__
+#define __ARM_LTD_NIOBE_REGS_H__
+
+#include <stdint.h>
+#include "platform_retarget.h"
+
+/* Secure System Control (SYSCTRL) Alias */
+#define CMSDK_SYSCTRL_BASE_S    SYSCON_BASE + 0xFA4
+
+/* sysctrl memory mapped register access structure */
+struct sysctrl_t {
+		union {
+			volatile uint32_t secdbgstat;             /* (R/ ) Secure Debug Configuration
+                                               *       Status Register*/
+      volatile uint32_t secdbgset;              /* ( /W) Secure Debug Configuration
+                                               *       Set Register */
+      volatile uint32_t secdbgclr;              /* ( /W) Secure Debug Configuration
+                                               *       Clear Register */
+		};
+};
+
+#endif /* __ARM_LTD_NIOBE_REGS_H__ */

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/platform_retarget.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2017-2018 Arm Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * \file platform_retarget.h
+ * \brief This file defines all the peripheral base addresses for Niobe platform.
+ */
+
+#ifndef __ARM_LTD_NIOBE_RETARGET_H__
+#define __ARM_LTD_NIOBE_RETARGET_H__
+
+#include "platform_regs.h"           /* Platform registers */
+#include "LPC55S69_cm33_core0.h"
+
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+#define MPC_ISRAM0_RANGE_BASE_NS   0x20000000
+#define MPC_ISRAM0_RANGE_LIMIT_NS  0x2000FFFF
+#define MPC_ISRAM0_RANGE_BASE_S    0x30000000
+#define MPC_ISRAM0_RANGE_LIMIT_S   0x3000FFFF
+
+#define MPC_ISRAM1_RANGE_BASE_NS   0x20010000
+#define MPC_ISRAM1_RANGE_LIMIT_NS  0x2001FFFF
+#define MPC_ISRAM1_RANGE_BASE_S    0x30010000
+#define MPC_ISRAM1_RANGE_LIMIT_S   0x3001FFFF
+
+#define MPC_ISRAM2_RANGE_BASE_NS   0x20020000
+#define MPC_ISRAM2_RANGE_LIMIT_NS  0x2002FFFF
+#define MPC_ISRAM2_RANGE_BASE_S    0x30020000
+#define MPC_ISRAM2_RANGE_LIMIT_S   0x3002FFFF
+
+#define MPC_ISRAM3_RANGE_BASE_NS   0x20030000
+#define MPC_ISRAM3_RANGE_LIMIT_NS  0x2003FFFF
+#define MPC_ISRAM3_RANGE_BASE_S    0x30030000
+#define MPC_ISRAM3_RANGE_LIMIT_S   0x3003FFFF
+
+#define MPC_ISRAM4_RANGE_BASE_NS   0x20040000
+#define MPC_ISRAM4_RANGE_LIMIT_NS  0x20043FFF 
+#define MPC_ISRAM4_RANGE_BASE_S    0x30040000
+#define MPC_ISRAM4_RANGE_LIMIT_S   0x30043FFF
+
+/* Code SRAM memory */
+#define MPC_CODE_SRAM_RANGE_BASE_NS  (0x04000000)
+#define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x04007FFF)
+#define MPC_CODE_SRAM_RANGE_BASE_S   (0x14000000)
+#define MPC_CODE_SRAM_RANGE_LIMIT_S  (0x14007FFF)
+
+/* Internal Flash memory */
+#define FLASH0_BASE_S                 (0x10000000)
+#define FLASH0_BASE_NS                (0x00000000)
+#define FLASH0_SIZE                   (0x0009FFFF)  /* 640 kB */
+#define FLASH0_SECTOR_SIZE            (0x00008000)  /* 32 kB */
+#define FLASH0_PAGE_SIZE              (0x00000200)  /* 512 B */
+#define FLASH0_PROGRAM_UNIT           (0x4)         /* Minimum write size */
+
+#endif  /* __ARM_LTD_NIOBE_RETARGET_H__ */

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.c

@@ -0,0 +1,369 @@
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JET98_cm33_core0
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.4  25 Sep 2018
+**     Version:             rev. 1.0, 2018-08-22
+**     Build:               b181219
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC55S69_cm33_core0
+ * @version 1.0
+ * @date 2018-08-22
+ * @brief Device specific configuration file for LPC55S69_cm33_core0
+ *        (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+/* PLL0 SSCG control1 */
+#define PLL_SSCG_MD_FRACT_P 0U
+#define PLL_SSCG_MD_INT_P 25U
+#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P)
+#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P)
+
+/* Get predivider (N) from PLL0 NDEC setting */
+static uint32_t findPll0PreDiv(void)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
+    {
+        preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
+        if (preDiv == 0)
+        {
+            preDiv = 1;
+        }
+    }
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL0 PDEC setting */
+static uint32_t findPll0PostDiv(void)
+{
+    uint32_t postDiv = 1;
+
+    if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
+    {
+        if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
+        {
+            postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
+        }
+        else
+        {
+            postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
+        }
+        if (postDiv == 0)
+        {
+            postDiv = 2;
+        }
+    }
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
+static float findPll0MMult(void)
+{
+    float mMult = 1;
+    float mMult_fract;
+    uint32_t mMult_int;
+
+    if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
+    {
+        mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
+    }
+    else
+    {
+        mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
+        mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P));
+        mMult = (float)mMult_int + mMult_fract;
+    }
+    if (mMult == 0)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+/* Get predivider (N) from PLL1 NDEC setting */
+static uint32_t findPll1PreDiv(void)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
+    {
+        preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
+        if (preDiv == 0)
+        {
+            preDiv = 1;
+        }
+    }
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL1 PDEC setting */
+static uint32_t findPll1PostDiv(void)
+{
+    uint32_t postDiv = 1;
+
+    if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)
+    {
+        if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
+        {
+            postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
+        }
+        else
+        {
+            postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
+        }
+        if (postDiv == 0)
+        {
+            postDiv = 2;
+        }
+    }
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL1 MDEC settings */
+static uint32_t findPll1MMult(void)
+{
+    uint32_t mMult = 1;
+
+    mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
+
+    if (mMult == 0)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+/* Get FRO 12M Clk */
+/*! brief  Return Frequency of FRO 12MHz
+ *  return Frequency of FRO 12MHz
+ */
+static uint32_t CLOCK_GetFro12MFreq(void)
+{
+    return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
+               0 :
+               (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
+}
+
+/* Get FRO 1M Clk */
+/*! brief  Return Frequency of FRO 1MHz
+ *  return Frequency of FRO 1MHz
+ */
+static uint32_t CLOCK_GetFro1MFreq(void)
+{
+    return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
+}
+
+/* Get EXT OSC Clk */
+/*! brief  Return Frequency of External Clock
+ *  return Frequency of External Clock. If no external clock is used returns 0.
+ */
+static uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;
+}
+
+/* Get HF FRO Clk */
+/*! brief  Return Frequency of High-Freq output of FRO
+ *  return Frequency of High-Freq output of FRO
+ */
+static uint32_t CLOCK_GetFroHfFreq(void)
+{
+    return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
+               0 :
+               (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
+}
+
+/* Get RTC OSC Clk */
+/*! brief  Return Frequency of 32kHz osc
+ *  return Frequency of 32kHz osc
+ */
+static uint32_t CLOCK_GetOsc32KFreq(void)
+{
+    return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?
+               CLK_RTC_32K_CLK :
+               ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?
+               CLK_RTC_32K_CLK :
+               0U;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+  SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access (enable PowerQuad) */
+
+  SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
+
+#if defined(__MCUXPRESSO)
+    extern void(*const g_pfnVectors[]) (void);
+    SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+    extern void *__Vectors;
+    SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+    SYSCON->TRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+    SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK
+                          | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
+#endif
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+    uint32_t clkRate = 0;
+    uint32_t prediv, postdiv;
+    float workRate;
+    uint64_t workRate1;
+
+    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+    {
+        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLOCK_GetFro12MFreq();
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLOCK_GetExtClkFreq();
+                    break;
+                case 0x02: /* Fro 1MHz (fro_1m) */
+                    clkRate = CLOCK_GetFro1MFreq();
+                    break;
+                default: /* = 0x03 = FRO 96 MHz (fro_hf) */
+                    clkRate = CLOCK_GetFroHfFreq();
+                    break;
+            }
+            break;
+        case 0x01: /* PLL0 clock (pll0_clk)*/
+            switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLOCK_GetFro12MFreq();
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLOCK_GetExtClkFreq();
+                    break;
+                case 0x02: /* Fro 1MHz (fro_1m) */
+                    clkRate = CLOCK_GetFro1MFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLOCK_GetOsc32KFreq();
+                    break;
+                default:
+                    break;
+            }
+            if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
+            {
+                prediv = findPll0PreDiv();
+                postdiv = findPll0PostDiv();
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+                /* MDEC used for rate */
+                workRate = (float)clkRate * (float)findPll0MMult();
+                clkRate = (uint32_t)(workRate / ((float)postdiv));
+            }
+            break;
+        case 0x02: /* PLL1 clock (pll1_clk)*/
+            switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLOCK_GetFro12MFreq();
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLOCK_GetExtClkFreq();
+                    break;
+                case 0x02: /* Fro 1MHz (fro_1m) */
+                    clkRate = CLOCK_GetFro1MFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLOCK_GetOsc32KFreq();
+                    break;
+                default:
+                    break;
+            }
+            if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))
+            {
+                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+                prediv = findPll1PreDiv();
+                postdiv = findPll1PostDiv();
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+
+                /* MDEC used for rate */
+                workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();
+                clkRate = workRate1 / ((uint64_t)postdiv);
+            }
+            break;
+        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+            clkRate = CLOCK_GetOsc32KFreq();
+            break;
+        default:
+            break;
+    }
+    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core0.h

@@ -0,0 +1,110 @@
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JET98_cm33_core0
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.4  25 Sep 2018
+**     Version:             rev. 1.0, 2018-08-22
+**     Build:               b181219
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC55S69_cm33_core0
+ * @version 1.0
+ * @date 2018-08-22
+ * @brief Device specific configuration file for LPC55S69_cm33_core0 (header
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC55S69_cm33_core0_H_
+#define _SYSTEM_LPC55S69_cm33_core0_H_           /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                     16000000u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC55S69_cm33_core0_H_ */

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/system_LPC55S69_cm33_core1.h

@@ -0,0 +1,110 @@
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core1
+**                          LPC55S69JET98_cm33_core1
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.4  25 Sep 2018
+**     Version:             rev. 1.0, 2018-08-22
+**     Build:               b181219
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC55S69_cm33_core1
+ * @version 1.0
+ * @date 2018-08-22
+ * @brief Device specific configuration file for LPC55S69_cm33_core1 (header
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC55S69_cm33_core1_H_
+#define _SYSTEM_LPC55S69_cm33_core1_H_           /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                     16000000u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC55S69_cm33_core1_H_ */