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/*
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** ###################################################################
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** Version: rev. 1.1, 2018-11-16
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** Build: b190319
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2019 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 0.1 (2017-01-10)
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** Initial version.
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** - rev. 1.0 (2018-09-21)
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** Update interrupt vector table and dma request source.
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** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
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** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
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** - rev. 1.1 (2018-11-16)
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** Update feature files to align with IMXRT1050RM Rev.1.
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**
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** ###################################################################
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*/
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#ifndef _MIMXRT1052_FEATURES_H_
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#define _MIMXRT1052_FEATURES_H_
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/* SOC module features */
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/* @brief ADC availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC_COUNT (2)
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/* @brief AIPSTZ availability on the SoC. */
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#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
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/* @brief AOI availability on the SoC. */
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#define FSL_FEATURE_SOC_AOI_COUNT (2)
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/* @brief CCM availability on the SoC. */
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#define FSL_FEATURE_SOC_CCM_COUNT (1)
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/* @brief CCM_ANALOG availability on the SoC. */
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#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
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/* @brief CMP availability on the SoC. */
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#define FSL_FEATURE_SOC_CMP_COUNT (4)
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/* @brief CSI availability on the SoC. */
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#define FSL_FEATURE_SOC_CSI_COUNT (1)
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/* @brief DCDC availability on the SoC. */
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#define FSL_FEATURE_SOC_DCDC_COUNT (1)
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/* @brief DCP availability on the SoC. */
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#define FSL_FEATURE_SOC_DCP_COUNT (1)
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/* @brief DMAMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
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/* @brief EDMA availability on the SoC. */
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#define FSL_FEATURE_SOC_EDMA_COUNT (1)
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/* @brief ENC availability on the SoC. */
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#define FSL_FEATURE_SOC_ENC_COUNT (4)
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/* @brief ENET availability on the SoC. */
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#define FSL_FEATURE_SOC_ENET_COUNT (1)
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/* @brief EWM availability on the SoC. */
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#define FSL_FEATURE_SOC_EWM_COUNT (1)
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/* @brief FLEXCAN availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
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/* @brief FLEXIO availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
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/* @brief FLEXRAM availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
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/* @brief FLEXSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
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/* @brief GPC availability on the SoC. */
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#define FSL_FEATURE_SOC_GPC_COUNT (1)
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/* @brief GPT availability on the SoC. */
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#define FSL_FEATURE_SOC_GPT_COUNT (2)
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/* @brief I2S availability on the SoC. */
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#define FSL_FEATURE_SOC_I2S_COUNT (3)
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/* @brief IGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
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/* @brief IOMUXC availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
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/* @brief IOMUXC_GPR availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
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/* @brief IOMUXC_SNVS availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
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/* @brief KPP availability on the SoC. */
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#define FSL_FEATURE_SOC_KPP_COUNT (1)
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/* @brief LCDIF availability on the SoC. */
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#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
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/* @brief LPI2C availability on the SoC. */
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#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
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/* @brief LPSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
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/* @brief LPUART availability on the SoC. */
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#define FSL_FEATURE_SOC_LPUART_COUNT (8)
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/* @brief OCOTP availability on the SoC. */
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#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
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/* @brief PIT availability on the SoC. */
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#define FSL_FEATURE_SOC_PIT_COUNT (1)
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/* @brief PMU availability on the SoC. */
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#define FSL_FEATURE_SOC_PMU_COUNT (1)
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/* @brief PWM availability on the SoC. */
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#define FSL_FEATURE_SOC_PWM_COUNT (4)
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/* @brief PXP availability on the SoC. */
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#define FSL_FEATURE_SOC_PXP_COUNT (1)
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/* @brief ROMC availability on the SoC. */
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#define FSL_FEATURE_SOC_ROMC_COUNT (1)
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/* @brief SEMC availability on the SoC. */
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#define FSL_FEATURE_SOC_SEMC_COUNT (1)
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/* @brief SNVS availability on the SoC. */
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#define FSL_FEATURE_SOC_SNVS_COUNT (1)
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/* @brief SPDIF availability on the SoC. */
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#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
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/* @brief SRC availability on the SoC. */
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#define FSL_FEATURE_SOC_SRC_COUNT (1)
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/* @brief TEMPMON availability on the SoC. */
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#define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
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/* @brief TMR availability on the SoC. */
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#define FSL_FEATURE_SOC_TMR_COUNT (4)
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/* @brief TRNG availability on the SoC. */
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#define FSL_FEATURE_SOC_TRNG_COUNT (1)
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/* @brief TSC availability on the SoC. */
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#define FSL_FEATURE_SOC_TSC_COUNT (1)
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/* @brief USBHS availability on the SoC. */
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#define FSL_FEATURE_SOC_USBHS_COUNT (2)
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/* @brief USBNC availability on the SoC. */
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#define FSL_FEATURE_SOC_USBNC_COUNT (2)
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/* @brief USBPHY availability on the SoC. */
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#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
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/* @brief USDHC availability on the SoC. */
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#define FSL_FEATURE_SOC_USDHC_COUNT (2)
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/* @brief WDOG availability on the SoC. */
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#define FSL_FEATURE_SOC_WDOG_COUNT (2)
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/* @brief XBARA availability on the SoC. */
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#define FSL_FEATURE_SOC_XBARA_COUNT (1)
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/* @brief XBARB availability on the SoC. */
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#define FSL_FEATURE_SOC_XBARB_COUNT (2)
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/* @brief XTALOSC24M availability on the SoC. */
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#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
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/* ADC module features */
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/* @brief Remove Hardware Trigger feature. */
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#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
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/* @brief Remove ALT Clock selection feature. */
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#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
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/* @brief Conversion control count (related to number of registers HCn and Rn). */
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#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8)
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/* ADC_ETC module features */
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/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
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#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
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/* AOI module features */
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/* @brief Maximum value of input mux. */
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#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
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/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
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#define FSL_FEATURE_AOI_EVENT_COUNT (4)
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/* FLEXCAN module features */
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/* @brief Message buffer size */
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#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
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/* @brief Has doze mode support (register bit field MCR[DOZE]). */
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#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
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/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
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/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
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#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
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/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
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#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
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/* @brief Instance has extended bit timing register (register CBT). */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
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/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
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#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
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/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
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/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
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#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
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/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
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/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
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/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
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/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
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/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
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#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
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/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
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#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
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/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
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#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
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/* @brief Has extra MB interrupt or common one. */
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#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
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/* CMP module features */
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/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
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#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
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/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
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#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
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/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
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#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
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/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
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#define FSL_FEATURE_CMP_HAS_DMA (1)
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/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
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#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
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/* @brief Has DAC Test function in CMP (register DACTEST). */
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#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
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/* EDMA module features */
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/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
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/* @brief Total number of DMA channels on all modules. */
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#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
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/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
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/* @brief Has DMA_Error interrupt vector. */
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#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
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/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
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/* @brief Channel IRQ entry shared offset. */
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#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
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/* @brief If 8 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
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/* @brief If 16 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
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/* DMAMUX module features */
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/* @brief Number of DMA channels (related to number of register CHCFGn). */
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#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
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/* @brief Total number of DMA channels on all modules. */
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#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
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/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
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#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
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/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
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#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
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/* ENET module features */
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/* @brief Support Interrupt Coalesce */
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#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
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/* @brief Queue Size. */
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#define FSL_FEATURE_ENET_QUEUE (1)
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/* @brief Has AVB Support. */
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#define FSL_FEATURE_ENET_HAS_AVB (0)
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/* @brief Has Timer Pulse Width control. */
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#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
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/* @brief Has Extend MDIO Support. */
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#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
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/* @brief Has Additional 1588 Timer Channel Interrupt. */
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#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
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/* EWM module features */
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/* @brief Has clock select (register CLKCTRL). */
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#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
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/* @brief Has clock prescaler (register CLKPRESCALER). */
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#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
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/* FLEXIO module features */
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/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
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#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
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/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
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#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
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/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
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#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
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/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
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#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
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/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
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#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
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/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
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#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
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/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
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#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
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/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
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#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
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/* @brief Reset value of the FLEXIO_VERID register */
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#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
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/* @brief Reset value of the FLEXIO_PARAM register */
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#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
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/* @brief Flexio DMA request base channel */
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#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
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/* FLEXRAM module features */
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/* @brief Bank size */
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#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
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/* @brief Total Bank numbers */
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#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
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/* FLEXSPI module features */
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/* @brief FlexSPI AHB buffer count */
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#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
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/* @brief FlexSPI has no data learn. */
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#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
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/* GPC module features */
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/* @brief Has DVFS0 Change Request. */
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#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0)
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/* @brief Has GPC interrupt/event masking. */
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#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0)
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/* @brief Has L2 cache power control. */
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#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0)
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/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */
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#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1)
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/* @brief Has VADC power control. */
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#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0)
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/* @brief Has Display power control. */
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#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0)
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/* @brief Supports IRQ 0-31. */
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||||
#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
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||||
/* IGPIO module features */
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||||
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||||
/* @brief Has data register set DR_SET. */
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#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
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/* @brief Has data register clear DR_CLEAR. */
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||||
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
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/* @brief Has data register toggle DR_TOGGLE. */
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||||
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
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||||
/* LCDIF module features */
|
||||
|
||||
/* @brief LCDIF does not support alpha support. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
|
||||
/* @brief LCDIF does not support output reset pin to LCD panel. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
|
||||
/* @brief LCDIF supports LUT. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_LUT (1)
|
||||
|
||||
/* LPI2C module features */
|
||||
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
||||
|
||||
/* LPSPI module features */
|
||||
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
|
||||
/* LPUART module features */
|
||||
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
|
||||
/* @brief Has 32-bit register MODIR */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief If 10-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief If 7-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
|
||||
/* @brief Maximal data width with parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
|
||||
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
/* @brief Has separate RX and TX interrupts. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
|
||||
/* @brief Has LPAURT_PARAM. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
|
||||
/* @brief Has LPUART_VERID. */
|
||||
#define FSL_FEATURE_LPUART_HAS_VERID (1)
|
||||
/* @brief Has LPUART_GLOBAL. */
|
||||
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
|
||||
/* @brief Has LPUART_PINCFG. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
|
||||
|
||||
/* interrupt module features */
|
||||
|
||||
/* @brief Lowest interrupt request number. */
|
||||
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
|
||||
/* @brief Highest interrupt request number. */
|
||||
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
|
||||
|
||||
/* OCOTP module features */
|
||||
|
||||
/* No feature definitions */
|
||||
|
||||
/* PIT module features */
|
||||
|
||||
/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
|
||||
#define FSL_FEATURE_PIT_TIMER_COUNT (4)
|
||||
/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
|
||||
#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
|
||||
/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
|
||||
#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
|
||||
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
|
||||
#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
|
||||
/* @brief Has timer enable control. */
|
||||
#define FSL_FEATURE_PIT_HAS_MDIS (1)
|
||||
|
||||
/* PMU module features */
|
||||
|
||||
/* @brief PMU supports lower power control. */
|
||||
#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0)
|
||||
|
||||
/* PWM module features */
|
||||
|
||||
/* @brief Number of each EflexPWM module channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
|
||||
/* @brief Number of EflexPWM module A channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
|
||||
/* @brief Number of EflexPWM module B channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
|
||||
/* @brief Number of EflexPWM module X channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module compare channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module reload channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module capture channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of each EflexPWM module reload error channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of each EflexPWM module fault channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of submodules in each EflexPWM module. */
|
||||
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
|
||||
|
||||
/* PXP module features */
|
||||
|
||||
/* @brief PXP module has dither engine. */
|
||||
#define FSL_FEATURE_PXP_HAS_DITHER (0)
|
||||
/* @brief PXP module supports repeat run */
|
||||
#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
|
||||
/* @brief PXP doesn't have CSC */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
|
||||
/* @brief PXP doesn't have LUT */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_LUT (1)
|
||||
|
||||
/* RTWDOG module features */
|
||||
|
||||
/* @brief Watchdog is available. */
|
||||
#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
|
||||
/* @brief RTWDOG_CNT can be 32-bit written. */
|
||||
#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
|
||||
|
||||
/* SAI module features */
|
||||
|
||||
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
|
||||
#define FSL_FEATURE_SAI_FIFO_COUNT (32)
|
||||
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
|
||||
#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
|
||||
(((x) == SAI1) ? (4) : \
|
||||
(((x) == SAI2) ? (1) : \
|
||||
(((x) == SAI3) ? (1) : (-1))))
|
||||
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
|
||||
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
|
||||
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
|
||||
/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
|
||||
/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
|
||||
/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
|
||||
#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
|
||||
/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
|
||||
#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
|
||||
/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
|
||||
#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
|
||||
/* @brief Interrupt source number */
|
||||
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
|
||||
/* @brief Has register of MCR. */
|
||||
#define FSL_FEATURE_SAI_HAS_MCR (0)
|
||||
/* @brief Has bit field MICS of the MCR register. */
|
||||
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
|
||||
/* @brief Has register of MDR */
|
||||
#define FSL_FEATURE_SAI_HAS_MDR (0)
|
||||
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
|
||||
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
|
||||
/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
|
||||
#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
|
||||
/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
|
||||
#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
|
||||
|
||||
/* SEMC module features */
|
||||
|
||||
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
|
||||
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
|
||||
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
|
||||
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
|
||||
|
||||
/* SNVS module features */
|
||||
|
||||
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
|
||||
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
|
||||
|
||||
/* SRC module features */
|
||||
|
||||
/* @brief There is MASK_WDOG3_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1)
|
||||
/* @brief There is MIX_RST_STRCH bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0)
|
||||
/* @brief There is DBG_RST_MSK_PG bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1)
|
||||
/* @brief There is WDOG3_RST_OPTN bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0)
|
||||
/* @brief There is CORES_DBG_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0)
|
||||
/* @brief There is MTSR bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0)
|
||||
/* @brief There is CORE0_DBG_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1)
|
||||
/* @brief There is CORE0_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
|
||||
/* @brief There is LOCKUP_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
|
||||
/* @brief There is SWRC bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
|
||||
/* @brief There is EIM_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0)
|
||||
/* @brief There is LUEN bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0)
|
||||
/* @brief There is no WRBC bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1)
|
||||
/* @brief There is no WRE bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1)
|
||||
/* @brief There is SISR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SISR (0)
|
||||
/* @brief There is RESET_OUT bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
|
||||
/* @brief There is WDOG3_RST_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
|
||||
/* @brief There is SW bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
|
||||
/* @brief There is IPP_USER_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1)
|
||||
/* @brief There is SNVS bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0)
|
||||
/* @brief There is CSU_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1)
|
||||
/* @brief There is LOCKUP bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0)
|
||||
/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1)
|
||||
/* @brief There is POR bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_POR (0)
|
||||
/* @brief There is IPP_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1)
|
||||
/* @brief There is no WBI bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1)
|
||||
|
||||
/* SCB module features */
|
||||
|
||||
/* @brief L1 ICACHE line size in byte. */
|
||||
#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
|
||||
/* @brief L1 DCACHE line size in byte. */
|
||||
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
|
||||
|
||||
/* TRNG module features */
|
||||
|
||||
/* @brief TRNG has no TRNG_ACC bitfield. */
|
||||
#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
|
||||
|
||||
/* USBHS module features */
|
||||
|
||||
/* @brief EHCI module instance count */
|
||||
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
|
||||
/* @brief Number of endpoints supported */
|
||||
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
|
||||
|
||||
/* USDHC module features */
|
||||
|
||||
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
||||
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
|
||||
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
||||
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
|
||||
|
||||
/* XBARA module features */
|
||||
|
||||
/* @brief Number of interrupt requests. */
|
||||
#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
|
||||
|
||||
#endif /* _MIMXRT1052_FEATURES_H_ */
|
||||
|
||||
@@ -0,0 +1,147 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define __ram_vector_table__ 1
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x60000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_COMPILE)
|
||||
#define m_flash_config_start MBED_APP_START
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start MBED_APP_START + 0x1000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start MBED_APP_START + 0x2000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start MBED_APP_START + 0x2400
|
||||
#define m_text_size MBED_APP_SIZE - 0x2400
|
||||
#else
|
||||
#define m_interrupts_start MBED_APP_START
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start MBED_APP_START + 0x400
|
||||
#define m_text_size MBED_APP_SIZE - 0x400
|
||||
#endif
|
||||
|
||||
#define m_text2_start 0x00000000
|
||||
#define m_text2_size 0x00020000
|
||||
|
||||
#define m_data_start 0x80000000
|
||||
#define m_data_size 0x01E00000
|
||||
|
||||
#define m_ncache_start 0x81E00000
|
||||
#define m_ncache_size 0x00200000
|
||||
|
||||
#define m_interrupts_ram_start 0x20000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data2_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data2_size (0x00020000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_data3_start 0x20200000
|
||||
#define m_data3_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size MBED_BOOT_STACK_SIZE
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_IROM1 MBED_APP_START m_text_start+m_text_size-MBED_APP_START { ; load region size_region
|
||||
#if !defined(MBED_APP_COMPILE)
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_IROM1 m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data m_data_start m_data_size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
*(m_usb_dma_init_data)
|
||||
*(m_usb_dma_noninit_data)
|
||||
}
|
||||
RW_IRAM1 ImageLimit(RW_m_data) {
|
||||
}
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (m_data_start + m_data_size - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
RW_m_ram_text m_text2_start m_text2_size {
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,292 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__ram_vector_table__ = 1;
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x60000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
__stack_size__ = MBED_BOOT_STACK_SIZE;
|
||||
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
#if !defined(MBED_APP_COMPILE)
|
||||
m_flash_config (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00001000
|
||||
m_ivt (RX) : ORIGIN = MBED_APP_START + 0x1000, LENGTH = 0x00001000
|
||||
m_interrupts (RX) : ORIGIN = MBED_APP_START + 0x2000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = MBED_APP_START + 0x2400, LENGTH = MBED_APP_SIZE - 0x2400
|
||||
#else
|
||||
m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
|
||||
#endif
|
||||
m_text2 (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000
|
||||
m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
|
||||
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
|
||||
m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
#if !defined(MBED_APP_COMPILE)
|
||||
.flash_config :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__FLASH_BASE = .;
|
||||
KEEP(* (.boot_hdr.conf)) /* flash config section */
|
||||
. = ALIGN(8);
|
||||
} > m_flash_config
|
||||
|
||||
ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config);
|
||||
|
||||
.ivt : AT(ivt_begin)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(* (.boot_hdr.ivt)) /* ivt section */
|
||||
KEEP(* (.boot_hdr.boot_data)) /* boot section */
|
||||
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
|
||||
. = ALIGN(8);
|
||||
} > m_ivt
|
||||
#endif
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} > m_interrupts
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(8);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.interrupts_ram :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__VECTOR_RAM__ = .;
|
||||
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
|
||||
*(.m_interrupts_ram) /* This is a user defined section */
|
||||
. += M_VECTOR_RAM_SIZE;
|
||||
. = ALIGN(8);
|
||||
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
|
||||
} > m_data2
|
||||
|
||||
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(8);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
|
||||
|
||||
.ram_function : AT(__ram_function_flash_start)
|
||||
{
|
||||
. = ALIGN(32);
|
||||
__ram_function_start__ = .;
|
||||
*(CodeQuickAccess)
|
||||
. = ALIGN(128);
|
||||
__ram_function_end__ = .;
|
||||
} > m_text2
|
||||
|
||||
__ram_function_size = SIZEOF(.ram_function);
|
||||
|
||||
__NDATA_ROM = __ram_function_flash_start + SIZEOF(.ram_function);
|
||||
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(8);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_ncache
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(8);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_ncache
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(8);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. = ORIGIN(m_data) + LENGTH(m_data) - STACK_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol __ram_vector_table__ = 1;
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_START)) {
|
||||
define symbol MBED_APP_START = 0x60000000;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) {
|
||||
define symbol MBED_APP_SIZE = 0x400000;
|
||||
}
|
||||
|
||||
/* Sizes */
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
define symbol __stack_size__=MBED_BOOT_STACK_SIZE;
|
||||
define symbol __heap_size__=0x10000;
|
||||
|
||||
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
|
||||
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_COMPILE)) {
|
||||
define symbol m_interrupts_start = MBED_APP_START + 0x2000;
|
||||
define symbol m_interrupts_end = MBED_APP_START + 0x23FF;
|
||||
|
||||
define symbol m_text_start = MBED_APP_START + 0x2400;
|
||||
define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
} else {
|
||||
define symbol m_interrupts_start = MBED_APP_START;
|
||||
define symbol m_interrupts_end = MBED_APP_START + 0x3FF;
|
||||
|
||||
define symbol m_text_start = MBED_APP_START + 0x400;
|
||||
define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
}
|
||||
|
||||
define symbol m_text2_start = 0x00000000;
|
||||
define symbol m_text2_end = 0x0001FFFF;
|
||||
|
||||
define symbol m_interrupts_ram_start = 0x20000000;
|
||||
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
|
||||
|
||||
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x2023FFFF;
|
||||
|
||||
define symbol m_data3_start = 0x80000000;
|
||||
define symbol m_data3_end = 0x81DFFFFF;
|
||||
|
||||
define symbol m_ncache_start = 0x81E00000;
|
||||
define symbol m_ncache_end = 0x81FFFFFF;
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_COMPILE)) {
|
||||
define exported symbol m_boot_hdr_conf_start = MBED_APP_START;
|
||||
define symbol m_boot_hdr_ivt_start = MBED_APP_START + 0x1000;
|
||||
define symbol m_boot_hdr_boot_data_start = MBED_APP_START + 0x1020;
|
||||
define symbol m_boot_hdr_dcd_data_start = MBED_APP_START + 0x1030;
|
||||
}
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
|
||||
define region TEXT2_region = mem:[from m_text2_start to m_text2_end];
|
||||
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
|
||||
define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
|
||||
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
|
||||
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { first readwrite, section m_usb_dma_init_data };
|
||||
define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
|
||||
define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
|
||||
define block QACCESS_FUNC {section .textrw};
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_COMPILE)) {
|
||||
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
|
||||
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
|
||||
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
|
||||
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
|
||||
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
|
||||
}
|
||||
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA3_region { block RW };
|
||||
place in DATA3_region { block ZI };
|
||||
place in DATA3_region { last block HEAP };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
place in NCACHE_region { block NCACHE_VAR };
|
||||
place in TEXT2_region { block QACCESS_FUNC };
|
||||
place in m_interrupts_ram_region { section m_interrupts_ram };
|
||||
@@ -0,0 +1,972 @@
|
||||
; -------------------------------------------------------------------------
|
||||
; @file: startup_MIMXRT1052.s
|
||||
; @purpose: CMSIS Cortex-M7 Core Device Startup File
|
||||
; MIMXRT1052
|
||||
; @version: 1.2
|
||||
; @date: 2018-11-27
|
||||
; @build: b190124
|
||||
; -------------------------------------------------------------------------
|
||||
;
|
||||
; Copyright 1997-2016 Freescale Semiconductor, Inc.
|
||||
; Copyright 2016-2019 NXP
|
||||
; All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: BSD-3-Clause
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler ;NMI Handler
|
||||
DCD HardFault_Handler ;Hard Fault Handler
|
||||
DCD MemManage_Handler ;MPU Fault Handler
|
||||
DCD BusFault_Handler ;Bus Fault Handler
|
||||
DCD UsageFault_Handler ;Usage Fault Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD SVC_Handler ;SVCall Handler
|
||||
DCD DebugMon_Handler ;Debug Monitor Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD PendSV_Handler ;PendSV Handler
|
||||
DCD SysTick_Handler ;SysTick Handler
|
||||
|
||||
;External Interrupts
|
||||
DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete
|
||||
DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete
|
||||
DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete
|
||||
DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete
|
||||
DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete
|
||||
DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete
|
||||
DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete
|
||||
DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete
|
||||
DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete
|
||||
DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete
|
||||
DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete
|
||||
DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete
|
||||
DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete
|
||||
DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete
|
||||
DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete
|
||||
DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete
|
||||
DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31
|
||||
DCD CTI0_ERROR_IRQHandler ;CTI0_Error
|
||||
DCD CTI1_ERROR_IRQHandler ;CTI1_Error
|
||||
DCD CORE_IRQHandler ;CorePlatform exception IRQ
|
||||
DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt
|
||||
DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt
|
||||
DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt
|
||||
DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt
|
||||
DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt
|
||||
DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt
|
||||
DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt
|
||||
DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt
|
||||
DCD LPI2C1_IRQHandler ;LPI2C1 interrupt
|
||||
DCD LPI2C2_IRQHandler ;LPI2C2 interrupt
|
||||
DCD LPI2C3_IRQHandler ;LPI2C3 interrupt
|
||||
DCD LPI2C4_IRQHandler ;LPI2C4 interrupt
|
||||
DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources
|
||||
DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources
|
||||
DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources
|
||||
DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources
|
||||
DCD CAN1_IRQHandler ;CAN1 interrupt
|
||||
DCD CAN2_IRQHandler ;CAN2 interrupt
|
||||
DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ
|
||||
DCD KPP_IRQHandler ;Keypad nterrupt
|
||||
DCD TSC_DIG_IRQHandler ;TSC interrupt
|
||||
DCD GPR_IRQ_IRQHandler ;GPR interrupt
|
||||
DCD LCDIF_IRQHandler ;LCDIF interrupt
|
||||
DCD CSI_IRQHandler ;CSI interrupt
|
||||
DCD PXP_IRQHandler ;PXP interrupt
|
||||
DCD WDOG2_IRQHandler ;WDOG2 interrupt
|
||||
DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ
|
||||
DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ
|
||||
DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event)
|
||||
DCD CSU_IRQHandler ;CSU interrupt
|
||||
DCD DCP_IRQHandler ;DCP_IRQ interrupt
|
||||
DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt
|
||||
DCD Reserved68_IRQHandler ;Reserved interrupt
|
||||
DCD TRNG_IRQHandler ;TRNG interrupt
|
||||
DCD SJC_IRQHandler ;SJC interrupt
|
||||
DCD BEE_IRQHandler ;BEE interrupt
|
||||
DCD SAI1_IRQHandler ;SAI1 interrupt
|
||||
DCD SAI2_IRQHandler ;SAI1 interrupt
|
||||
DCD SAI3_RX_IRQHandler ;SAI3 interrupt
|
||||
DCD SAI3_TX_IRQHandler ;SAI3 interrupt
|
||||
DCD SPDIF_IRQHandler ;SPDIF interrupt
|
||||
DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt
|
||||
DCD Reserved78_IRQHandler ;Reserved interrupt
|
||||
DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt
|
||||
DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt
|
||||
DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt
|
||||
DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt
|
||||
DCD ADC1_IRQHandler ;ADC1 interrupt
|
||||
DCD ADC2_IRQHandler ;ADC2 interrupt
|
||||
DCD DCDC_IRQHandler ;DCDC interrupt
|
||||
DCD Reserved86_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved87_IRQHandler ;Reserved interrupt
|
||||
DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO
|
||||
DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO
|
||||
DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO
|
||||
DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO
|
||||
DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO
|
||||
DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO
|
||||
DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO
|
||||
DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO
|
||||
DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15
|
||||
DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31
|
||||
DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15
|
||||
DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31
|
||||
DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15
|
||||
DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31
|
||||
DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15
|
||||
DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31
|
||||
DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15
|
||||
DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31
|
||||
DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt
|
||||
DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt
|
||||
DCD WDOG1_IRQHandler ;WDOG1 interrupt
|
||||
DCD RTWDOG_IRQHandler ;RTWDOG interrupt
|
||||
DCD EWM_IRQHandler ;EWM interrupt
|
||||
DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt
|
||||
DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt
|
||||
DCD GPC_IRQHandler ;GPC interrupt
|
||||
DCD SRC_IRQHandler ;SRC interrupt
|
||||
DCD Reserved115_IRQHandler ;Reserved interrupt
|
||||
DCD GPT1_IRQHandler ;GPT1 interrupt
|
||||
DCD GPT2_IRQHandler ;GPT2 interrupt
|
||||
DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt
|
||||
DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt
|
||||
DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt
|
||||
DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt
|
||||
DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt
|
||||
DCD Reserved123_IRQHandler ;Reserved interrupt
|
||||
DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt
|
||||
DCD SEMC_IRQHandler ;Reserved interrupt
|
||||
DCD USDHC1_IRQHandler ;USDHC1 interrupt
|
||||
DCD USDHC2_IRQHandler ;USDHC2 interrupt
|
||||
DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2
|
||||
DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1
|
||||
DCD ENET_IRQHandler ;ENET interrupt
|
||||
DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt
|
||||
DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt
|
||||
DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt
|
||||
DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt
|
||||
DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt
|
||||
DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt
|
||||
DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt
|
||||
DCD PIT_IRQHandler ;PIT interrupt
|
||||
DCD ACMP1_IRQHandler ;ACMP interrupt
|
||||
DCD ACMP2_IRQHandler ;ACMP interrupt
|
||||
DCD ACMP3_IRQHandler ;ACMP interrupt
|
||||
DCD ACMP4_IRQHandler ;ACMP interrupt
|
||||
DCD Reserved143_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved144_IRQHandler ;Reserved interrupt
|
||||
DCD ENC1_IRQHandler ;ENC1 interrupt
|
||||
DCD ENC2_IRQHandler ;ENC2 interrupt
|
||||
DCD ENC3_IRQHandler ;ENC3 interrupt
|
||||
DCD ENC4_IRQHandler ;ENC4 interrupt
|
||||
DCD TMR1_IRQHandler ;TMR1 interrupt
|
||||
DCD TMR2_IRQHandler ;TMR2 interrupt
|
||||
DCD TMR3_IRQHandler ;TMR3 interrupt
|
||||
DCD TMR4_IRQHandler ;TMR4 interrupt
|
||||
DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt
|
||||
DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt
|
||||
DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt
|
||||
DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt
|
||||
DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt
|
||||
DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt
|
||||
DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt
|
||||
DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt
|
||||
DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt
|
||||
DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt
|
||||
DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt
|
||||
DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt
|
||||
DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt
|
||||
DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt
|
||||
DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt
|
||||
DCD DefaultISR ;168
|
||||
DCD DefaultISR ;169
|
||||
DCD DefaultISR ;170
|
||||
DCD DefaultISR ;171
|
||||
DCD DefaultISR ;172
|
||||
DCD DefaultISR ;173
|
||||
DCD DefaultISR ;174
|
||||
DCD DefaultISR ;175
|
||||
DCD DefaultISR ;176
|
||||
DCD DefaultISR ;177
|
||||
DCD DefaultISR ;178
|
||||
DCD DefaultISR ;179
|
||||
DCD DefaultISR ;180
|
||||
DCD DefaultISR ;181
|
||||
DCD DefaultISR ;182
|
||||
DCD DefaultISR ;183
|
||||
DCD DefaultISR ;184
|
||||
DCD DefaultISR ;185
|
||||
DCD DefaultISR ;186
|
||||
DCD DefaultISR ;187
|
||||
DCD DefaultISR ;188
|
||||
DCD DefaultISR ;189
|
||||
DCD DefaultISR ;190
|
||||
DCD DefaultISR ;191
|
||||
DCD DefaultISR ;192
|
||||
DCD DefaultISR ;193
|
||||
DCD DefaultISR ;194
|
||||
DCD DefaultISR ;195
|
||||
DCD DefaultISR ;196
|
||||
DCD DefaultISR ;197
|
||||
DCD DefaultISR ;198
|
||||
DCD DefaultISR ;199
|
||||
DCD DefaultISR ;200
|
||||
DCD DefaultISR ;201
|
||||
DCD DefaultISR ;202
|
||||
DCD DefaultISR ;203
|
||||
DCD DefaultISR ;204
|
||||
DCD DefaultISR ;205
|
||||
DCD DefaultISR ;206
|
||||
DCD DefaultISR ;207
|
||||
DCD DefaultISR ;208
|
||||
DCD DefaultISR ;209
|
||||
DCD DefaultISR ;210
|
||||
DCD DefaultISR ;211
|
||||
DCD DefaultISR ;212
|
||||
DCD DefaultISR ;213
|
||||
DCD DefaultISR ;214
|
||||
DCD DefaultISR ;215
|
||||
DCD DefaultISR ;216
|
||||
DCD DefaultISR ;217
|
||||
DCD DefaultISR ;218
|
||||
DCD DefaultISR ;219
|
||||
DCD DefaultISR ;220
|
||||
DCD DefaultISR ;221
|
||||
DCD DefaultISR ;222
|
||||
DCD DefaultISR ;223
|
||||
DCD DefaultISR ;224
|
||||
DCD DefaultISR ;225
|
||||
DCD DefaultISR ;226
|
||||
DCD DefaultISR ;227
|
||||
DCD DefaultISR ;228
|
||||
DCD DefaultISR ;229
|
||||
DCD DefaultISR ;230
|
||||
DCD DefaultISR ;231
|
||||
DCD DefaultISR ;232
|
||||
DCD DefaultISR ;233
|
||||
DCD DefaultISR ;234
|
||||
DCD DefaultISR ;235
|
||||
DCD DefaultISR ;236
|
||||
DCD DefaultISR ;237
|
||||
DCD DefaultISR ;238
|
||||
DCD DefaultISR ;239
|
||||
DCD DefaultISR ;240
|
||||
DCD DefaultISR ;241
|
||||
DCD DefaultISR ;242
|
||||
DCD DefaultISR ;243
|
||||
DCD DefaultISR ;244
|
||||
DCD DefaultISR ;245
|
||||
DCD DefaultISR ;246
|
||||
DCD DefaultISR ;247
|
||||
DCD DefaultISR ;248
|
||||
DCD DefaultISR ;249
|
||||
DCD DefaultISR ;250
|
||||
DCD DefaultISR ;251
|
||||
DCD DefaultISR ;252
|
||||
DCD DefaultISR ;253
|
||||
DCD DefaultISR ;254
|
||||
DCD 0xFFFFFFFF ; Reserved for user TRIM value
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
CPSID I ; Mask interrupts
|
||||
LDR R0, =0xE000ED08
|
||||
LDR R1, =__vector_table
|
||||
STR R1, [R0]
|
||||
LDR R2, [R1]
|
||||
MSR MSP, R2
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
CPSIE I ; Unmask interrupts
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DMA0_DMA16_IRQHandler
|
||||
PUBWEAK DMA0_DMA16_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA0_DMA16_IRQHandler
|
||||
LDR R0, =DMA0_DMA16_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA1_DMA17_IRQHandler
|
||||
PUBWEAK DMA1_DMA17_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA1_DMA17_IRQHandler
|
||||
LDR R0, =DMA1_DMA17_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA2_DMA18_IRQHandler
|
||||
PUBWEAK DMA2_DMA18_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA2_DMA18_IRQHandler
|
||||
LDR R0, =DMA2_DMA18_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA3_DMA19_IRQHandler
|
||||
PUBWEAK DMA3_DMA19_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA3_DMA19_IRQHandler
|
||||
LDR R0, =DMA3_DMA19_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA4_DMA20_IRQHandler
|
||||
PUBWEAK DMA4_DMA20_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA4_DMA20_IRQHandler
|
||||
LDR R0, =DMA4_DMA20_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA5_DMA21_IRQHandler
|
||||
PUBWEAK DMA5_DMA21_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA5_DMA21_IRQHandler
|
||||
LDR R0, =DMA5_DMA21_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA6_DMA22_IRQHandler
|
||||
PUBWEAK DMA6_DMA22_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA6_DMA22_IRQHandler
|
||||
LDR R0, =DMA6_DMA22_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA7_DMA23_IRQHandler
|
||||
PUBWEAK DMA7_DMA23_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA7_DMA23_IRQHandler
|
||||
LDR R0, =DMA7_DMA23_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA8_DMA24_IRQHandler
|
||||
PUBWEAK DMA8_DMA24_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA8_DMA24_IRQHandler
|
||||
LDR R0, =DMA8_DMA24_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA9_DMA25_IRQHandler
|
||||
PUBWEAK DMA9_DMA25_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA9_DMA25_IRQHandler
|
||||
LDR R0, =DMA9_DMA25_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA10_DMA26_IRQHandler
|
||||
PUBWEAK DMA10_DMA26_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA10_DMA26_IRQHandler
|
||||
LDR R0, =DMA10_DMA26_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA11_DMA27_IRQHandler
|
||||
PUBWEAK DMA11_DMA27_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA11_DMA27_IRQHandler
|
||||
LDR R0, =DMA11_DMA27_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA12_DMA28_IRQHandler
|
||||
PUBWEAK DMA12_DMA28_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA12_DMA28_IRQHandler
|
||||
LDR R0, =DMA12_DMA28_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA13_DMA29_IRQHandler
|
||||
PUBWEAK DMA13_DMA29_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA13_DMA29_IRQHandler
|
||||
LDR R0, =DMA13_DMA29_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA14_DMA30_IRQHandler
|
||||
PUBWEAK DMA14_DMA30_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA14_DMA30_IRQHandler
|
||||
LDR R0, =DMA14_DMA30_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA15_DMA31_IRQHandler
|
||||
PUBWEAK DMA15_DMA31_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA15_DMA31_IRQHandler
|
||||
LDR R0, =DMA15_DMA31_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK DMA_ERROR_IRQHandler
|
||||
PUBWEAK DMA_ERROR_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
DMA_ERROR_IRQHandler
|
||||
LDR R0, =DMA_ERROR_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK CTI0_ERROR_IRQHandler
|
||||
PUBWEAK CTI1_ERROR_IRQHandler
|
||||
PUBWEAK CORE_IRQHandler
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
PUBWEAK LPUART1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART1_IRQHandler
|
||||
LDR R0, =LPUART1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART2_IRQHandler
|
||||
PUBWEAK LPUART2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART2_IRQHandler
|
||||
LDR R0, =LPUART2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART3_IRQHandler
|
||||
PUBWEAK LPUART3_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART3_IRQHandler
|
||||
LDR R0, =LPUART3_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART4_IRQHandler
|
||||
PUBWEAK LPUART4_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART4_IRQHandler
|
||||
LDR R0, =LPUART4_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART5_IRQHandler
|
||||
PUBWEAK LPUART5_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART5_IRQHandler
|
||||
LDR R0, =LPUART5_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART6_IRQHandler
|
||||
PUBWEAK LPUART6_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART6_IRQHandler
|
||||
LDR R0, =LPUART6_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART7_IRQHandler
|
||||
PUBWEAK LPUART7_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART7_IRQHandler
|
||||
LDR R0, =LPUART7_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPUART8_IRQHandler
|
||||
PUBWEAK LPUART8_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPUART8_IRQHandler
|
||||
LDR R0, =LPUART8_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPI2C1_IRQHandler
|
||||
PUBWEAK LPI2C1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPI2C1_IRQHandler
|
||||
LDR R0, =LPI2C1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPI2C2_IRQHandler
|
||||
PUBWEAK LPI2C2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPI2C2_IRQHandler
|
||||
LDR R0, =LPI2C2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPI2C3_IRQHandler
|
||||
PUBWEAK LPI2C3_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPI2C3_IRQHandler
|
||||
LDR R0, =LPI2C3_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPI2C4_IRQHandler
|
||||
PUBWEAK LPI2C4_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPI2C4_IRQHandler
|
||||
LDR R0, =LPI2C4_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPSPI1_IRQHandler
|
||||
PUBWEAK LPSPI1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPSPI1_IRQHandler
|
||||
LDR R0, =LPSPI1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPSPI2_IRQHandler
|
||||
PUBWEAK LPSPI2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPSPI2_IRQHandler
|
||||
LDR R0, =LPSPI2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPSPI3_IRQHandler
|
||||
PUBWEAK LPSPI3_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPSPI3_IRQHandler
|
||||
LDR R0, =LPSPI3_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK LPSPI4_IRQHandler
|
||||
PUBWEAK LPSPI4_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
LPSPI4_IRQHandler
|
||||
LDR R0, =LPSPI4_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK CAN1_IRQHandler
|
||||
PUBWEAK CAN1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
CAN1_IRQHandler
|
||||
LDR R0, =CAN1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK CAN2_IRQHandler
|
||||
PUBWEAK CAN2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
CAN2_IRQHandler
|
||||
LDR R0, =CAN2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK FLEXRAM_IRQHandler
|
||||
PUBWEAK KPP_IRQHandler
|
||||
PUBWEAK TSC_DIG_IRQHandler
|
||||
PUBWEAK GPR_IRQ_IRQHandler
|
||||
PUBWEAK LCDIF_IRQHandler
|
||||
PUBWEAK CSI_IRQHandler
|
||||
PUBWEAK PXP_IRQHandler
|
||||
PUBWEAK WDOG2_IRQHandler
|
||||
PUBWEAK SNVS_HP_WRAPPER_IRQHandler
|
||||
PUBWEAK SNVS_HP_WRAPPER_TZ_IRQHandler
|
||||
PUBWEAK SNVS_LP_WRAPPER_IRQHandler
|
||||
PUBWEAK CSU_IRQHandler
|
||||
PUBWEAK DCP_IRQHandler
|
||||
PUBWEAK DCP_VMI_IRQHandler
|
||||
PUBWEAK Reserved68_IRQHandler
|
||||
PUBWEAK TRNG_IRQHandler
|
||||
PUBWEAK SJC_IRQHandler
|
||||
PUBWEAK BEE_IRQHandler
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
PUBWEAK SAI1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SAI1_IRQHandler
|
||||
LDR R0, =SAI1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SAI2_IRQHandler
|
||||
PUBWEAK SAI2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SAI2_IRQHandler
|
||||
LDR R0, =SAI2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SAI3_RX_IRQHandler
|
||||
PUBWEAK SAI3_RX_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SAI3_RX_IRQHandler
|
||||
LDR R0, =SAI3_RX_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SAI3_TX_IRQHandler
|
||||
PUBWEAK SAI3_TX_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SAI3_TX_IRQHandler
|
||||
LDR R0, =SAI3_TX_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SPDIF_IRQHandler
|
||||
PUBWEAK SPDIF_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
SPDIF_IRQHandler
|
||||
LDR R0, =SPDIF_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK PMU_EVENT_IRQHandler
|
||||
PUBWEAK Reserved78_IRQHandler
|
||||
PUBWEAK TEMP_LOW_HIGH_IRQHandler
|
||||
PUBWEAK TEMP_PANIC_IRQHandler
|
||||
PUBWEAK USB_PHY1_IRQHandler
|
||||
PUBWEAK USB_PHY2_IRQHandler
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
PUBWEAK ADC2_IRQHandler
|
||||
PUBWEAK DCDC_IRQHandler
|
||||
PUBWEAK Reserved86_IRQHandler
|
||||
PUBWEAK Reserved87_IRQHandler
|
||||
PUBWEAK GPIO1_INT0_IRQHandler
|
||||
PUBWEAK GPIO1_INT1_IRQHandler
|
||||
PUBWEAK GPIO1_INT2_IRQHandler
|
||||
PUBWEAK GPIO1_INT3_IRQHandler
|
||||
PUBWEAK GPIO1_INT4_IRQHandler
|
||||
PUBWEAK GPIO1_INT5_IRQHandler
|
||||
PUBWEAK GPIO1_INT6_IRQHandler
|
||||
PUBWEAK GPIO1_INT7_IRQHandler
|
||||
PUBWEAK GPIO1_Combined_0_15_IRQHandler
|
||||
PUBWEAK GPIO1_Combined_16_31_IRQHandler
|
||||
PUBWEAK GPIO2_Combined_0_15_IRQHandler
|
||||
PUBWEAK GPIO2_Combined_16_31_IRQHandler
|
||||
PUBWEAK GPIO3_Combined_0_15_IRQHandler
|
||||
PUBWEAK GPIO3_Combined_16_31_IRQHandler
|
||||
PUBWEAK GPIO4_Combined_0_15_IRQHandler
|
||||
PUBWEAK GPIO4_Combined_16_31_IRQHandler
|
||||
PUBWEAK GPIO5_Combined_0_15_IRQHandler
|
||||
PUBWEAK GPIO5_Combined_16_31_IRQHandler
|
||||
PUBWEAK FLEXIO1_IRQHandler
|
||||
PUBWEAK FLEXIO1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
FLEXIO1_IRQHandler
|
||||
LDR R0, =FLEXIO1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK FLEXIO2_IRQHandler
|
||||
PUBWEAK FLEXIO2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
FLEXIO2_IRQHandler
|
||||
LDR R0, =FLEXIO2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK WDOG1_IRQHandler
|
||||
PUBWEAK RTWDOG_IRQHandler
|
||||
PUBWEAK EWM_IRQHandler
|
||||
PUBWEAK CCM_1_IRQHandler
|
||||
PUBWEAK CCM_2_IRQHandler
|
||||
PUBWEAK GPC_IRQHandler
|
||||
PUBWEAK SRC_IRQHandler
|
||||
PUBWEAK Reserved115_IRQHandler
|
||||
PUBWEAK GPT1_IRQHandler
|
||||
PUBWEAK GPT2_IRQHandler
|
||||
PUBWEAK PWM1_0_IRQHandler
|
||||
PUBWEAK PWM1_1_IRQHandler
|
||||
PUBWEAK PWM1_2_IRQHandler
|
||||
PUBWEAK PWM1_3_IRQHandler
|
||||
PUBWEAK PWM1_FAULT_IRQHandler
|
||||
PUBWEAK Reserved123_IRQHandler
|
||||
PUBWEAK FLEXSPI_IRQHandler
|
||||
PUBWEAK FLEXSPI_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
FLEXSPI_IRQHandler
|
||||
LDR R0, =FLEXSPI_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK SEMC_IRQHandler
|
||||
PUBWEAK USDHC1_IRQHandler
|
||||
PUBWEAK USDHC1_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
USDHC1_IRQHandler
|
||||
LDR R0, =USDHC1_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK USDHC2_IRQHandler
|
||||
PUBWEAK USDHC2_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
USDHC2_IRQHandler
|
||||
LDR R0, =USDHC2_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK USB_OTG2_IRQHandler
|
||||
PUBWEAK USB_OTG1_IRQHandler
|
||||
PUBWEAK ENET_IRQHandler
|
||||
PUBWEAK ENET_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
ENET_IRQHandler
|
||||
LDR R0, =ENET_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK ENET_1588_Timer_IRQHandler
|
||||
PUBWEAK ENET_1588_Timer_DriverIRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
ENET_1588_Timer_IRQHandler
|
||||
LDR R0, =ENET_1588_Timer_DriverIRQHandler
|
||||
BX R0
|
||||
|
||||
PUBWEAK XBAR1_IRQ_0_1_IRQHandler
|
||||
PUBWEAK XBAR1_IRQ_2_3_IRQHandler
|
||||
PUBWEAK ADC_ETC_IRQ0_IRQHandler
|
||||
PUBWEAK ADC_ETC_IRQ1_IRQHandler
|
||||
PUBWEAK ADC_ETC_IRQ2_IRQHandler
|
||||
PUBWEAK ADC_ETC_ERROR_IRQ_IRQHandler
|
||||
PUBWEAK PIT_IRQHandler
|
||||
PUBWEAK ACMP1_IRQHandler
|
||||
PUBWEAK ACMP2_IRQHandler
|
||||
PUBWEAK ACMP3_IRQHandler
|
||||
PUBWEAK ACMP4_IRQHandler
|
||||
PUBWEAK Reserved143_IRQHandler
|
||||
PUBWEAK Reserved144_IRQHandler
|
||||
PUBWEAK ENC1_IRQHandler
|
||||
PUBWEAK ENC2_IRQHandler
|
||||
PUBWEAK ENC3_IRQHandler
|
||||
PUBWEAK ENC4_IRQHandler
|
||||
PUBWEAK TMR1_IRQHandler
|
||||
PUBWEAK TMR2_IRQHandler
|
||||
PUBWEAK TMR3_IRQHandler
|
||||
PUBWEAK TMR4_IRQHandler
|
||||
PUBWEAK PWM2_0_IRQHandler
|
||||
PUBWEAK PWM2_1_IRQHandler
|
||||
PUBWEAK PWM2_2_IRQHandler
|
||||
PUBWEAK PWM2_3_IRQHandler
|
||||
PUBWEAK PWM2_FAULT_IRQHandler
|
||||
PUBWEAK PWM3_0_IRQHandler
|
||||
PUBWEAK PWM3_1_IRQHandler
|
||||
PUBWEAK PWM3_2_IRQHandler
|
||||
PUBWEAK PWM3_3_IRQHandler
|
||||
PUBWEAK PWM3_FAULT_IRQHandler
|
||||
PUBWEAK PWM4_0_IRQHandler
|
||||
PUBWEAK PWM4_1_IRQHandler
|
||||
PUBWEAK PWM4_2_IRQHandler
|
||||
PUBWEAK PWM4_3_IRQHandler
|
||||
PUBWEAK PWM4_FAULT_IRQHandler
|
||||
PUBWEAK DefaultISR
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA0_DMA16_DriverIRQHandler
|
||||
DMA1_DMA17_DriverIRQHandler
|
||||
DMA2_DMA18_DriverIRQHandler
|
||||
DMA3_DMA19_DriverIRQHandler
|
||||
DMA4_DMA20_DriverIRQHandler
|
||||
DMA5_DMA21_DriverIRQHandler
|
||||
DMA6_DMA22_DriverIRQHandler
|
||||
DMA7_DMA23_DriverIRQHandler
|
||||
DMA8_DMA24_DriverIRQHandler
|
||||
DMA9_DMA25_DriverIRQHandler
|
||||
DMA10_DMA26_DriverIRQHandler
|
||||
DMA11_DMA27_DriverIRQHandler
|
||||
DMA12_DMA28_DriverIRQHandler
|
||||
DMA13_DMA29_DriverIRQHandler
|
||||
DMA14_DMA30_DriverIRQHandler
|
||||
DMA15_DMA31_DriverIRQHandler
|
||||
DMA_ERROR_DriverIRQHandler
|
||||
CTI0_ERROR_IRQHandler
|
||||
CTI1_ERROR_IRQHandler
|
||||
CORE_IRQHandler
|
||||
LPUART1_DriverIRQHandler
|
||||
LPUART2_DriverIRQHandler
|
||||
LPUART3_DriverIRQHandler
|
||||
LPUART4_DriverIRQHandler
|
||||
LPUART5_DriverIRQHandler
|
||||
LPUART6_DriverIRQHandler
|
||||
LPUART7_DriverIRQHandler
|
||||
LPUART8_DriverIRQHandler
|
||||
LPI2C1_DriverIRQHandler
|
||||
LPI2C2_DriverIRQHandler
|
||||
LPI2C3_DriverIRQHandler
|
||||
LPI2C4_DriverIRQHandler
|
||||
LPSPI1_DriverIRQHandler
|
||||
LPSPI2_DriverIRQHandler
|
||||
LPSPI3_DriverIRQHandler
|
||||
LPSPI4_DriverIRQHandler
|
||||
CAN1_DriverIRQHandler
|
||||
CAN2_DriverIRQHandler
|
||||
FLEXRAM_IRQHandler
|
||||
KPP_IRQHandler
|
||||
TSC_DIG_IRQHandler
|
||||
GPR_IRQ_IRQHandler
|
||||
LCDIF_IRQHandler
|
||||
CSI_IRQHandler
|
||||
PXP_IRQHandler
|
||||
WDOG2_IRQHandler
|
||||
SNVS_HP_WRAPPER_IRQHandler
|
||||
SNVS_HP_WRAPPER_TZ_IRQHandler
|
||||
SNVS_LP_WRAPPER_IRQHandler
|
||||
CSU_IRQHandler
|
||||
DCP_IRQHandler
|
||||
DCP_VMI_IRQHandler
|
||||
Reserved68_IRQHandler
|
||||
TRNG_IRQHandler
|
||||
SJC_IRQHandler
|
||||
BEE_IRQHandler
|
||||
SAI1_DriverIRQHandler
|
||||
SAI2_DriverIRQHandler
|
||||
SAI3_RX_DriverIRQHandler
|
||||
SAI3_TX_DriverIRQHandler
|
||||
SPDIF_DriverIRQHandler
|
||||
PMU_EVENT_IRQHandler
|
||||
Reserved78_IRQHandler
|
||||
TEMP_LOW_HIGH_IRQHandler
|
||||
TEMP_PANIC_IRQHandler
|
||||
USB_PHY1_IRQHandler
|
||||
USB_PHY2_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
DCDC_IRQHandler
|
||||
Reserved86_IRQHandler
|
||||
Reserved87_IRQHandler
|
||||
GPIO1_INT0_IRQHandler
|
||||
GPIO1_INT1_IRQHandler
|
||||
GPIO1_INT2_IRQHandler
|
||||
GPIO1_INT3_IRQHandler
|
||||
GPIO1_INT4_IRQHandler
|
||||
GPIO1_INT5_IRQHandler
|
||||
GPIO1_INT6_IRQHandler
|
||||
GPIO1_INT7_IRQHandler
|
||||
GPIO1_Combined_0_15_IRQHandler
|
||||
GPIO1_Combined_16_31_IRQHandler
|
||||
GPIO2_Combined_0_15_IRQHandler
|
||||
GPIO2_Combined_16_31_IRQHandler
|
||||
GPIO3_Combined_0_15_IRQHandler
|
||||
GPIO3_Combined_16_31_IRQHandler
|
||||
GPIO4_Combined_0_15_IRQHandler
|
||||
GPIO4_Combined_16_31_IRQHandler
|
||||
GPIO5_Combined_0_15_IRQHandler
|
||||
GPIO5_Combined_16_31_IRQHandler
|
||||
FLEXIO1_DriverIRQHandler
|
||||
FLEXIO2_DriverIRQHandler
|
||||
WDOG1_IRQHandler
|
||||
RTWDOG_IRQHandler
|
||||
EWM_IRQHandler
|
||||
CCM_1_IRQHandler
|
||||
CCM_2_IRQHandler
|
||||
GPC_IRQHandler
|
||||
SRC_IRQHandler
|
||||
Reserved115_IRQHandler
|
||||
GPT1_IRQHandler
|
||||
GPT2_IRQHandler
|
||||
PWM1_0_IRQHandler
|
||||
PWM1_1_IRQHandler
|
||||
PWM1_2_IRQHandler
|
||||
PWM1_3_IRQHandler
|
||||
PWM1_FAULT_IRQHandler
|
||||
Reserved123_IRQHandler
|
||||
FLEXSPI_DriverIRQHandler
|
||||
SEMC_IRQHandler
|
||||
USDHC1_DriverIRQHandler
|
||||
USDHC2_DriverIRQHandler
|
||||
USB_OTG2_IRQHandler
|
||||
USB_OTG1_IRQHandler
|
||||
ENET_DriverIRQHandler
|
||||
ENET_1588_Timer_DriverIRQHandler
|
||||
XBAR1_IRQ_0_1_IRQHandler
|
||||
XBAR1_IRQ_2_3_IRQHandler
|
||||
ADC_ETC_IRQ0_IRQHandler
|
||||
ADC_ETC_IRQ1_IRQHandler
|
||||
ADC_ETC_IRQ2_IRQHandler
|
||||
ADC_ETC_ERROR_IRQ_IRQHandler
|
||||
PIT_IRQHandler
|
||||
ACMP1_IRQHandler
|
||||
ACMP2_IRQHandler
|
||||
ACMP3_IRQHandler
|
||||
ACMP4_IRQHandler
|
||||
Reserved143_IRQHandler
|
||||
Reserved144_IRQHandler
|
||||
ENC1_IRQHandler
|
||||
ENC2_IRQHandler
|
||||
ENC3_IRQHandler
|
||||
ENC4_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
TMR4_IRQHandler
|
||||
PWM2_0_IRQHandler
|
||||
PWM2_1_IRQHandler
|
||||
PWM2_2_IRQHandler
|
||||
PWM2_3_IRQHandler
|
||||
PWM2_FAULT_IRQHandler
|
||||
PWM3_0_IRQHandler
|
||||
PWM3_1_IRQHandler
|
||||
PWM3_2_IRQHandler
|
||||
PWM3_3_IRQHandler
|
||||
PWM3_FAULT_IRQHandler
|
||||
PWM4_0_IRQHandler
|
||||
PWM4_1_IRQHandler
|
||||
PWM4_2_IRQHandler
|
||||
PWM4_3_IRQHandler
|
||||
PWM4_FAULT_IRQHandler
|
||||
DefaultISR
|
||||
B DefaultISR
|
||||
|
||||
END
|
||||
@@ -0,0 +1,13 @@
|
||||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC11U24 specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of ARM Limited nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#else
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#endif
|
||||
|
||||
/* Symbols defined by the linker script */
|
||||
#define NVIC_NUM_VECTORS (16 + 160) // CORE + MCU Peripherals
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \
|
||||
defined(CPU_MIMXRT1052DVL6B))
|
||||
|
||||
#define MIMXRT1052_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MIMXRT1052.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "MIMXRT1052_features.h"
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,236 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compilers: Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Keil ARM C/C++ Compiler
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
|
||||
** Version: rev. 1.2, 2018-11-27
|
||||
** Build: b190329
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2017-01-10)
|
||||
** Initial version.
|
||||
** - rev. 1.0 (2018-09-21)
|
||||
** Update interrupt vector table and dma request source.
|
||||
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
|
||||
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
|
||||
** - rev. 1.1 (2018-11-16)
|
||||
** Update header files to align with IMXRT1050RM Rev.1.
|
||||
** - rev. 1.2 (2018-11-27)
|
||||
** Update header files to align with IMXRT1050RM Rev.2.1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MIMXRT1052
|
||||
* @version 1.2
|
||||
* @date 2018-11-27
|
||||
* @brief Device specific configuration file for MIMXRT1052 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
|
||||
#if defined(__MCUXPRESSO)
|
||||
extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
|
||||
SCB->VTOR = (uint32_t)g_pfnVectors;
|
||||
#endif
|
||||
|
||||
/* Disable Watchdog Power Down Counter */
|
||||
WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
|
||||
WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
|
||||
|
||||
/* Watchdog disable */
|
||||
|
||||
#if (DISABLE_WDOG)
|
||||
if (WDOG1->WCR & WDOG_WCR_WDE_MASK)
|
||||
{
|
||||
WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
|
||||
}
|
||||
if (WDOG2->WCR & WDOG_WCR_WDE_MASK)
|
||||
{
|
||||
WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
|
||||
}
|
||||
RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
|
||||
RTWDOG->TOVAL = 0xFFFF;
|
||||
RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
/* Disable Systick which might be enabled by bootrom */
|
||||
if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/* Enable instruction and data caches */
|
||||
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
|
||||
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
|
||||
SCB_EnableICache();
|
||||
}
|
||||
#endif
|
||||
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
|
||||
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
#endif
|
||||
|
||||
SystemInitHook();
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
uint32_t freq;
|
||||
uint32_t PLL1MainClock;
|
||||
uint32_t PLL2MainClock;
|
||||
|
||||
/* Periph_clk2_clk ---> Periph_clk */
|
||||
if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
|
||||
{
|
||||
switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
|
||||
{
|
||||
/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
|
||||
if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
|
||||
{
|
||||
freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
|
||||
}
|
||||
break;
|
||||
|
||||
/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
|
||||
freq = CPU_XTAL_CLK_HZ;
|
||||
break;
|
||||
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
|
||||
freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
break;
|
||||
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
|
||||
}
|
||||
/* Pre_Periph_clk ---> Periph_clk */
|
||||
else
|
||||
{
|
||||
/* check if pll is bypassed */
|
||||
if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
|
||||
{
|
||||
PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
|
||||
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
|
||||
}
|
||||
|
||||
/* check if pll is bypassed */
|
||||
if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
|
||||
{
|
||||
PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
|
||||
}
|
||||
PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
|
||||
|
||||
|
||||
switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
|
||||
{
|
||||
/* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
|
||||
freq = PLL2MainClock;
|
||||
break;
|
||||
|
||||
/* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
|
||||
freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
|
||||
break;
|
||||
|
||||
/* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
|
||||
freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
|
||||
break;
|
||||
|
||||
/* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
|
||||
freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
|
||||
break;
|
||||
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
|
||||
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInitHook()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||
/* Void implementation of the weak function. */
|
||||
}
|
||||
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compilers: Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Keil ARM C/C++ Compiler
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
|
||||
** Version: rev. 1.2, 2018-11-27
|
||||
** Build: b181205
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2017-01-10)
|
||||
** Initial version.
|
||||
** - rev. 1.0 (2018-09-21)
|
||||
** Update interrupt vector table and dma request source.
|
||||
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
|
||||
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
|
||||
** - rev. 1.1 (2018-11-16)
|
||||
** Update header files to align with IMXRT1050RM Rev.1.
|
||||
** - rev. 1.2 (2018-11-27)
|
||||
** Update header files to align with IMXRT1050RM Rev.2.1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MIMXRT1052
|
||||
* @version 1.2
|
||||
* @date 2018-11-27
|
||||
* @brief Device specific configuration file for MIMXRT1052 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MIMXRT1052_H_
|
||||
#define _SYSTEM_MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
|
||||
#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
|
||||
/* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
* @brief SystemInit function hook.
|
||||
*
|
||||
* This weak function allows to call specific initialization code during the
|
||||
* SystemInit() execution.This can be used when an application specific code needs
|
||||
* to be called as close to the reset entry as possible (for example the Multicore
|
||||
* Manager MCMGR_EarlyInit() function call).
|
||||
* NOTE: No global r/w variables can be used in this hook function because the
|
||||
* initialization of these variables happens after this function.
|
||||
*/
|
||||
void SystemInitHook (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MIMXRT1052_H_ */
|
||||
Reference in New Issue
Block a user