Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
578
targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c
Normal file
578
targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c
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@@ -0,0 +1,578 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "mbed_assert.h"
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#include <math.h>
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#include "spi_api.h"
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#include "cmsis.h"
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#include "PeripheralPins.h"
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#include "mbed_error.h"
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#include "RZ_A1_Init.h"
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#include "mbed_drv_cfg.h"
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static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
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static inline void spi_disable(spi_t *obj);
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static inline void spi_enable(spi_t *obj);
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static inline int spi_readable(spi_t *obj);
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static inline void spi_write(spi_t *obj, int value);
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static inline int spi_read(spi_t *obj);
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void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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// determine the SPI to use
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volatile uint8_t dummy;
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uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
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uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
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uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
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uint32_t spi = pinmap_merge(spi_data, spi_cntl);
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MBED_ASSERT((int)spi != NC);
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obj->spi.spi = (struct st_rspi *)RSPI[spi];
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obj->spi.index = spi;
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// enable power and clocking
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CPGSTBCR10 &= ~(0x80 >> spi);
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dummy = CPGSTBCR10;
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(void)dummy;
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obj->spi.spi->SPCR = 0x00; // CTRL to 0
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obj->spi.spi->SPSCR = 0x00; // no sequential operation
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obj->spi.spi->SSLP = 0x00; // SSL 'L' active
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obj->spi.spi->SPDCR = 0x20; // byte access
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obj->spi.spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
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obj->spi.spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
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obj->spi.spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
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obj->spi.spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
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obj->spi.spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
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obj->spi.spi->SPBFCR = 0x30; // and reset buffer
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// pin out the spi pins
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pinmap_pinout(mosi, PinMap_SPI_MOSI);
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pinmap_pinout(miso, PinMap_SPI_MISO);
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pinmap_pinout(sclk, PinMap_SPI_SCLK);
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if ((int)ssel != NC) {
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pinmap_pinout(ssel, PinMap_SPI_SSEL);
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}
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}
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void spi_free(spi_t *obj) {}
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void spi_format(spi_t *obj, int bits, int mode, int slave) {
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int DSS; // DSS (data select size)
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int polarity = (mode & 0x2) ? 1 : 0;
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int phase = (mode & 0x1) ? 1 : 0;
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uint16_t tmp = 0;
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uint16_t mask = 0xf03;
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uint16_t wk_spcmd0;
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uint8_t splw;
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switch (mode) {
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case 0:
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case 1:
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case 2:
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case 3:
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// Do Nothing
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break;
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default:
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error("SPI format error");
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return;
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}
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switch (bits) {
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case 8:
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DSS = 0x7;
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splw = 0x20;
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break;
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case 16:
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DSS = 0xf;
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splw = 0x40;
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break;
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case 32:
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DSS = 0x2;
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splw = 0x60;
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break;
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default:
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error("SPI module don't support other than 8/16/32bits");
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return;
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}
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tmp |= phase;
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tmp |= (polarity << 1);
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tmp |= (DSS << 8);
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obj->spi.bits = bits;
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spi_disable(obj);
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wk_spcmd0 = obj->spi.spi->SPCMD0;
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wk_spcmd0 &= ~mask;
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wk_spcmd0 |= (mask & tmp);
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obj->spi.spi->SPCMD0 = wk_spcmd0;
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obj->spi.spi->SPDCR = splw;
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if (slave) {
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obj->spi.spi->SPCR &=~(1 << 3); // MSTR to 0
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} else {
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obj->spi.spi->SPCR |= (1 << 3); // MSTR to 1
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}
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spi_enable(obj);
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}
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void spi_frequency(spi_t *obj, int hz) {
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uint32_t pclk_base;
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uint32_t div;
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uint32_t brdv = 0;
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uint32_t hz_max;
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uint32_t hz_min;
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uint16_t mask = 0x000c;
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uint16_t wk_spcmd0;
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/* set PCLK */
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if (RZ_A1_IsClockMode0() == false) {
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pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
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} else {
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pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
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}
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hz_min = pclk_base / 2 / 256 / 8;
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hz_max = pclk_base / 2;
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if ((uint32_t)hz < hz_min) {
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hz = hz_min;
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}
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if ((uint32_t)hz > hz_max) {
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hz = hz_max;
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}
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div = (pclk_base / hz / 2);
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while (div > 256) {
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div >>= 1;
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brdv++;
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}
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div -= 1;
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brdv = (brdv << 2);
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spi_disable(obj);
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obj->spi.spi->SPBR = div;
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wk_spcmd0 = obj->spi.spi->SPCMD0;
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wk_spcmd0 &= ~mask;
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wk_spcmd0 |= (mask & brdv);
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obj->spi.spi->SPCMD0 = wk_spcmd0;
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spi_enable(obj);
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}
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static inline void spi_disable(spi_t *obj) {
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obj->spi.spi->SPCR &= ~(1 << 6); // SPE to 0
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}
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static inline void spi_enable(spi_t *obj) {
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obj->spi.spi->SPCR |= (1 << 6); // SPE to 1
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}
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static inline int spi_readable(spi_t *obj) {
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return obj->spi.spi->SPSR & (1 << 7); // SPRF
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}
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static inline int spi_tend(spi_t *obj) {
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return obj->spi.spi->SPSR & (1 << 6); // TEND
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}
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static inline void spi_write(spi_t *obj, int value) {
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if (obj->spi.bits == 8) {
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obj->spi.spi->SPDR.UINT8[0] = (uint8_t)value;
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} else if (obj->spi.bits == 16) {
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obj->spi.spi->SPDR.UINT16[0] = (uint16_t)value;
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} else {
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obj->spi.spi->SPDR.UINT32 = (uint32_t)value;
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}
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}
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static inline int spi_read(spi_t *obj) {
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int read_data;
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if (obj->spi.bits == 8) {
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read_data = obj->spi.spi->SPDR.UINT8[0];
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} else if (obj->spi.bits == 16) {
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read_data = obj->spi.spi->SPDR.UINT16[0];
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} else {
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read_data = obj->spi.spi->SPDR.UINT32;
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}
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return read_data;
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}
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int spi_master_write(spi_t *obj, int value) {
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spi_write(obj, value);
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while(!spi_tend(obj));
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return spi_read(obj);
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}
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int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
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char *rx_buffer, int rx_length, char write_fill) {
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int total = (tx_length > rx_length) ? tx_length : rx_length;
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for (int i = 0; i < total; i++) {
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char out = (i < tx_length) ? tx_buffer[i] : write_fill;
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char in = spi_master_write(obj, out);
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if (i < rx_length) {
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rx_buffer[i] = in;
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}
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}
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return total;
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}
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int spi_slave_receive(spi_t *obj) {
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return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
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}
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int spi_slave_read(spi_t *obj) {
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return spi_read(obj);
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}
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void spi_slave_write(spi_t *obj, int value) {
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spi_write(obj, value);
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}
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int spi_busy(spi_t *obj) {
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return 0;
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}
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const PinMap *spi_master_mosi_pinmap()
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{
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return PinMap_SPI_MOSI;
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}
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const PinMap *spi_master_miso_pinmap()
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{
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return PinMap_SPI_MISO;
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}
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const PinMap *spi_master_clk_pinmap()
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{
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return PinMap_SPI_SCLK;
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}
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const PinMap *spi_master_cs_pinmap()
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{
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return PinMap_SPI_SSEL;
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}
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const PinMap *spi_slave_mosi_pinmap()
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{
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return PinMap_SPI_MOSI;
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}
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const PinMap *spi_slave_miso_pinmap()
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{
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return PinMap_SPI_MISO;
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}
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const PinMap *spi_slave_clk_pinmap()
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{
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return PinMap_SPI_SCLK;
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}
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const PinMap *spi_slave_cs_pinmap()
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{
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return PinMap_SPI_SSEL;
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}
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#if DEVICE_SPI_ASYNCH
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#define SPI_NUM 5
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#define IRQ_NUM 2
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static void spi_irqs_set(spi_t *obj, uint32_t enable);
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static void spi_async_write(spi_t *obj);
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static void spi_async_read(spi_t *obj);
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static void spi0_rx_irq(void);
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static void spi0_er_irq(void);
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static void spi1_rx_irq(void);
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static void spi1_er_irq(void);
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static void spi2_rx_irq(void);
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static void spi2_er_irq(void);
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static void spi3_rx_irq(void);
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static void spi3_er_irq(void);
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static void spi4_rx_irq(void);
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static void spi4_er_irq(void);
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static const IRQn_Type irq_set_tbl[SPI_NUM][IRQ_NUM] = {
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{RSPISPRI0_IRQn, RSPISPEI0_IRQn},
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{RSPISPRI1_IRQn, RSPISPEI1_IRQn},
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{RSPISPRI2_IRQn, RSPISPEI2_IRQn},
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{RSPISPRI3_IRQn, RSPISPEI3_IRQn},
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{RSPISPRI4_IRQn, RSPISPEI4_IRQn},
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};
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static const IRQHandler hander_set_tbl[SPI_NUM][IRQ_NUM] = {
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{spi0_rx_irq, spi0_er_irq},
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{spi1_rx_irq, spi1_er_irq},
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{spi2_rx_irq, spi2_er_irq},
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{spi3_rx_irq, spi3_er_irq},
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{spi4_rx_irq, spi4_er_irq},
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};
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struct spi_global_data_s {
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spi_t *async_obj;
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uint32_t async_callback, event, wanted_events;
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};
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static struct spi_global_data_s spi_data[SPI_NUM];
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static void spi_rx_irq(IRQn_Type irq_num, uint32_t index)
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{
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spi_t *obj = spi_data[index].async_obj;
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if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
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spi_async_read(obj);
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} else {
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if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
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spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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}
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spi_irqs_set(obj, 0);
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spi_data[obj->spi.index].async_obj = NULL;
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((void (*)())spi_data[obj->spi.index].async_callback)();
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return;
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}
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spi_read(obj);
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}
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if (obj->tx_buff.buffer) {
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if (obj->tx_buff.pos == obj->tx_buff.length) {
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spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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}
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spi_irqs_set(obj, 0);
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spi_data[obj->spi.index].async_obj = NULL;
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((void (*)())spi_data[obj->spi.index].async_callback)();
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} else {
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spi_async_write(obj);
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}
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} else {
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if (obj->rx_buff.pos == obj->rx_buff.length) {
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spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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}
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spi_irqs_set(obj, 0);
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spi_data[obj->spi.index].async_obj = NULL;
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((void (*)())spi_data[obj->spi.index].async_callback)();
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} else {
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spi_async_write(obj);
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}
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}
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}
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static void spi_err_irq(IRQn_Type irq_num, uint32_t index)
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{
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spi_t *obj = spi_data[index].async_obj;
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spi_abort_asynch(obj);
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spi_data[index].event = SPI_EVENT_ERROR;
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if (spi_data[index].wanted_events & SPI_EVENT_ERROR) {
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((void (*)())spi_data[index].async_callback)();
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}
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}
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static void spi0_rx_irq(void) {
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spi_rx_irq(RSPISPRI0_IRQn, 0);
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}
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static void spi0_er_irq(void) {
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spi_err_irq(RSPISPEI0_IRQn, 0);
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}
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static void spi1_rx_irq(void) {
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spi_rx_irq(RSPISPRI1_IRQn, 1);
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}
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static void spi1_er_irq(void) {
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spi_err_irq(RSPISPEI1_IRQn, 1);
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}
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static void spi2_rx_irq(void) {
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spi_rx_irq(RSPISPRI2_IRQn, 2);
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}
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static void spi2_er_irq(void) {
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spi_err_irq(RSPISPEI2_IRQn, 2);
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}
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static void spi3_rx_irq(void) {
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spi_rx_irq(RSPISPRI3_IRQn, 3);
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}
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static void spi3_er_irq(void) {
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spi_err_irq(RSPISPEI3_IRQn, 3);
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}
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static void spi4_rx_irq(void) {
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spi_rx_irq(RSPISPRI4_IRQn, 4);
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}
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static void spi4_er_irq(void) {
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spi_err_irq(RSPISPEI4_IRQn, 4);
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}
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static void spi_irqs_set(spi_t *obj, uint32_t enable)
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{
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int i;
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const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index];
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const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index];
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for (i = 0; i < IRQ_NUM; ++i) {
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if (enable) {
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InterruptHandlerRegister(irqTable[i], handlerTable[i]);
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GIC_SetPriority(irqTable[i], 5);
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GIC_SetConfiguration(irqTable[i], 1);
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GIC_EnableIRQ(irqTable[i]);
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} else {
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GIC_DisableIRQ(irqTable[i]);
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}
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}
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if (enable) {
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obj->spi.spi->SPCR |= (1 << 4) | (1 << 7);
|
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} else {
|
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obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7));
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}
|
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}
|
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static void spi_async_write(spi_t *obj)
|
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{
|
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uint8_t **width8;
|
||||
uint16_t **width16;
|
||||
uint32_t **width32;
|
||||
|
||||
if (obj->tx_buff.buffer) {
|
||||
switch (obj->tx_buff.width) {
|
||||
case 8:
|
||||
width8 = (uint8_t **)&obj->tx_buff.buffer;
|
||||
spi_write(obj, **width8);
|
||||
++*width8;
|
||||
obj->tx_buff.pos += sizeof(uint8_t);
|
||||
break;
|
||||
|
||||
case 16:
|
||||
width16 = (uint16_t **)&obj->tx_buff.buffer;
|
||||
spi_write(obj, **width16);
|
||||
++*width16;
|
||||
obj->tx_buff.pos += sizeof(uint16_t);
|
||||
break;
|
||||
|
||||
case 32:
|
||||
width32 = (uint32_t **)&obj->tx_buff.buffer;
|
||||
spi_write(obj, **width32);
|
||||
++*width32;
|
||||
obj->tx_buff.pos += sizeof(uint32_t);
|
||||
break;
|
||||
|
||||
default:
|
||||
MBED_ASSERT(0);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
spi_write(obj, SPI_FILL_WORD);
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_async_read(spi_t *obj)
|
||||
{
|
||||
uint8_t **width8;
|
||||
uint16_t **width16;
|
||||
uint32_t **width32;
|
||||
|
||||
switch (obj->rx_buff.width) {
|
||||
case 8:
|
||||
width8 = (uint8_t **)&obj->rx_buff.buffer;
|
||||
**width8 = spi_read(obj);
|
||||
++*width8;
|
||||
obj->rx_buff.pos += sizeof(uint8_t);
|
||||
break;
|
||||
|
||||
case 16:
|
||||
width16 = (uint16_t **)&obj->rx_buff.buffer;
|
||||
**width16 = spi_read(obj);
|
||||
++*width16;
|
||||
obj->rx_buff.pos += sizeof(uint16_t);
|
||||
break;
|
||||
|
||||
case 32:
|
||||
width32 = (uint32_t **)&obj->rx_buff.buffer;
|
||||
**width32 = spi_read(obj);
|
||||
++*width32;
|
||||
obj->rx_buff.pos += sizeof(uint32_t);
|
||||
break;
|
||||
|
||||
default:
|
||||
MBED_ASSERT(0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* ASYNCHRONOUS HAL
|
||||
******************************************************************************/
|
||||
|
||||
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
||||
{
|
||||
int i;
|
||||
MBED_ASSERT(obj);
|
||||
MBED_ASSERT(tx || rx);
|
||||
MBED_ASSERT(tx && ! rx ? tx_length : 1);
|
||||
MBED_ASSERT(rx && ! tx ? rx_length : 1);
|
||||
MBED_ASSERT(obj->spi.spi->SPCR & (1 << 3)); /* Slave mode */
|
||||
MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32);
|
||||
|
||||
if (tx_length) {
|
||||
obj->tx_buff.buffer = (void *)tx;
|
||||
} else {
|
||||
obj->tx_buff.buffer = NULL;
|
||||
}
|
||||
obj->tx_buff.length = tx_length * bit_width / 8;
|
||||
obj->tx_buff.pos = 0;
|
||||
obj->tx_buff.width = bit_width;
|
||||
if (rx_length) {
|
||||
obj->rx_buff.buffer = rx;
|
||||
} else {
|
||||
obj->rx_buff.buffer = NULL;
|
||||
}
|
||||
obj->rx_buff.length = rx_length * bit_width / 8;
|
||||
obj->rx_buff.pos = 0;
|
||||
obj->rx_buff.width = bit_width;
|
||||
for (i = 0; i < (int)obj->rx_buff.length; i++) {
|
||||
((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD;
|
||||
}
|
||||
|
||||
spi_data[obj->spi.index].async_callback = handler;
|
||||
spi_data[obj->spi.index].async_obj = obj;
|
||||
spi_data[obj->spi.index].event = 0;
|
||||
spi_data[obj->spi.index].wanted_events = event;
|
||||
|
||||
spi_irqs_set(obj, 1);
|
||||
|
||||
spi_async_write(obj);
|
||||
}
|
||||
|
||||
uint32_t spi_irq_handler_asynch(spi_t *obj)
|
||||
{
|
||||
return spi_data[obj->spi.index].event;
|
||||
}
|
||||
|
||||
uint8_t spi_active(spi_t *obj)
|
||||
{
|
||||
return spi_data[obj->spi.index].async_obj != NULL;
|
||||
}
|
||||
|
||||
void spi_abort_asynch(spi_t *obj)
|
||||
{
|
||||
spi_disable(obj);
|
||||
spi_irqs_set(obj, 0);
|
||||
spi_data[obj->spi.index].async_obj = NULL;
|
||||
spi_enable(obj);
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user