Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
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;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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;* File Name : startup_stm32f410rx.s
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;* Author : MCD Application Team
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;* Description : STM32F410Rx devices vector table for MDK-ARM_STD toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;*******************************************************************************
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;
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;*******************************************************************************
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_IRQHandler ; TIM1 Update
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD 0 ; Reserved
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TIM5_IRQHandler ; TIM5
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
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DCD 0 ; Reserved
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; RNG
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DCD FPU_IRQHandler ; FPU
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI5_IRQHandler ; SPI5
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
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DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
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DCD LPTIM1_IRQHandler ; LP TIM1
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Stream0_IRQHandler [WEAK]
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EXPORT DMA1_Stream1_IRQHandler [WEAK]
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EXPORT DMA1_Stream2_IRQHandler [WEAK]
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EXPORT DMA1_Stream3_IRQHandler [WEAK]
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EXPORT DMA1_Stream4_IRQHandler [WEAK]
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EXPORT DMA1_Stream5_IRQHandler [WEAK]
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EXPORT DMA1_Stream6_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
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EXPORT TIM1_UP_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT DMA1_Stream7_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT TIM6_DAC_IRQHandler [WEAK]
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EXPORT DMA2_Stream0_IRQHandler [WEAK]
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EXPORT DMA2_Stream1_IRQHandler [WEAK]
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EXPORT DMA2_Stream2_IRQHandler [WEAK]
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EXPORT DMA2_Stream3_IRQHandler [WEAK]
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EXPORT DMA2_Stream4_IRQHandler [WEAK]
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EXPORT DMA2_Stream4_IRQHandler [WEAK]
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EXPORT DMA2_Stream5_IRQHandler [WEAK]
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EXPORT DMA2_Stream6_IRQHandler [WEAK]
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EXPORT DMA2_Stream7_IRQHandler [WEAK]
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EXPORT USART6_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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EXPORT SPI5_IRQHandler [WEAK]
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EXPORT FMPI2C1_EV_IRQHandler [WEAK]
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EXPORT FMPI2C1_ER_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_IRQHandler
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TAMP_STAMP_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Stream0_IRQHandler
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DMA1_Stream1_IRQHandler
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DMA1_Stream2_IRQHandler
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DMA1_Stream3_IRQHandler
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DMA1_Stream4_IRQHandler
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DMA1_Stream5_IRQHandler
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DMA1_Stream6_IRQHandler
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ADC_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_TIM9_IRQHandler
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TIM1_UP_IRQHandler
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TIM1_TRG_COM_TIM11_IRQHandler
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TIM1_CC_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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DMA1_Stream7_IRQHandler
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TIM5_IRQHandler
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TIM6_DAC_IRQHandler
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DMA2_Stream0_IRQHandler
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DMA2_Stream1_IRQHandler
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DMA2_Stream2_IRQHandler
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DMA2_Stream3_IRQHandler
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DMA2_Stream4_IRQHandler
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DMA2_Stream5_IRQHandler
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DMA2_Stream6_IRQHandler
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DMA2_Stream7_IRQHandler
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USART6_IRQHandler
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RNG_IRQHandler
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FPU_IRQHandler
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SPI5_IRQHandler
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FMPI2C1_EV_IRQHandler
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FMPI2C1_ER_IRQHandler
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LPTIM1_IRQHandler
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B .
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ENDP
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ALIGN
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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@@ -0,0 +1,54 @@
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#! armcc -E
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; Scatter-Loading Description File
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright (c) 2014, STMicroelectronics
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice,
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; this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright notice,
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||||
; this list of conditions and the following disclaimer in the documentation
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; and/or other materials provided with the distribution.
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; 3. Neither the name of STMicroelectronics nor the names of its contributors
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; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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#define Stack_Size MBED_BOOT_STACK_SIZE
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; STM32F410RB: 128 KB FLASH (0x20000) + 32 KB SRAM (0x8000)
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LR_IROM1 0x08000000 0x20000 { ; load region size_region
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ER_IROM1 0x08000000 0x20000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
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RW_IRAM1 (0x20000000+0x1C8) (0x8000-0x1C8-Stack_Size) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_STACK (0x20000000+0x8000) EMPTY -Stack_Size { ; stack
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}
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}
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Reference in New Issue
Block a user