Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
@@ -0,0 +1,508 @@
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;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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;* File Name : startup_stm32f410rx.s
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;* Author : MCD Application Team
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;* Description : STM32F410Rx devices vector table for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == _iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* - Configure the system clock
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;*******************************************************************************
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;
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_IRQHandler ; TIM1 Update
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD 0 ; Reserved
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TIM5_IRQHandler ; TIM5
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
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DCD 0 ; Reserved
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; RNG
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DCD FPU_IRQHandler ; FPU
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI5_IRQHandler ; SPI5
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
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DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
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DCD LPTIM1_IRQHandler ; LP TIM1
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK PVD_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PVD_IRQHandler
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B PVD_IRQHandler
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PUBWEAK TAMP_STAMP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TAMP_STAMP_IRQHandler
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B TAMP_STAMP_IRQHandler
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PUBWEAK RTC_WKUP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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RTC_WKUP_IRQHandler
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B RTC_WKUP_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI0_IRQHandler
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B EXTI0_IRQHandler
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PUBWEAK EXTI1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI1_IRQHandler
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B EXTI1_IRQHandler
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PUBWEAK EXTI2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI2_IRQHandler
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B EXTI2_IRQHandler
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PUBWEAK EXTI3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI3_IRQHandler
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B EXTI3_IRQHandler
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PUBWEAK EXTI4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI4_IRQHandler
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B EXTI4_IRQHandler
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PUBWEAK DMA1_Stream0_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream0_IRQHandler
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B DMA1_Stream0_IRQHandler
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PUBWEAK DMA1_Stream1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream1_IRQHandler
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B DMA1_Stream1_IRQHandler
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PUBWEAK DMA1_Stream2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream2_IRQHandler
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B DMA1_Stream2_IRQHandler
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PUBWEAK DMA1_Stream3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream3_IRQHandler
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B DMA1_Stream3_IRQHandler
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PUBWEAK DMA1_Stream4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream4_IRQHandler
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B DMA1_Stream4_IRQHandler
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PUBWEAK DMA1_Stream5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream5_IRQHandler
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B DMA1_Stream5_IRQHandler
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PUBWEAK DMA1_Stream6_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream6_IRQHandler
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B DMA1_Stream6_IRQHandler
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PUBWEAK ADC_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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ADC_IRQHandler
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B ADC_IRQHandler
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PUBWEAK EXTI9_5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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EXTI9_5_IRQHandler
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B EXTI9_5_IRQHandler
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PUBWEAK TIM1_BRK_TIM9_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM1_BRK_TIM9_IRQHandler
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B TIM1_BRK_TIM9_IRQHandler
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PUBWEAK TIM1_UP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM1_UP_IRQHandler
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B TIM1_UP_IRQHandler
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PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM1_TRG_COM_TIM11_IRQHandler
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B TIM1_TRG_COM_TIM11_IRQHandler
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PUBWEAK TIM1_CC_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM1_CC_IRQHandler
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B TIM1_CC_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_EV_IRQHandler
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B I2C1_EV_IRQHandler
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PUBWEAK I2C1_ER_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_ER_IRQHandler
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B I2C1_ER_IRQHandler
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PUBWEAK I2C2_EV_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
I2C2_EV_IRQHandler
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B I2C2_EV_IRQHandler
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||||
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PUBWEAK I2C2_ER_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
I2C2_ER_IRQHandler
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||||
B I2C2_ER_IRQHandler
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||||
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||||
PUBWEAK SPI1_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
SPI1_IRQHandler
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||||
B SPI1_IRQHandler
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||||
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||||
PUBWEAK SPI2_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
SPI2_IRQHandler
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||||
B SPI2_IRQHandler
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||||
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||||
PUBWEAK USART1_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
USART1_IRQHandler
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||||
B USART1_IRQHandler
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||||
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||||
PUBWEAK USART2_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
USART2_IRQHandler
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||||
B USART2_IRQHandler
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||||
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||||
PUBWEAK EXTI15_10_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
EXTI15_10_IRQHandler
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||||
B EXTI15_10_IRQHandler
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||||
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||||
PUBWEAK RTC_Alarm_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
RTC_Alarm_IRQHandler
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||||
B RTC_Alarm_IRQHandler
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||||
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||||
PUBWEAK DMA1_Stream7_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA1_Stream7_IRQHandler
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||||
B DMA1_Stream7_IRQHandler
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||||
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||||
PUBWEAK TIM5_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
TIM5_IRQHandler
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||||
B TIM5_IRQHandler
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||||
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||||
PUBWEAK TIM6_DAC_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
TIM6_DAC_IRQHandler
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||||
B TIM6_DAC_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream0_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream0_IRQHandler
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||||
B DMA2_Stream0_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream1_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream1_IRQHandler
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||||
B DMA2_Stream1_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream2_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream2_IRQHandler
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||||
B DMA2_Stream2_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream3_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream3_IRQHandler
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||||
B DMA2_Stream3_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream4_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream4_IRQHandler
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||||
B DMA2_Stream4_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream5_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream5_IRQHandler
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||||
B DMA2_Stream5_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream6_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream6_IRQHandler
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||||
B DMA2_Stream6_IRQHandler
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||||
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||||
PUBWEAK DMA2_Stream7_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
DMA2_Stream7_IRQHandler
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||||
B DMA2_Stream7_IRQHandler
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||||
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||||
PUBWEAK USART6_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK FMPI2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FMPI2C1_EV_IRQHandler
|
||||
B FMPI2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK FMPI2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FMPI2C1_ER_IRQHandler
|
||||
B FMPI2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,33 @@
|
||||
/* [ROM = 128kb = 0x20000] */
|
||||
define symbol __intvec_start__ = 0x08000000;
|
||||
define symbol __region_ROM_start__ = 0x08000000;
|
||||
define symbol __region_ROM_end__ = 0x0801FFFF;
|
||||
|
||||
/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x20000000;
|
||||
define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */
|
||||
define symbol __region_RAM_start__ = 0x200001C8;
|
||||
define symbol __region_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
|
||||
/* Stack and Heap */
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __size_heap__ = 0x2000;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block STACKHEAP };
|
||||
Reference in New Issue
Block a user