Import Mbed OS hard-float snapshot
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Beslan
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;******************************************************************************
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;* File Name : startup_stm32g081xx.s
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;* Author : MCD Application Team
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;* Description : STM32G081xx devices vector table for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == __iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M0+ processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;******************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;*******************************************************************************
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD PVD_IRQHandler ; PVD through EXTI Line detect
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DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
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DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
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DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
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DCD UCPD1_2_IRQHandler ; UCPD1, UCPD2
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
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DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun
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DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
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DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1
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DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2
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DCD TIM14_IRQHandler ; TIM14
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DCD TIM15_IRQHandler ; TIM15
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DCD TIM16_IRQHandler ; TIM16
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DCD TIM17_IRQHandler ; TIM17
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DCD I2C1_IRQHandler ; I2C1
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DCD I2C2_IRQHandler ; I2C2
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_4_LPUART1_IRQHandler ; USART3, USART4, LPUART1
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DCD CEC_IRQHandler ; CEC
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DCD AES_RNG_IRQHandler ; AES, RNG
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK PVD_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PVD_IRQHandler
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B PVD_IRQHandler
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PUBWEAK RTC_TAMP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RTC_TAMP_IRQHandler
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B RTC_TAMP_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI0_1_IRQHandler
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B EXTI0_1_IRQHandler
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PUBWEAK EXTI2_3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI2_3_IRQHandler
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B EXTI2_3_IRQHandler
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PUBWEAK EXTI4_15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI4_15_IRQHandler
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B EXTI4_15_IRQHandler
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PUBWEAK UCPD1_2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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UCPD1_2_IRQHandler
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B UCPD1_2_IRQHandler
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PUBWEAK DMA1_Channel1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel1_IRQHandler
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B DMA1_Channel1_IRQHandler
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PUBWEAK DMA1_Channel2_3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel2_3_IRQHandler
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B DMA1_Channel2_3_IRQHandler
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PUBWEAK DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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B DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
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PUBWEAK ADC1_COMP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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ADC1_COMP_IRQHandler
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B ADC1_COMP_IRQHandler
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PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_BRK_UP_TRG_COM_IRQHandler
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B TIM1_BRK_UP_TRG_COM_IRQHandler
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PUBWEAK TIM1_CC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_CC_IRQHandler
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B TIM1_CC_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK TIM3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM3_IRQHandler
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B TIM3_IRQHandler
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PUBWEAK TIM6_DAC_LPTIM1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM6_DAC_LPTIM1_IRQHandler
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B TIM6_DAC_LPTIM1_IRQHandler
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PUBWEAK TIM7_LPTIM2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM7_LPTIM2_IRQHandler
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B TIM7_LPTIM2_IRQHandler
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PUBWEAK TIM14_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM14_IRQHandler
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B TIM14_IRQHandler
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PUBWEAK TIM15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM15_IRQHandler
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B TIM15_IRQHandler
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PUBWEAK TIM16_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM16_IRQHandler
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B TIM16_IRQHandler
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PUBWEAK TIM17_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM17_IRQHandler
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B TIM17_IRQHandler
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PUBWEAK I2C1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_IRQHandler
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B I2C1_IRQHandler
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PUBWEAK I2C2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C2_IRQHandler
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B I2C2_IRQHandler
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PUBWEAK SPI1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI1_IRQHandler
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B SPI1_IRQHandler
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PUBWEAK SPI2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI2_IRQHandler
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B SPI2_IRQHandler
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PUBWEAK USART1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART1_IRQHandler
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B USART1_IRQHandler
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PUBWEAK USART2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART2_IRQHandler
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B USART2_IRQHandler
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PUBWEAK USART3_4_LPUART1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART3_4_LPUART1_IRQHandler
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B USART3_4_LPUART1_IRQHandler
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PUBWEAK CEC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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CEC_IRQHandler
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B CEC_IRQHandler
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PUBWEAK AES_RNG_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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AES_RNG_IRQHandler
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B AES_RNG_IRQHandler
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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@@ -0,0 +1,59 @@
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/* Linker script to configure memory regions.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016-2020 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Device specific values */
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/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
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define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
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define symbol HEAP_SIZE = 0x2000;
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/* Common - Do not change */
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if (!isdefinedsymbol(MBED_APP_START)) {
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define symbol MBED_APP_START = MBED_ROM_START;
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}
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if (!isdefinedsymbol(MBED_APP_SIZE)) {
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define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
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}
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if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
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/* This value is normally defined by the tools
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to 0x1000 for bare metal and 0x400 for RTOS */
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define symbol MBED_BOOT_STACK_SIZE = 0x400;
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}
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/* Round up VECTORS_SIZE to 8 bytes */
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define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
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define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
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define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
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define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
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define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { };
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define block HEAP with alignment = 8, size = HEAP_SIZE { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem: MBED_APP_START { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };
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