Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2015, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ADC_1 = (int)ADC1_BASE,
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ADC_2 = (int)ADC2_BASE,
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ADC_3 = (int)ADC3_BASE
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} ADCName;
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typedef enum {
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DAC_1 = (int)DAC_BASE
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} DACName;
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typedef enum {
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UART_1 = (int)USART1_BASE,
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UART_2 = (int)USART2_BASE,
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UART_3 = (int)USART3_BASE,
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UART_4 = (int)UART4_BASE,
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UART_5 = (int)UART5_BASE,
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LPUART_1 = (int)LPUART1_BASE
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} UARTName;
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#define DEVICE_SPI_COUNT 3
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typedef enum {
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SPI_1 = (int)SPI1_BASE,
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SPI_2 = (int)SPI2_BASE,
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SPI_3 = (int)SPI3_BASE
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} SPIName;
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typedef enum {
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I2C_1 = (int)I2C1_BASE,
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I2C_2 = (int)I2C2_BASE,
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I2C_3 = (int)I2C3_BASE
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} I2CName;
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typedef enum {
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PWM_1 = (int)TIM1_BASE,
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PWM_2 = (int)TIM2_BASE,
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PWM_3 = (int)TIM3_BASE,
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PWM_4 = (int)TIM4_BASE,
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PWM_5 = (int)TIM5_BASE,
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PWM_8 = (int)TIM8_BASE,
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PWM_15 = (int)TIM15_BASE,
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PWM_16 = (int)TIM16_BASE,
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PWM_17 = (int)TIM17_BASE
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} PWMName;
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typedef enum {
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CAN_1 = (int)CAN1_BASE
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} CANName;
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typedef enum {
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QSPI_1 = (int)QSPI_R_BASE,
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} QSPIName;
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typedef enum {
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USB_FS = (int)USB_OTG_FS_PERIPH_BASE,
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} USBName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -0,0 +1,393 @@
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2018, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include "PeripheralPins.h"
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#include "mbed_toolchain.h"
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//==============================================================================
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// Notes
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//
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// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
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// HW peripheral instances. You can use them the same way as any other "normal"
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// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
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// pinout image on mbed.org.
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//
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// - The pins which are connected to other components present on the board have
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// the comment "Connected to xxx". The pin function may not work properly in this
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// case. These pins may not be displayed on the board pinout image on mbed.org.
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// Please read the board reference manual and schematic for more information.
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//
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// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
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// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
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//
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//==============================================================================
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//*** ADC ***
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MBED_WEAK const PinMap PinMap_ADC[] = {
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{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to JOY_CENTER [MT-008A_CENTER]
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{PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to JOY_CENTER [MT-008A_CENTER]
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{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to JOY_LEFT [MT-008A_LEFT]
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{PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to JOY_LEFT [MT-008A_LEFT]
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{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to JOY_RIGHT [MT-008A_RIGHT]
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{PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to JOY_RIGHT [MT-008A_RIGHT]
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{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to JOY_UP [MT-008A_UP]
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{PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to JOY_UP [MT-008A_UP]
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{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to MFX_WAKEUP [MFX_V2_WAKEUP]
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{PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // Connected to MFX_WAKEUP [MFX_V2_WAKEUP]
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{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to JOY_DOWN [MT-008A_DOWN]
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{PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to JOY_DOWN [MT-008A_DOWN]
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{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to SEG23 [GH08172T_SEG23]
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{PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to SEG23 [GH08172T_SEG23]
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{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to SEG0 [GH08172T_SEG0]
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{PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to SEG0 [GH08172T_SEG0]
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{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to SEG21 [GH08172T_SEG21]
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{PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to SEG21 [GH08172T_SEG21]
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{PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // Connected to SEG2 [GH08172T_SEG2]
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{PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 // Connected to SEG2 [GH08172T_SEG2]
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{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to GPIO_Input
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{PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to GPIO_Input
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{PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to GPIO_Input
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{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to MAG_INT [LSM303CTR_MAG_INT]
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{PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to MAG_INT [LSM303CTR_MAG_INT]
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{PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to MAG_INT [LSM303CTR_MAG_INT]
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{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to MAG_DRDY [LSM303CTR_DRDY_MAG]
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{PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to MAG_DRDY [LSM303CTR_DRDY_MAG]
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{PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to MAG_DRDY [LSM303CTR_DRDY_MAG]
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{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to VLCD
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{PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to VLCD
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{PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // Connected to VLCD
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{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to SEG22 [GH08172T_SEG22]
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{PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // Connected to SEG22 [GH08172T_SEG22]
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{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to SEG1 [GH08172T_SEG1]
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{PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to SEG1 [GH08172T_SEG1]
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
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{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
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{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
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{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
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{NC, NC, 0}
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};
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//*** DAC ***
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MBED_WEAK const PinMap PinMap_DAC[] = {
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{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // Connected to MFX_WAKEUP [MFX_V2_WAKEUP]
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{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to JOY_DOWN [MT-008A_DOWN]
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{NC, NC, 0}
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};
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//*** I2C ***
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MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
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{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to I2C1_SDA [SSM-104-L-DH_SDA]
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{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to COM3 [GH08172T_COM3]
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{PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA]
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{PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to SEG19 [GH08172T_SEG19]
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{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to MAG_INT [LSM303CTR_MAG_INT]
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
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{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to I2C1_SCL [SSM-104-L-DH_SCL]
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{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to GYRO_INT2 [L3D20_DRDY/INT2]
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{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
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{PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to SEG3 [GH08172T_SEG3]
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{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to GPIO_Input
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{NC, NC, 0}
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};
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//*** PWM ***
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// TIM5 cannot be used because already used by the us_ticker
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MBED_WEAK const PinMap PinMap_PWM[] = {
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{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to JOY_CENTER [MT-008A_CENTER]
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// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to JOY_CENTER [MT-008A_CENTER]
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{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to JOY_LEFT [MT-008A_LEFT]
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// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to JOY_LEFT [MT-008A_LEFT]
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{PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // Connected to JOY_LEFT [MT-008A_LEFT]
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{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to JOY_RIGHT [MT-008A_RIGHT]
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// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to JOY_RIGHT [MT-008A_RIGHT]
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{PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to JOY_RIGHT [MT-008A_RIGHT]
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{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to JOY_UP [MT-008A_UP]
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// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to JOY_UP [MT-008A_UP]
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{PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to JOY_UP [MT-008A_UP]
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{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to JOY_DOWN [MT-008A_DOWN]
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{PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to JOY_DOWN [MT-008A_DOWN]
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{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to SEG23 [GH08172T_SEG23]
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{PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to SEG23 [GH08172T_SEG23]
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{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to SEG0 [GH08172T_SEG0]
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{PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SEG0 [GH08172T_SEG0]
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||||
{PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to SEG0 [GH08172T_SEG0]
|
||||
{PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to SEG0 [GH08172T_SEG0]
|
||||
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to COM0 [GH08172T_COM0]
|
||||
{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to COM1 [GH08172T_COM1]
|
||||
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to COM2 [GH08172T_COM2]
|
||||
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to OTG_FS_DM [EMIF02-USB03F2_D-out]
|
||||
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
|
||||
{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to SEG21 [GH08172T_SEG21]
|
||||
{PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SEG21 [GH08172T_SEG21]
|
||||
{PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to SEG21 [GH08172T_SEG21]
|
||||
{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to SEG2 [GH08172T_SEG2]
|
||||
{PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SEG2 [GH08172T_SEG2]
|
||||
{PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to SEG2 [GH08172T_SEG2]
|
||||
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
|
||||
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SEG12 [GH08172T_SEG12]
|
||||
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to I2C1_SCL [SSM-104-L-DH_SCL]
|
||||
{PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // Connected to I2C1_SCL [SSM-104-L-DH_SCL]
|
||||
{PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to I2C1_SDA [SSM-104-L-DH_SDA]
|
||||
{PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // Connected to I2C1_SDA [SSM-104-L-DH_SDA]
|
||||
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to GYRO_INT2 [L3D20_DRDY/INT2]
|
||||
{PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to GYRO_INT2 [L3D20_DRDY/INT2]
|
||||
{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to COM3 [GH08172T_COM3]
|
||||
{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to COM3 [GH08172T_COM3]
|
||||
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
|
||||
{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA]
|
||||
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to SEG3 [GH08172T_SEG3]
|
||||
{PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // Connected to SEG3 [GH08172T_SEG3]
|
||||
{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to SEG19 [GH08172T_SEG19]
|
||||
{PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to SEG19 [GH08172T_SEG19]
|
||||
{PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to SEG19 [GH08172T_SEG19]
|
||||
{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to SEG4 [GH08172T_SEG4]
|
||||
{PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to SEG4 [GH08172T_SEG4]
|
||||
{PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to SEG4 [GH08172T_SEG4]
|
||||
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to SEG14 [GH08172T_SEG14]
|
||||
{PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to SEG14 [GH08172T_SEG14]
|
||||
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SEG9 [GH08172T_SEG9]
|
||||
{PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to SEG9 [GH08172T_SEG9]
|
||||
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SEG13 [GH08172T_SEG13]
|
||||
{PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to SEG13 [GH08172T_SEG13]
|
||||
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to OTG_FS_PowerSwitchOn [STMPS2141STR_EN]
|
||||
{PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to OTG_FS_PowerSwitchOn [STMPS2141STR_EN]
|
||||
{PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to SEG16 [GH08172T_SEG16]
|
||||
{PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to SEG7 [GH08172T_SEG7]
|
||||
{PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to SEG15 [GH08172T_SEG15]
|
||||
{PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to SEG8 [GH08172T_SEG8]
|
||||
{PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // Connected to XL_CS [LSM303CTR_CS_XL]
|
||||
{PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // Connected to XL_INT [LSM303CTR_INT_XL]
|
||||
{PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to AUDIO_RST [CS43L22_RESET]
|
||||
{PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SAI1_FS [CS43L22_LRCK]
|
||||
{PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SAI1_SCK [CS43L22_SCLK]
|
||||
{PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SAI1_SD [CS43L22_SDIN]
|
||||
{PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to LD_G [LED_Green]
|
||||
{PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to AUDIO_CLK [MP34DT01_CLK]
|
||||
{PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to QSPI_CLK [N25Q128A13EF840E_C]
|
||||
{PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to QSPI_CS [N25Q128A13EF840E_S\#]
|
||||
{PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0]
|
||||
{PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to QSPI_D1 [N25Q128A13EF840E_DQ1]
|
||||
{PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SERIAL ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_TX[] = {
|
||||
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to JOY_CENTER [MT-008A_CENTER]
|
||||
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to JOY_RIGHT [MT-008A_RIGHT]
|
||||
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to COM1 [GH08172T_COM1]
|
||||
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SCL [SSM-104-L-DH_SCL]
|
||||
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
|
||||
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA]
|
||||
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MAG_INT [LSM303CTR_MAG_INT]
|
||||
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG22 [GH08172T_SEG22]
|
||||
{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to OTG_FS_OverCurrent [STMPS2141STR_FAULT]
|
||||
{PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to OTG_FS_OverCurrent [STMPS2141STR_FAULT]
|
||||
{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||
{PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
|
||||
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG18 [GH08172T_SEG18]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_RX[] = {
|
||||
{PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to JOY_LEFT [MT-008A_LEFT]
|
||||
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to JOY_UP [MT-008A_UP]
|
||||
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to COM2 [GH08172T_COM2]
|
||||
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SDA [SSM-104-L-DH_SDA]
|
||||
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
|
||||
{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA]
|
||||
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to GPIO_Input
|
||||
{PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG1 [GH08172T_SEG1]
|
||||
{PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to OTG_FS_VBUS [EMIF02-USB03F2_Vbus]
|
||||
{PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to OTG_FS_VBUS [EMIF02-USB03F2_Vbus]
|
||||
{PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to GYRO_INT1 [L3GD20_INT1]
|
||||
{PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
|
||||
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG5 [GH08172T_SEG5]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to JOY_LEFT [MT-008A_LEFT]
|
||||
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DP [EMIF02-USB03F2_D+out]
|
||||
{PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG2 [GH08172T_SEG2]
|
||||
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SEG20 [GH08172T_SEG20]
|
||||
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG19 [GH08172T_SEG19]
|
||||
{PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to GYRO_INT1 [L3GD20_INT1]
|
||||
{PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_MOSI [L3GD20_SDA/SDI/SDO]
|
||||
{PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG16 [GH08172T_SEG16]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
||||
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to JOY_CENTER [MT-008A_CENTER]
|
||||
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG23 [GH08172T_SEG23]
|
||||
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DM [EMIF02-USB03F2_D-out]
|
||||
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SEG12 [GH08172T_SEG12]
|
||||
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to I2C1_SDA [SSM-104-L-DH_SDA]
|
||||
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG3 [GH08172T_SEG3]
|
||||
{PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SEG3 [GH08172T_SEG3]
|
||||
{PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_MISO [L3GD20_SA0/SDO]
|
||||
{PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG6 [GH08172T_SEG6]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SEG0 [GH08172T_SEG0]
|
||||
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SEG12 [GH08172T_SEG12]
|
||||
{PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SEG12 [GH08172T_SEG12]
|
||||
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SEG4 [GH08172T_SEG4]
|
||||
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to VLCD
|
||||
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to MEMS_MOSI [L3GD20_SDA/SDI/SDO]
|
||||
{PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
|
||||
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SEG23 [GH08172T_SEG23]
|
||||
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SEG19 [GH08172T_SEG19]
|
||||
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to MAG_DRDY [LSM303CTR_DRDY_MAG]
|
||||
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to OTG_FS_VBUS [EMIF02-USB03F2_Vbus]
|
||||
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to MEMS_MISO [L3GD20_SA0/SDO]
|
||||
{PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JOY_DOWN [MT-008A_DOWN]
|
||||
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
|
||||
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SEG3 [GH08172T_SEG3]
|
||||
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to OTG_FS_OverCurrent [STMPS2141STR_FAULT]
|
||||
{PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to MEMS_SCK [L3GD20_SCL/SPC]
|
||||
{PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QSPI_D1 [N25Q128A13EF840E_DQ1]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to MFX_WAKEUP [MFX_V2_WAKEUP]
|
||||
{PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to MFX_WAKEUP [MFX_V2_WAKEUP]
|
||||
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to COM3 [GH08172T_COM3]
|
||||
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SEG20 [GH08172T_SEG20]
|
||||
{PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to EXT_RST [SSM-104-L-DH_EXT_RST]
|
||||
{PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** CAN ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
|
||||
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to OTG_FS_DM [EMIF02-USB03F2_D-out]
|
||||
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to GYRO_INT2 [L3D20_DRDY/INT2]
|
||||
{PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to EXT_RST [SSM-104-L-DH_EXT_RST]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
|
||||
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to OTG_FS_DP [EMIF02-USB03F2_D+out]
|
||||
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to COM3 [GH08172T_COM3]
|
||||
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to MEMS_SCK [L3GD20_SCL/SPC]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** QUADSPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
|
||||
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SEG2 [GH08172T_SEG2]
|
||||
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
|
||||
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to SEG21 [GH08172T_SEG21]
|
||||
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_D1 [N25Q128A13EF840E_DQ1]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
|
||||
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to SEG0 [GH08172T_SEG0]
|
||||
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
|
||||
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to SEG23 [GH08172T_SEG23]
|
||||
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
|
||||
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL]
|
||||
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK [N25Q128A13EF840E_C]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
|
||||
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA]
|
||||
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // Connected to QSPI_CS [N25Q128A13EF840E_S\#]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** USBDEVICE ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_USB_FS[] = {
|
||||
// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF // Connected to COM0 [GH08172T_COM0]
|
||||
{PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to COM1 [GH08172T_COM1]
|
||||
{PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID // Connected to COM2 [GH08172T_COM2]
|
||||
{PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM // Connected to OTG_FS_DM [EMIF02-USB03F2_D-out]
|
||||
{PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP // Connected to OTG_FS_DP [EMIF02-USB03F2_D+out]
|
||||
// {PA_13, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
|
||||
// {PC_9, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE // Connected to OTG_FS_PowerSwitchOn [STMPS2141STR_EN]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
@@ -0,0 +1,277 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2018, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNamesTypes.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ALT0 = 0x100,
|
||||
ALT1 = 0x200,
|
||||
ALT2 = 0x300,
|
||||
ALT3 = 0x400
|
||||
} ALTx;
|
||||
|
||||
typedef enum {
|
||||
PA_0 = 0x00, // On P1/P2 connectors
|
||||
PA_0_ALT0 = PA_0 | ALT0,
|
||||
PA_1 = 0x01, // On P1/P2 connectors
|
||||
PA_1_ALT0 = PA_1 | ALT0,
|
||||
PA_2 = 0x02, // On P1/P2 connectors
|
||||
PA_2_ALT0 = PA_2 | ALT0,
|
||||
PA_3 = 0x03, // On P1/P2 connectors
|
||||
PA_3_ALT0 = PA_3 | ALT0,
|
||||
PA_4 = 0x04,
|
||||
PA_4_ALT0 = PA_4 | ALT0,
|
||||
PA_5 = 0x05, // On P1/P2 connectors
|
||||
PA_5_ALT0 = PA_5 | ALT0,
|
||||
PA_6 = 0x06,
|
||||
PA_6_ALT0 = PA_6 | ALT0,
|
||||
PA_7 = 0x07,
|
||||
PA_7_ALT0 = PA_7 | ALT0,
|
||||
PA_7_ALT1 = PA_7 | ALT1,
|
||||
PA_7_ALT2 = PA_7 | ALT2,
|
||||
PA_8 = 0x08,
|
||||
PA_9 = 0x09,
|
||||
PA_10 = 0x0A,
|
||||
PA_11 = 0x0B,
|
||||
PA_12 = 0x0C,
|
||||
PA_13 = 0x0D,
|
||||
PA_14 = 0x0E,
|
||||
PA_15 = 0x0F,
|
||||
PA_15_ALT0 = PA_15 | ALT0,
|
||||
|
||||
PB_0 = 0x10,
|
||||
PB_0_ALT0 = PB_0 | ALT0,
|
||||
PB_0_ALT1 = PB_0 | ALT1,
|
||||
PB_1 = 0x11,
|
||||
PB_1_ALT0 = PB_1 | ALT0,
|
||||
PB_1_ALT1 = PB_1 | ALT1,
|
||||
PB_2 = 0x12, // On P1/P2 connectors
|
||||
PB_3 = 0x13, // On P1/P2 connectors
|
||||
PB_3_ALT0 = PB_3 | ALT0,
|
||||
PB_4 = 0x14,
|
||||
PB_4_ALT0 = PB_4 | ALT0,
|
||||
PB_5 = 0x15,
|
||||
PB_5_ALT0 = PB_5 | ALT0,
|
||||
PB_6 = 0x16,
|
||||
PB_6_ALT0 = PB_6 | ALT0,
|
||||
PB_7 = 0x17,
|
||||
PB_7_ALT0 = PB_7 | ALT0,
|
||||
PB_8 = 0x18, // On P1/P2 connectors
|
||||
PB_8_ALT0 = PB_8 | ALT0,
|
||||
PB_9 = 0x19, // On P1/P2 connectors
|
||||
PB_9_ALT0 = PB_9 | ALT0,
|
||||
PB_10 = 0x1A,
|
||||
PB_11 = 0x1B,
|
||||
PB_12 = 0x1C,
|
||||
PB_13 = 0x1D,
|
||||
PB_13_ALT0 = PB_13 | ALT0,
|
||||
PB_14 = 0x1E,
|
||||
PB_14_ALT0 = PB_14 | ALT0,
|
||||
PB_14_ALT1 = PB_14 | ALT1,
|
||||
PB_15 = 0x1F,
|
||||
PB_15_ALT0 = PB_15 | ALT0,
|
||||
PB_15_ALT1 = PB_15 | ALT1,
|
||||
|
||||
PC_0 = 0x20,
|
||||
PC_0_ALT0 = PC_0 | ALT0,
|
||||
PC_0_ALT1 = PC_0 | ALT1,
|
||||
PC_1 = 0x21,
|
||||
PC_1_ALT0 = PC_1 | ALT0,
|
||||
PC_1_ALT1 = PC_1 | ALT1,
|
||||
PC_2 = 0x22,
|
||||
PC_2_ALT0 = PC_2 | ALT0,
|
||||
PC_2_ALT1 = PC_2 | ALT1,
|
||||
PC_3 = 0x23,
|
||||
PC_3_ALT0 = PC_3 | ALT0,
|
||||
PC_3_ALT1 = PC_3 | ALT1,
|
||||
PC_4 = 0x24,
|
||||
PC_4_ALT0 = PC_4 | ALT0,
|
||||
PC_5 = 0x25,
|
||||
PC_5_ALT0 = PC_5 | ALT0,
|
||||
PC_6 = 0x26,
|
||||
PC_6_ALT0 = PC_6 | ALT0,
|
||||
PC_7 = 0x27,
|
||||
PC_7_ALT0 = PC_7 | ALT0,
|
||||
PC_8 = 0x28,
|
||||
PC_8_ALT0 = PC_8 | ALT0,
|
||||
PC_9 = 0x29,
|
||||
PC_9_ALT0 = PC_9 | ALT0,
|
||||
PC_10 = 0x2A,
|
||||
PC_10_ALT0 = PC_10 | ALT0,
|
||||
PC_11 = 0x2B,
|
||||
PC_11_ALT0 = PC_11 | ALT0,
|
||||
PC_12 = 0x2C,
|
||||
PC_13 = 0x2D,
|
||||
PC_14 = 0x2E, // On P1/P2 connectors
|
||||
PC_15 = 0x2F, // On P1/P2 connectors
|
||||
|
||||
PD_0 = 0x30, // On P1/P2 connectors
|
||||
PD_1 = 0x31,
|
||||
PD_2 = 0x32,
|
||||
PD_3 = 0x33,
|
||||
PD_4 = 0x34,
|
||||
PD_5 = 0x35,
|
||||
PD_6 = 0x36,
|
||||
PD_7 = 0x37,
|
||||
PD_8 = 0x38,
|
||||
PD_9 = 0x39,
|
||||
PD_10 = 0x3A,
|
||||
PD_11 = 0x3B,
|
||||
PD_12 = 0x3C,
|
||||
PD_13 = 0x3D,
|
||||
PD_14 = 0x3E,
|
||||
PD_15 = 0x3F,
|
||||
|
||||
PE_0 = 0x40,
|
||||
PE_1 = 0x41,
|
||||
PE_2 = 0x42,
|
||||
PE_3 = 0x43,
|
||||
PE_4 = 0x44,
|
||||
PE_5 = 0x45,
|
||||
PE_6 = 0x46,
|
||||
PE_7 = 0x47,
|
||||
PE_8 = 0x48, // On P1/P2 connectors
|
||||
PE_9 = 0x49,
|
||||
PE_10 = 0x4A, // On P1/P2 connectors
|
||||
PE_11 = 0x4B, // On P1/P2 connectors
|
||||
PE_12 = 0x4C, // On P1/P2 connectors
|
||||
PE_13 = 0x4D, // On P1/P2 connectors
|
||||
PE_14 = 0x4E, // On P1/P2 connectors
|
||||
PE_15 = 0x4F, // On P1/P2 connectors
|
||||
|
||||
PH_0 = 0x70, // On P1/P2 connectors
|
||||
PH_1 = 0x71, // On P1/P2 connectors
|
||||
|
||||
// ADC internal channels
|
||||
ADC_TEMP = 0xF0,
|
||||
ADC_VREF = 0xF1,
|
||||
ADC_VBAT = 0xF2,
|
||||
|
||||
// STDIO for console print
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
|
||||
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
|
||||
#else
|
||||
STDIO_UART_TX = PD_5,
|
||||
#endif
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
|
||||
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
|
||||
#else
|
||||
STDIO_UART_RX = PD_6,
|
||||
#endif
|
||||
|
||||
// Generic signals namings
|
||||
LED1 = PE_8, // LD5 Green
|
||||
LED2 = PB_2, // LD4 Red
|
||||
LED3 = LED1,
|
||||
LED4 = LED2,
|
||||
JOYSTICK_CENTER = PA_0,
|
||||
JOYSTICK_LEFT = PA_1,
|
||||
JOYSTICK_RIGHT = PA_2,
|
||||
JOYSTICK_UP = PA_3,
|
||||
JOYSTICK_DOWN = PA_5,
|
||||
USER_BUTTON = JOYSTICK_CENTER,
|
||||
// Standardized button names
|
||||
BUTTON1 = USER_BUTTON,
|
||||
BUTTON2 = JOYSTICK_LEFT,
|
||||
BUTTON3 = JOYSTICK_RIGHT,
|
||||
BUTTON4 = JOYSTICK_UP,
|
||||
BUTTON5 = JOYSTICK_DOWN,
|
||||
|
||||
SERIAL_TX = STDIO_UART_TX,
|
||||
SERIAL_RX = STDIO_UART_RX,
|
||||
USBTX = STDIO_UART_TX,
|
||||
USBRX = STDIO_UART_RX,
|
||||
|
||||
I2C_SCL = PB_8,
|
||||
I2C_SDA = PB_9,
|
||||
SPI_MOSI = PA_7,
|
||||
SPI_MISO = PA_6,
|
||||
SPI_SCK = PA_5,
|
||||
SPI_CS = PA_4,
|
||||
PWM_OUT = PB_3,
|
||||
|
||||
/**** USB FS pins ****/
|
||||
USB_OTG_FS_DM = PA_11,
|
||||
USB_OTG_FS_DP = PA_12,
|
||||
USB_OTG_FS_ID = PA_10,
|
||||
USB_OTG_FS_NOE = PA_13,
|
||||
USB_OTG_FS_NOE_ALT0 = PC_9,
|
||||
USB_OTG_FS_SOF = PA_8,
|
||||
USB_OTG_FS_VBUS = PA_9,
|
||||
|
||||
/**** OSCILLATOR pins ****/
|
||||
RCC_OSC32_IN = PC_14,
|
||||
RCC_OSC32_OUT = PC_15,
|
||||
RCC_OSC_IN = PH_0,
|
||||
RCC_OSC_OUT = PH_1,
|
||||
|
||||
/**** DEBUG pins ****/
|
||||
SYS_JTCK_SWCLK = PA_14,
|
||||
SYS_JTDI = PA_15,
|
||||
SYS_JTDO_SWO = PB_3,
|
||||
SYS_JTMS_SWDIO = PA_13,
|
||||
SYS_JTRST = PB_4,
|
||||
SYS_PVD_IN = PB_7,
|
||||
SYS_TRACECLK = PE_2,
|
||||
SYS_TRACED0 = PE_3,
|
||||
SYS_TRACED1 = PE_4,
|
||||
SYS_TRACED2 = PE_5,
|
||||
SYS_TRACED3 = PE_6,
|
||||
SYS_WKUP1 = PA_0,
|
||||
SYS_WKUP2 = PC_13,
|
||||
SYS_WKUP3 = PE_6,
|
||||
SYS_WKUP4 = PA_2,
|
||||
SYS_WKUP5 = PC_5,
|
||||
|
||||
/**** QSPI FLASH pins ****/
|
||||
QSPI_FLASH1_IO0 = PE_12,
|
||||
QSPI_FLASH1_IO1 = PE_13,
|
||||
QSPI_FLASH1_IO2 = PE_14,
|
||||
QSPI_FLASH1_IO3 = PE_15,
|
||||
QSPI_FLASH1_SCK = PE_10,
|
||||
QSPI_FLASH1_CSN = PE_11,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,335 @@
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
{
|
||||
error("SetSysClock failed\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if DEVICE_USBDEVICE
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
#endif /* DEVICE_USBDEVICE */
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0) {
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
} else {
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
}
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if DEVICE_USBDEVICE
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
#endif /* DEVICE_USBDEVICE */
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
#if MBED_CONF_TARGET_LSE_AVAILABLE
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
|
||||
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if MBED_CONF_TARGET_LSE_AVAILABLE
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
|
||||
|
||||
#if DEVICE_USBDEVICE
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
#endif /* DEVICE_USBDEVICE */
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
@@ -0,0 +1,99 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2015, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ADC_1 = (int)ADC1_BASE,
|
||||
ADC_2 = (int)ADC2_BASE,
|
||||
ADC_3 = (int)ADC3_BASE
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
DAC_1 = (int)DAC_BASE
|
||||
} DACName;
|
||||
|
||||
typedef enum {
|
||||
UART_1 = (int)USART1_BASE,
|
||||
UART_2 = (int)USART2_BASE,
|
||||
UART_3 = (int)USART3_BASE,
|
||||
UART_4 = (int)UART4_BASE,
|
||||
UART_5 = (int)UART5_BASE,
|
||||
LPUART_1 = (int)LPUART1_BASE
|
||||
} UARTName;
|
||||
|
||||
#define DEVICE_SPI_COUNT 3
|
||||
typedef enum {
|
||||
SPI_1 = (int)SPI1_BASE,
|
||||
SPI_2 = (int)SPI2_BASE,
|
||||
SPI_3 = (int)SPI3_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_1 = (int)I2C1_BASE,
|
||||
I2C_2 = (int)I2C2_BASE,
|
||||
I2C_3 = (int)I2C3_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = (int)TIM1_BASE,
|
||||
PWM_2 = (int)TIM2_BASE,
|
||||
PWM_3 = (int)TIM3_BASE,
|
||||
PWM_4 = (int)TIM4_BASE,
|
||||
PWM_5 = (int)TIM5_BASE,
|
||||
PWM_8 = (int)TIM8_BASE,
|
||||
PWM_15 = (int)TIM15_BASE,
|
||||
PWM_16 = (int)TIM16_BASE,
|
||||
PWM_17 = (int)TIM17_BASE
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
CAN_1 = (int)CAN1_BASE
|
||||
} CANName;
|
||||
|
||||
typedef enum {
|
||||
QSPI_1 = (int)QSPI_R_BASE
|
||||
} QSPIName;
|
||||
|
||||
typedef enum {
|
||||
USB_FS = (int)USB_OTG_FS_PERIPH_BASE,
|
||||
} USBName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,352 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2018, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
#include "mbed_toolchain.h"
|
||||
|
||||
//==============================================================================
|
||||
// Notes
|
||||
//
|
||||
// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
|
||||
// HW peripheral instances. You can use them the same way as any other "normal"
|
||||
// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
|
||||
// pinout image on mbed.org.
|
||||
//
|
||||
// - The pins which are connected to other components present on the board have
|
||||
// the comment "Connected to xxx". The pin function may not work properly in this
|
||||
// case. These pins may not be displayed on the board pinout image on mbed.org.
|
||||
// Please read the board reference manual and schematic for more information.
|
||||
//
|
||||
// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
|
||||
// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
|
||||
//
|
||||
//==============================================================================
|
||||
|
||||
|
||||
//*** ADC ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_ADC[] = {
|
||||
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
|
||||
{PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
|
||||
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
|
||||
{PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
|
||||
// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to STDIO_UART_TX
|
||||
// {PA_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to STDIO_UART_TX
|
||||
// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to STDIO_UART_RX
|
||||
// {PA_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to STDIO_UART_RX
|
||||
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
|
||||
{PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
|
||||
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to LD2 [green Led]
|
||||
{PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to LD2 [green Led]
|
||||
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
|
||||
{PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
|
||||
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
|
||||
{PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
|
||||
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
|
||||
{PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
|
||||
{PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
|
||||
{PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
|
||||
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
|
||||
{PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
|
||||
{PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
|
||||
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
|
||||
{PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
|
||||
{PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
|
||||
{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
|
||||
{PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
|
||||
{PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
|
||||
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
|
||||
{PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
|
||||
{PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
|
||||
{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
|
||||
{PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
|
||||
{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
|
||||
{PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
|
||||
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
|
||||
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
|
||||
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** DAC ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_DAC[] = {
|
||||
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
|
||||
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to LD2 [green Led]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** I2C ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
|
||||
{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||
{PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||
{PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||
{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
|
||||
{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
|
||||
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||
{PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
|
||||
{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** PWM ***
|
||||
|
||||
// TIM5 cannot be used because already used by the us_ticker
|
||||
MBED_WEAK const PinMap PinMap_PWM[] = {
|
||||
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
|
||||
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
|
||||
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
|
||||
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
|
||||
{PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
|
||||
// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX
|
||||
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to STDIO_UART_TX
|
||||
// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // Connected to STDIO_UART_TX
|
||||
// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX
|
||||
// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to STDIO_UART_RX
|
||||
// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // Connected to STDIO_UART_RX
|
||||
{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LD2 [green Led]
|
||||
{PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to LD2 [green Led]
|
||||
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||
{PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
|
||||
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
|
||||
{PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
|
||||
{PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
|
||||
{PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
|
||||
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
|
||||
{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
|
||||
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
|
||||
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
|
||||
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
|
||||
{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
|
||||
{PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
|
||||
{PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
|
||||
{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
|
||||
{PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
|
||||
{PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
|
||||
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
|
||||
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
|
||||
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
|
||||
{PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
|
||||
{PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
|
||||
{PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N
|
||||
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
|
||||
{PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
|
||||
{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
|
||||
{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
|
||||
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
|
||||
{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
|
||||
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
|
||||
{PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
|
||||
{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
|
||||
{PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
|
||||
{PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
|
||||
{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
|
||||
{PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
|
||||
{PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
|
||||
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
|
||||
{PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
|
||||
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
|
||||
{PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
|
||||
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
|
||||
{PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
|
||||
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
|
||||
{PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SERIAL ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_TX[] = {
|
||||
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
|
||||
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_RX[] = {
|
||||
{PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
|
||||
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||
{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||
{PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
||||
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
|
||||
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||
{PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
|
||||
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [green Led]
|
||||
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
|
||||
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** CAN ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
|
||||
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
|
||||
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** QUADSPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
|
||||
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
|
||||
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
|
||||
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
|
||||
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
|
||||
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
|
||||
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** USBDEVICE ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_USB_FS[] = {
|
||||
// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
|
||||
{PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
|
||||
{PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID
|
||||
{PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM
|
||||
{PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP
|
||||
// {PA_13, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
|
||||
// {PC_9, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
|
||||
{NC, NC, 0}
|
||||
};
|
||||
@@ -0,0 +1,248 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2018, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNamesTypes.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ALT0 = 0x100,
|
||||
ALT1 = 0x200,
|
||||
ALT2 = 0x300,
|
||||
ALT3 = 0x400
|
||||
} ALTx;
|
||||
|
||||
typedef enum {
|
||||
PA_0 = 0x00,
|
||||
PA_0_ALT0 = PA_0 | ALT0,
|
||||
PA_0_ALT1 = PA_0 | ALT1,
|
||||
PA_1 = 0x01,
|
||||
PA_1_ALT0 = PA_1 | ALT0,
|
||||
PA_1_ALT1 = PA_1 | ALT1,
|
||||
PA_2 = 0x02,
|
||||
PA_3 = 0x03,
|
||||
PA_4 = 0x04,
|
||||
PA_4_ALT0 = PA_4 | ALT0,
|
||||
PA_5 = 0x05,
|
||||
PA_5_ALT0 = PA_5 | ALT0,
|
||||
PA_6 = 0x06,
|
||||
PA_6_ALT0 = PA_6 | ALT0,
|
||||
PA_7 = 0x07,
|
||||
PA_7_ALT0 = PA_7 | ALT0,
|
||||
PA_7_ALT1 = PA_7 | ALT1,
|
||||
PA_7_ALT2 = PA_7 | ALT2,
|
||||
PA_8 = 0x08,
|
||||
PA_9 = 0x09,
|
||||
PA_10 = 0x0A,
|
||||
PA_11 = 0x0B,
|
||||
PA_12 = 0x0C,
|
||||
PA_13 = 0x0D,
|
||||
PA_14 = 0x0E,
|
||||
PA_15 = 0x0F,
|
||||
PA_15_ALT0 = PA_15 | ALT0,
|
||||
|
||||
PB_0 = 0x10,
|
||||
PB_0_ALT0 = PB_0 | ALT0,
|
||||
PB_0_ALT1 = PB_0 | ALT1,
|
||||
PB_1 = 0x11,
|
||||
PB_1_ALT0 = PB_1 | ALT0,
|
||||
PB_1_ALT1 = PB_1 | ALT1,
|
||||
PB_2 = 0x12,
|
||||
PB_3 = 0x13,
|
||||
PB_3_ALT0 = PB_3 | ALT0,
|
||||
PB_4 = 0x14,
|
||||
PB_4_ALT0 = PB_4 | ALT0,
|
||||
PB_4_ALT1 = PB_4 | ALT1,
|
||||
PB_5 = 0x15,
|
||||
PB_5_ALT0 = PB_5 | ALT0,
|
||||
PB_5_ALT1 = PB_5 | ALT1,
|
||||
PB_6 = 0x16,
|
||||
PB_6_ALT0 = PB_6 | ALT0,
|
||||
PB_7 = 0x17,
|
||||
PB_7_ALT0 = PB_7 | ALT0,
|
||||
PB_8 = 0x18,
|
||||
PB_8_ALT0 = PB_8 | ALT0,
|
||||
PB_8_ALT1 = PB_8 | ALT1,
|
||||
PB_9 = 0x19,
|
||||
PB_9_ALT0 = PB_9 | ALT0,
|
||||
PB_9_ALT1 = PB_9 | ALT1,
|
||||
PB_10 = 0x1A,
|
||||
PB_11 = 0x1B,
|
||||
PB_12 = 0x1C,
|
||||
PB_13 = 0x1D,
|
||||
PB_13_ALT0 = PB_13 | ALT0,
|
||||
PB_14 = 0x1E,
|
||||
PB_14_ALT0 = PB_14 | ALT0,
|
||||
PB_14_ALT1 = PB_14 | ALT1,
|
||||
PB_15 = 0x1F,
|
||||
PB_15_ALT0 = PB_15 | ALT0,
|
||||
PB_15_ALT1 = PB_15 | ALT1,
|
||||
|
||||
PC_0 = 0x20,
|
||||
PC_0_ALT0 = PC_0 | ALT0,
|
||||
PC_0_ALT1 = PC_0 | ALT1,
|
||||
PC_1 = 0x21,
|
||||
PC_1_ALT0 = PC_1 | ALT0,
|
||||
PC_1_ALT1 = PC_1 | ALT1,
|
||||
PC_2 = 0x22,
|
||||
PC_2_ALT0 = PC_2 | ALT0,
|
||||
PC_2_ALT1 = PC_2 | ALT1,
|
||||
PC_3 = 0x23,
|
||||
PC_3_ALT0 = PC_3 | ALT0,
|
||||
PC_3_ALT1 = PC_3 | ALT1,
|
||||
PC_4 = 0x24,
|
||||
PC_4_ALT0 = PC_4 | ALT0,
|
||||
PC_5 = 0x25,
|
||||
PC_5_ALT0 = PC_5 | ALT0,
|
||||
PC_6 = 0x26,
|
||||
PC_6_ALT0 = PC_6 | ALT0,
|
||||
PC_7 = 0x27,
|
||||
PC_7_ALT0 = PC_7 | ALT0,
|
||||
PC_8 = 0x28,
|
||||
PC_8_ALT0 = PC_8 | ALT0,
|
||||
PC_9 = 0x29,
|
||||
PC_9_ALT0 = PC_9 | ALT0,
|
||||
PC_10 = 0x2A,
|
||||
PC_10_ALT0 = PC_10 | ALT0,
|
||||
PC_11 = 0x2B,
|
||||
PC_11_ALT0 = PC_11 | ALT0,
|
||||
PC_12 = 0x2C,
|
||||
PC_13 = 0x2D,
|
||||
PC_14 = 0x2E,
|
||||
PC_15 = 0x2F,
|
||||
|
||||
PD_2 = 0x32,
|
||||
|
||||
PH_0 = 0x70,
|
||||
PH_1 = 0x71,
|
||||
|
||||
// ADC internal channels
|
||||
ADC_TEMP = 0xF0,
|
||||
ADC_VREF = 0xF1,
|
||||
ADC_VBAT = 0xF2,
|
||||
|
||||
// Arduino connector namings
|
||||
A0 = PA_0,
|
||||
A1 = PA_1,
|
||||
A2 = PA_4,
|
||||
A3 = PB_0,
|
||||
A4 = PC_1,
|
||||
A5 = PC_0,
|
||||
D0 = PA_3,
|
||||
D1 = PA_2,
|
||||
D2 = PA_10,
|
||||
D3 = PB_3,
|
||||
D4 = PB_5,
|
||||
D5 = PB_4,
|
||||
D6 = PB_10,
|
||||
D7 = PA_8,
|
||||
D8 = PA_9,
|
||||
D9 = PC_7,
|
||||
D10 = PB_6,
|
||||
D11 = PA_7,
|
||||
D12 = PA_6,
|
||||
D13 = PA_5,
|
||||
D14 = PB_9,
|
||||
D15 = PB_8,
|
||||
|
||||
// STDIO for console print
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
|
||||
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
|
||||
#else
|
||||
STDIO_UART_TX = PA_2,
|
||||
#endif
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
|
||||
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
|
||||
#else
|
||||
STDIO_UART_RX = PA_3,
|
||||
#endif
|
||||
|
||||
// Generic signals namings
|
||||
LED1 = PA_5,
|
||||
LED2 = PA_5,
|
||||
LED3 = PA_5,
|
||||
LED4 = PA_5,
|
||||
USER_BUTTON = PC_13,
|
||||
// Standardized button names
|
||||
BUTTON1 = USER_BUTTON,
|
||||
SERIAL_TX = STDIO_UART_TX,
|
||||
SERIAL_RX = STDIO_UART_RX,
|
||||
USBTX = STDIO_UART_TX,
|
||||
USBRX = STDIO_UART_RX,
|
||||
I2C_SCL = PB_8,
|
||||
I2C_SDA = PB_9,
|
||||
SPI_MOSI = PA_7,
|
||||
SPI_MISO = PA_6,
|
||||
SPI_SCK = PA_5,
|
||||
SPI_CS = PB_6,
|
||||
PWM_OUT = PB_3,
|
||||
|
||||
/**** USB FS pins ****/
|
||||
USB_OTG_FS_DM = PA_11,
|
||||
USB_OTG_FS_DP = PA_12,
|
||||
USB_OTG_FS_ID = PA_10,
|
||||
USB_OTG_FS_NOE = PA_13,
|
||||
USB_OTG_FS_NOE_ALT0 = PC_9,
|
||||
USB_OTG_FS_SOF = PA_8,
|
||||
USB_OTG_FS_VBUS = PA_9,
|
||||
|
||||
/**** OSCILLATOR pins ****/
|
||||
RCC_OSC32_IN = PC_14,
|
||||
RCC_OSC32_OUT = PC_15,
|
||||
RCC_OSC_IN = PH_0,
|
||||
RCC_OSC_OUT = PH_1,
|
||||
|
||||
/**** DEBUG pins ****/
|
||||
SYS_JTCK_SWCLK = PA_14,
|
||||
SYS_JTDI = PA_15,
|
||||
SYS_JTDO_SWO = PB_3,
|
||||
SYS_JTMS_SWDIO = PA_13,
|
||||
SYS_JTRST = PB_4,
|
||||
SYS_PVD_IN = PB_7,
|
||||
SYS_WKUP1 = PA_0,
|
||||
SYS_WKUP2 = PC_13,
|
||||
SYS_WKUP4 = PA_2,
|
||||
SYS_WKUP5 = PC_5,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,335 @@
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
{
|
||||
error("SetSysClock failed\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if DEVICE_USBDEVICE
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
#endif /* DEVICE_USBDEVICE */
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0) {
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
} else {
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
}
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if DEVICE_USBDEVICE
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
#endif /* DEVICE_USBDEVICE */
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
#if MBED_CONF_TARGET_LSE_AVAILABLE
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
|
||||
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if MBED_CONF_TARGET_LSE_AVAILABLE
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
|
||||
|
||||
#if DEVICE_USBDEVICE
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
#endif /* DEVICE_USBDEVICE */
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
@@ -0,0 +1,97 @@
|
||||
/* mbed Microcontroller Library
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
********************************************************1***********************
|
||||
* Copyright (c) 2015, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ADC_1 = (int)ADC1_BASE,
|
||||
ADC_2 = (int)ADC2_BASE,
|
||||
ADC_3 = (int)ADC3_BASE
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
DAC_1 = (int)DAC_BASE
|
||||
} DACName;
|
||||
|
||||
typedef enum {
|
||||
UART_1 = (int)USART1_BASE,
|
||||
UART_2 = (int)USART2_BASE,
|
||||
UART_3 = (int)USART3_BASE,
|
||||
UART_4 = (int)UART4_BASE,
|
||||
UART_5 = (int)UART5_BASE,
|
||||
LPUART_1 = (int)LPUART1_BASE
|
||||
} UARTName;
|
||||
|
||||
#define DEVICE_SPI_COUNT 3
|
||||
typedef enum {
|
||||
SPI_1 = (int)SPI1_BASE,
|
||||
SPI_2 = (int)SPI2_BASE,
|
||||
SPI_3 = (int)SPI3_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_1 = (int)I2C1_BASE,
|
||||
I2C_2 = (int)I2C2_BASE,
|
||||
I2C_3 = (int)I2C3_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = (int)TIM1_BASE,
|
||||
PWM_2 = (int)TIM2_BASE,
|
||||
PWM_3 = (int)TIM3_BASE,
|
||||
PWM_4 = (int)TIM4_BASE,
|
||||
PWM_5 = (int)TIM5_BASE,
|
||||
PWM_8 = (int)TIM8_BASE,
|
||||
PWM_15 = (int)TIM15_BASE,
|
||||
PWM_16 = (int)TIM16_BASE,
|
||||
PWM_17 = (int)TIM17_BASE
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
CAN_1 = (int)CAN1_BASE
|
||||
} CANName;
|
||||
|
||||
typedef enum {
|
||||
QSPI_1 = (int)QSPI_R_BASE,
|
||||
} QSPIName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,382 @@
|
||||
/* mbed Microcontroller Library
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2018, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
#include "mbed_toolchain.h"
|
||||
|
||||
//==============================================================================
|
||||
// Notes
|
||||
//
|
||||
// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
|
||||
// HW peripheral instances. You can use them the same way as any other "normal"
|
||||
// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
|
||||
// pinout image on mbed.org.
|
||||
//
|
||||
// - The pins which are other components present on the board have
|
||||
// the comment "Connected to xxx". The pin function may not work properly in this
|
||||
// case. These pins may not be displayed on the board pinout image on mbed.org.
|
||||
// Please read the board reference manual and schematic for more information.
|
||||
//
|
||||
// - Warning: pins the default STDIO_UART_TX and STDIO_UART_RX pins are commented
|
||||
// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
|
||||
//
|
||||
//==============================================================================
|
||||
|
||||
|
||||
//*** ADC ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_ADC[] = {
|
||||
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // rhomb.io AD0
|
||||
{PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // rhomb.io AD0
|
||||
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // rhomb.io AD1
|
||||
{PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // rhomb.io AD1
|
||||
{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // rhomb.io UART-A_TXD
|
||||
{PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // rhomb.io UART-A_TXD
|
||||
{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // rhomb.io UART-A_RXD
|
||||
{PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // rhomb.io UART-A_RXD
|
||||
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // rhomb.io AD2
|
||||
{PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // rhomb.io AD2
|
||||
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // rhomb.io SPIA_CLK
|
||||
{PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // rhomb.io SPIA_CLK
|
||||
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // rhomb.io SPIA_MISO
|
||||
{PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // rhomb.io SPIA_MISO
|
||||
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // rhomb.io SPIA_MOSI
|
||||
{PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // rhomb.io SPIA_MOSI
|
||||
{PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // rhomb.io AD3
|
||||
{PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // rhomb.io AD3
|
||||
{PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 // rhomb.io NMI
|
||||
{PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 // rhomb.io NMI
|
||||
{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // rhomb.io AD5
|
||||
{PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // rhomb.io AD5
|
||||
{PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // rhomb.io AD5
|
||||
{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // rhomb.io AD4
|
||||
{PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // rhomb.io AD4
|
||||
{PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // rhomb.io AD4
|
||||
{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // rhomb.io CAPT1 (R19 must be populated)
|
||||
{PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // rhomb.io CAPT1 (R19 must be populated)
|
||||
{PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // rhomb.io CAPT1 (R19 must be populated)
|
||||
{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // rhomb.io CAPT0 (R18 must be populated)
|
||||
{PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // rhomb.io CAPT0 (R18 must be populated)
|
||||
{PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 // rhomb.io CAPT0 (R18 must be populated)
|
||||
{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // rhomb.io AD8
|
||||
{PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // rhomb.io AD8
|
||||
{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // rhomb.io AD7
|
||||
{PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // rhomb.io AD7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
|
||||
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
|
||||
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
|
||||
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** DAC ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_DAC[] = {
|
||||
{PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 // rhomb.io AD2
|
||||
{PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // rhomb.io SPIA_CLK
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** I2C ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
|
||||
{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io INT1
|
||||
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io I2C-A_SDA // Connected to ATECC608A
|
||||
{PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io QSPI_CS0 /
|
||||
{PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io SPI-A_CS1
|
||||
{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // rhomb.io AD4
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
|
||||
{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io SPI-A_CS0
|
||||
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // rhomb.io I2C-A_SCL // Connected to ATECC608A
|
||||
{PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io IO2
|
||||
{PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // rhomb.io SPI-A_CS2
|
||||
{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // rhomb.io AD5
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** PWM ***
|
||||
|
||||
// TIM5 cannot be used because already used by the us_ticker
|
||||
MBED_WEAK const PinMap PinMap_PWM[] = {
|
||||
{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io AD0
|
||||
// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // rhomb.io AD0
|
||||
{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // rhomb.io AD1
|
||||
// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // rhomb.io AD1
|
||||
{PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // rhomb.io AD1
|
||||
{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // rhomb.io UART-A_TXD
|
||||
// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // rhomb.io UART-A_TXD
|
||||
{PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // rhomb.io UART-A_TXD
|
||||
{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // rhomb.io UART-A_RXD
|
||||
// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // rhomb.io UART-A_RXD
|
||||
{PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // rhomb.io UART-A_RXD
|
||||
{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io SPI-A_CLK
|
||||
{PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // rhomb.io SPI-A_CLK
|
||||
{PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io SPI-A_MISO
|
||||
{PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io SPI-A_MISO
|
||||
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io SPI-A_MOSI
|
||||
{PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io SPI-A_MOSI
|
||||
{PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // rhomb.io SPI-A_MOSI
|
||||
{PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io SPI-A_MOSI
|
||||
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // rhomb.io IO3
|
||||
{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // rhomb.io IO4
|
||||
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // rhomb.io OTG_ID
|
||||
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // rhomb.io OTG_N
|
||||
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // rhomb.io INT2
|
||||
{PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io AD3
|
||||
{PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io AD3
|
||||
{PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // rhomb.io AD3
|
||||
{PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io NMI
|
||||
{PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io NMI
|
||||
{PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // rhomb.io NMI
|
||||
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // rhomb.io INT0
|
||||
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io IO1
|
||||
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io IO0
|
||||
{PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // rhomb.io SPI-A_CS0
|
||||
{PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // rhomb.io SPI-A_CS0
|
||||
{PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // rhomb.io INT1
|
||||
{PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // rhomb.io INT1
|
||||
{PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // rhomb.io I2C-A_SCL
|
||||
{PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io I2C-A_SCL
|
||||
{PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // rhomb.io I2C-A_SDA
|
||||
{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io I2C-A_SDA
|
||||
{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // rhomb.io IO2
|
||||
{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // rhomb.io QSPI_CS0
|
||||
{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io SPI-A_CS2
|
||||
{PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // rhomb.io SPI-A_CS2
|
||||
{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io SPI-A_CS1
|
||||
{PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // rhomb.io SPI-A_CS1
|
||||
{PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 // rhomb.io SPI-A_CS1
|
||||
{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io IO7
|
||||
{PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // rhomb.io IO7
|
||||
{PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // rhomb.io IO7
|
||||
{PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io PWM3
|
||||
{PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // rhomb.io PWM3
|
||||
{PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io PWM0
|
||||
{PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // rhomb.io PWM0
|
||||
{PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io SDIO_DATA0
|
||||
{PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // rhomb.io SDIO_DATA0
|
||||
{PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io SDIO_DATA1
|
||||
{PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // rhomb.io SDIO_DATA1
|
||||
{PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // rhomb.io IO12
|
||||
{PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // rhomb.io IO13
|
||||
{PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // rhomb.io PWM2
|
||||
{PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // rhomb.io SDIO_CDN
|
||||
{PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 // rhomb.io RESET_OUT
|
||||
{PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 // rhomb.io USB_SWITCH
|
||||
{PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // rhomb.io SAI-A_SDO
|
||||
{PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // rhomb.io SAI-A_LRCLK
|
||||
{PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // rhomb.io SAI-A_BCLK
|
||||
{PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // rhomb.io SAI-A_SDI
|
||||
{PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // rhomb.io IO5
|
||||
{PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // rhomb.io PWM1
|
||||
{PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // rhomb.io QSPI_CLK
|
||||
{PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // rhomb.io QSPI_MEM_CS
|
||||
{PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // rhomb.io QSPI_IO0
|
||||
{PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // rhomb.io QSPI_IO1
|
||||
{PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // rhomb.io QSPI_IO2
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SERIAL ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_TX[] = {
|
||||
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io AD0
|
||||
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_TXD
|
||||
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io IO4
|
||||
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io SPI-A_CS0
|
||||
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO2
|
||||
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io QSPI_CS0
|
||||
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io AD4
|
||||
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io COMP-A_N
|
||||
{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_DATA2
|
||||
{PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io SDIO_DATA2
|
||||
{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io SDIO_CLK
|
||||
{PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-B_TXD
|
||||
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io UART-C_TXD
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_RX[] = {
|
||||
{PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io AD1
|
||||
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_RXD
|
||||
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_ID
|
||||
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io INT1
|
||||
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io IO2
|
||||
{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI_CS0
|
||||
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io AD5
|
||||
{PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io COMP-A_P
|
||||
{PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_DATA3
|
||||
{PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io SDIO_DATA3
|
||||
{PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io SDIO_CMD
|
||||
{PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-B_RXD
|
||||
{PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io UART-C_RXD
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io AD1
|
||||
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_P
|
||||
{PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io INT2
|
||||
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io NMI
|
||||
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io INT0
|
||||
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io IO1
|
||||
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io 1WIRE // Connected to DS28E05X
|
||||
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_CS1
|
||||
{PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SDIO_CMD
|
||||
{PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_RTS
|
||||
{PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO12
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
||||
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io AD0
|
||||
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_MISO
|
||||
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io OTG_N
|
||||
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // rhomb.io IO1
|
||||
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // rhomb.io IO0
|
||||
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // rhomb.io INT1
|
||||
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io SPI-A_CS2
|
||||
{PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // rhomb.io SPI-A_CS2
|
||||
{PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // rhomb.io UART-A_CTS
|
||||
{PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // rhomb.io IO11
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** SPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_MOSI
|
||||
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io IO0
|
||||
{PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io IO0
|
||||
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO7
|
||||
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO14
|
||||
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_CLK
|
||||
{PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io UART-A_RTS
|
||||
{PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO3
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
|
||||
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_MISO
|
||||
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io IO1
|
||||
{PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io IO1
|
||||
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io SPI-A_CS1
|
||||
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO15
|
||||
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_DATA3
|
||||
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io UART-A_CTS
|
||||
{PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO2
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io SPI-A_CLK
|
||||
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io INT0
|
||||
{PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io INT0
|
||||
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io IO2
|
||||
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io SPI-A_CS2
|
||||
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io SDIO_DATA2
|
||||
{PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io CAN-A_TX
|
||||
{PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO1
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io AD2
|
||||
{PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io AD2
|
||||
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io INT2
|
||||
{PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // rhomb.io INT2
|
||||
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io I2C-A_SDA
|
||||
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io 1WIRE // Connected to DS28E05X
|
||||
{PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // rhomb.io CAN-A_RX
|
||||
{PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // rhomb.io QSPI_IO0
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** CAN ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_CAN_RD[] = {
|
||||
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io OTG_N
|
||||
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io I2C-A_SCL
|
||||
{PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io CAN-A_RX
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_CAN_TD[] = {
|
||||
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io OTG_P
|
||||
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io I2C-A_SDA
|
||||
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // rhomb.io CAN-A_TX
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** QUADSPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
|
||||
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io NMI
|
||||
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to MT25QL128ABA1EW7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
|
||||
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io AD3
|
||||
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to MT25QL128ABA1EW7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
|
||||
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io SPI_A_MOSI
|
||||
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to MT25QL128ABA1EW7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
|
||||
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io SPI_A_MISO
|
||||
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to MT25QL128ABA1EW7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
|
||||
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io IO2
|
||||
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to MT25QL128ABA1EW7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
|
||||
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_CS0
|
||||
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to MT25QL128ABA1EW7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
@@ -0,0 +1,351 @@
|
||||
/* mbed Microcontroller Library
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2018, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNamesTypes.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ALT0 = 0x100,
|
||||
ALT1 = 0x200,
|
||||
ALT2 = 0x300,
|
||||
ALT3 = 0x400
|
||||
} ALTx;
|
||||
|
||||
typedef enum {
|
||||
PA_0 = 0x00,
|
||||
PA_0_ALT0 = PA_0 | ALT0,
|
||||
PA_1 = 0x01,
|
||||
PA_1_ALT0 = PA_1 | ALT0,
|
||||
PA_2 = 0x02,
|
||||
PA_2_ALT0 = PA_2 | ALT0,
|
||||
PA_3 = 0x03,
|
||||
PA_3_ALT0 = PA_3 | ALT0,
|
||||
PA_4 = 0x04,
|
||||
PA_4_ALT0 = PA_4 | ALT0,
|
||||
PA_5 = 0x05,
|
||||
PA_5_ALT0 = PA_5 | ALT0,
|
||||
PA_6 = 0x06,
|
||||
PA_6_ALT0 = PA_6 | ALT0,
|
||||
PA_7 = 0x07,
|
||||
PA_7_ALT0 = PA_7 | ALT0,
|
||||
PA_7_ALT1 = PA_7 | ALT1,
|
||||
PA_7_ALT2 = PA_7 | ALT2,
|
||||
PA_8 = 0x08,
|
||||
PA_9 = 0x09,
|
||||
PA_10 = 0x0A,
|
||||
PA_11 = 0x0B,
|
||||
PA_12 = 0x0C,
|
||||
PA_13 = 0x0D,
|
||||
PA_14 = 0x0E,
|
||||
PA_15 = 0x0F,
|
||||
PA_15_ALT0 = PA_15 | ALT0,
|
||||
|
||||
PB_0 = 0x10,
|
||||
PB_0_ALT0 = PB_0 | ALT0,
|
||||
PB_0_ALT1 = PB_0 | ALT1,
|
||||
PB_1 = 0x11,
|
||||
PB_1_ALT0 = PB_1 | ALT0,
|
||||
PB_1_ALT1 = PB_1 | ALT1,
|
||||
PB_2 = 0x12,
|
||||
PB_3 = 0x13,
|
||||
PB_3_ALT0 = PB_3 | ALT0,
|
||||
PB_4 = 0x14,
|
||||
PB_4_ALT0 = PB_4 | ALT0,
|
||||
PB_5 = 0x15,
|
||||
PB_5_ALT0 = PB_5 | ALT0,
|
||||
PB_6 = 0x16,
|
||||
PB_6_ALT0 = PB_6 | ALT0,
|
||||
PB_7 = 0x17,
|
||||
PB_7_ALT0 = PB_7 | ALT0,
|
||||
PB_8 = 0x18,
|
||||
PB_8_ALT0 = PB_8 | ALT0,
|
||||
PB_9 = 0x19,
|
||||
PB_9_ALT0 = PB_9 | ALT0,
|
||||
PB_10 = 0x1A,
|
||||
PB_11 = 0x1B,
|
||||
PB_12 = 0x1C,
|
||||
PB_13 = 0x1D,
|
||||
PB_13_ALT0 = PB_13 | ALT0,
|
||||
PB_14 = 0x1E,
|
||||
PB_14_ALT0 = PB_14 | ALT0,
|
||||
PB_14_ALT1 = PB_14 | ALT1,
|
||||
PB_15 = 0x1F,
|
||||
PB_15_ALT0 = PB_15 | ALT0,
|
||||
PB_15_ALT1 = PB_15 | ALT1,
|
||||
|
||||
PC_0 = 0x20,
|
||||
PC_0_ALT0 = PC_0 | ALT0,
|
||||
PC_0_ALT1 = PC_0 | ALT1,
|
||||
PC_1 = 0x21,
|
||||
PC_1_ALT0 = PC_1 | ALT0,
|
||||
PC_1_ALT1 = PC_1 | ALT1,
|
||||
PC_2 = 0x22,
|
||||
PC_2_ALT0 = PC_2 | ALT0,
|
||||
PC_2_ALT1 = PC_2 | ALT1,
|
||||
PC_3 = 0x23,
|
||||
PC_3_ALT0 = PC_3 | ALT0,
|
||||
PC_3_ALT1 = PC_3 | ALT1,
|
||||
PC_4 = 0x24,
|
||||
PC_4_ALT0 = PC_4 | ALT0,
|
||||
PC_5 = 0x25,
|
||||
PC_5_ALT0 = PC_5 | ALT0,
|
||||
PC_6 = 0x26,
|
||||
PC_6_ALT0 = PC_6 | ALT0,
|
||||
PC_7 = 0x27,
|
||||
PC_7_ALT0 = PC_7 | ALT0,
|
||||
PC_8 = 0x28,
|
||||
PC_8_ALT0 = PC_8 | ALT0,
|
||||
PC_9 = 0x29,
|
||||
PC_9_ALT0 = PC_9 | ALT0,
|
||||
PC_10 = 0x2A,
|
||||
PC_10_ALT0 = PC_10 | ALT0,
|
||||
PC_11 = 0x2B,
|
||||
PC_11_ALT0 = PC_11 | ALT0,
|
||||
PC_12 = 0x2C,
|
||||
PC_13 = 0x2D,
|
||||
PC_14 = 0x2E,
|
||||
PC_15 = 0x2F,
|
||||
|
||||
PD_0 = 0x30,
|
||||
PD_1 = 0x31,
|
||||
PD_2 = 0x32,
|
||||
PD_3 = 0x33,
|
||||
PD_4 = 0x34,
|
||||
PD_5 = 0x35,
|
||||
PD_6 = 0x36,
|
||||
PD_7 = 0x37,
|
||||
PD_8 = 0x38,
|
||||
PD_9 = 0x39,
|
||||
PD_10 = 0x3A,
|
||||
PD_11 = 0x3B,
|
||||
PD_12 = 0x3C,
|
||||
PD_13 = 0x3D,
|
||||
PD_14 = 0x3E,
|
||||
PD_15 = 0x3F,
|
||||
|
||||
PE_0 = 0x40,
|
||||
PE_1 = 0x41,
|
||||
PE_2 = 0x42,
|
||||
PE_3 = 0x43,
|
||||
PE_4 = 0x44,
|
||||
PE_5 = 0x45,
|
||||
PE_6 = 0x46,
|
||||
PE_7 = 0x47,
|
||||
PE_8 = 0x48,
|
||||
PE_9 = 0x49,
|
||||
PE_10 = 0x4A,
|
||||
PE_11 = 0x4B,
|
||||
PE_12 = 0x4C,
|
||||
PE_13 = 0x4D,
|
||||
PE_14 = 0x4E,
|
||||
PE_15 = 0x4F,
|
||||
|
||||
PH_0 = 0x70,
|
||||
PH_1 = 0x71,
|
||||
|
||||
// ADC internal channels
|
||||
ADC_TEMP = 0xF0,
|
||||
ADC_VREF = 0xF1,
|
||||
ADC_VBAT = 0xF2,
|
||||
|
||||
// STDIO for console print
|
||||
STDIO_UART_TX = PC_4,
|
||||
STDIO_UART_RX = PC_5,
|
||||
|
||||
// Generic signals namings
|
||||
LED1 = PC_7, // LED Green
|
||||
LED2 = PC_7, // LED Green
|
||||
|
||||
USER_BUTTON = PB_1,
|
||||
// Standardized button names
|
||||
BUTTON1 = USER_BUTTON,
|
||||
|
||||
SERIAL_TX = STDIO_UART_TX,
|
||||
SERIAL_RX = STDIO_UART_RX,
|
||||
USBTX = STDIO_UART_TX,
|
||||
USBRX = STDIO_UART_RX,
|
||||
|
||||
I2C_SCL = PB_8,
|
||||
I2C_SDA = PB_9,
|
||||
SPI_MOSI = PA_7,
|
||||
SPI_MISO = PA_6,
|
||||
SPI_SCK = PA_5,
|
||||
SPI_CS = PB_6,
|
||||
PWM_OUT = PC_7,
|
||||
|
||||
/**** USB pins ****/
|
||||
USB_OTG_FS_DM = PA_11,
|
||||
USB_OTG_FS_DP = PA_12,
|
||||
USB_OTG_FS_ID = PA_10,
|
||||
|
||||
/**** OSCILLATOR pins ****/
|
||||
RCC_OSC32_IN = PC_14,
|
||||
RCC_OSC32_OUT = PC_15,
|
||||
RCC_OSC_IN = PH_0,
|
||||
RCC_OSC_OUT = PH_1,
|
||||
|
||||
/**** DEBUG pins ****/
|
||||
SYS_JTCK_SWCLK = PA_14,
|
||||
SYS_JTDI = PA_15,
|
||||
SYS_JTDO_SWO = PB_3,
|
||||
SYS_JTMS_SWDIO = PA_13,
|
||||
SYS_JTRST = PB_4,
|
||||
|
||||
/**** QSPI FLASH pins ****/
|
||||
QSPI_FLASH1_IO0 = PE_12,
|
||||
QSPI_FLASH1_IO1 = PE_13,
|
||||
QSPI_FLASH1_IO2 = PE_14,
|
||||
QSPI_FLASH1_IO3 = PE_15,
|
||||
QSPI_FLASH1_SCK = PE_10,
|
||||
QSPI_FLASH1_CSN = PE_11,
|
||||
|
||||
// rhomb.io system namings //.........................
|
||||
NMI = PB_1,
|
||||
INT0 = PB_3,
|
||||
INT1 = PB_7,
|
||||
INT2 = PA_15,
|
||||
|
||||
IO0 = PB_5,
|
||||
IO1 = PB_4,
|
||||
IO2 = PB_10,
|
||||
IO3 = PA_8,
|
||||
IO4 = PA_9,
|
||||
IO5 = PE_8,
|
||||
IO6 = PE_7,
|
||||
IO7 = PB_15,
|
||||
|
||||
IO8 = PC_13,
|
||||
IO9 = PD_7,
|
||||
IO10 = PD_10,
|
||||
IO11 = PD_11,
|
||||
IO12 = PD_12,
|
||||
IO13 = PD_13,
|
||||
IO14 = PC_3,
|
||||
IO15 = PC_2,
|
||||
|
||||
PWM0 = PC_7,
|
||||
PWM1 = PE_9,
|
||||
PWM2 = PD_14,
|
||||
PWM3 = PC_6,
|
||||
PWM4 = PB_2,
|
||||
|
||||
UART_A_RXD = PA_3,
|
||||
UART_A_TXD = PA_2,
|
||||
UART_A_CTS = PD_3,
|
||||
UART_A_RTS = PD_4,
|
||||
|
||||
UART_B_RXD = PD_6,
|
||||
UART_B_TXD = PD_5,
|
||||
|
||||
UART_C_RXD = PD_9,
|
||||
UART_C_TXD = PD_8,
|
||||
|
||||
I2C_A_SDA = PB_9,
|
||||
I2C_A_SCL = PB_8,
|
||||
I2C_B_SDA = PB_14, // R14 must be populated/closed (default is open)
|
||||
I2C_B_SCL = PB_13, // R15 must be populated/closed (default is open)
|
||||
|
||||
SPI_A_MOSI = PA_7,
|
||||
SPI_A_MISO = PA_6,
|
||||
SPI_A_CLK = PA_5,
|
||||
SPI_A_CS0 = PB_6,
|
||||
SPI_A_CS1 = PB_14,
|
||||
SPI_A_CS2 = PB_13,
|
||||
|
||||
QSPI_IO0 = PE_12,
|
||||
QSPI_IO1 = PE_13,
|
||||
QSPI_IO2 = PE_14,
|
||||
QSPI_IO3 = PE_15,
|
||||
QSPI_CLK = PE_10,
|
||||
QSPI_CS0 = PB_11,
|
||||
QSPI_MEM_CS = PE_11,
|
||||
|
||||
_1WIRE = PB_12,
|
||||
CAN_A_RX = PD_0,
|
||||
CAN_A_TX = PD_1,
|
||||
|
||||
SDIO_DATAO = PC_8,
|
||||
SDIO_DATA1 = PC_9,
|
||||
SDIO_DATA2 = PC_10,
|
||||
SDIO_DATA3 = PC_11,
|
||||
SDIO_CLK = PC_12,
|
||||
SDIO_CMD = PD_2,
|
||||
SDIO_CDN = PD_15,
|
||||
|
||||
SAI_A_BCLK = PE_5,
|
||||
SAI_A_LRCLK = PE_4,
|
||||
SAI_A_SDI = PE_6,
|
||||
SAI_A_SDO = PE_3,
|
||||
SAI_A_MCLK = PE_2,
|
||||
|
||||
OTG_P = PA_12,
|
||||
OTG_N = PA_11,
|
||||
OTG_ID = PA_10,
|
||||
|
||||
AD0 = PA_0,
|
||||
AD1 = PA_1,
|
||||
AD2 = PA_4,
|
||||
AD3 = PB_0,
|
||||
AD4 = PC_1,
|
||||
AD5 = PC_0,
|
||||
// AD6 not used
|
||||
AD7 = PC_5,
|
||||
AD8 = PC_4,
|
||||
|
||||
COMP_A_P = PC_5,
|
||||
COMP_A_N = PC_4,
|
||||
|
||||
CAPT0 = PC_3, // R18 must be populated/closed (default is open)
|
||||
CAPT1 = PC_2, // R19 must be populated/closed (default is open)
|
||||
|
||||
SWDIO = PA_13,
|
||||
SWCLK = PA_14,
|
||||
|
||||
RSTOUT = PE_0,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
|
||||
} PinName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,330 @@
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2019 ARM Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
{
|
||||
error("SetSysClock failed\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0) {
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
} else {
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
}
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
#if MBED_CONF_TARGET_LSE_AVAILABLE
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
|
||||
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
#if MBED_CONF_TARGET_LSE_AVAILABLE
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
|
||||
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
@@ -0,0 +1,373 @@
|
||||
;*******************************************************************************
|
||||
;* File Name : startup_stm32l476xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;*******************************************************************************
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
|
||||
|
||||
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1, ADC2
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
|
||||
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
|
||||
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
|
||||
DCD COMP_IRQHandler ; COMP Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
|
||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
|
||||
DCD LCD_IRQHandler ; LCD global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
DFSDM1_FLT3_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DFSDM1_FLT0_IRQHandler
|
||||
DFSDM1_FLT1_IRQHandler
|
||||
DFSDM1_FLT2_IRQHandler
|
||||
COMP_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
SWPMI1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
LCD_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@@ -0,0 +1,77 @@
|
||||
#! armcc -E
|
||||
; Scatter-Loading Description File
|
||||
;
|
||||
; SPDX-License-Identifier: BSD-3-Clause
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
#include "../cmsis_nvic.h"
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START MBED_ROM_START
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE MBED_ROM_SIZE
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
/* Round up VECTORS_SIZE to 8 bytes */
|
||||
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
|
||||
|
||||
; Crash report enabled as default
|
||||
#if !defined(MBED_CRASH_REPORT_RAM_SIZE)
|
||||
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
|
||||
#endif
|
||||
|
||||
;Vectors + Crash report - Fixed at start of RAM2 in sequence
|
||||
#define MBED_IRAM2_SIZE (MBED_RAM1_SIZE - VECTORS_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
|
||||
|
||||
#define MBED_CRASH_REPORT_RAM_START (MBED_RAM1_START + VECTORS_SIZE)
|
||||
#define MBED_IRAM2_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
|
||||
|
||||
; Minimum heap should be larger then smallest RAM bank (else can use
|
||||
; that bank for heap) and less then largest RAM bank.
|
||||
#define MINIMUM_HEAP 0x12000
|
||||
|
||||
;Splitting the RW and ZI section in IRAM1 (MBED_RAM_SIZE-MINIMUM_HEAP = 0x6000 available)
|
||||
;and IRAM2 (MBED_IRAM2_SIZE = 0x7D78 available)
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
|
||||
}
|
||||
|
||||
RW_IRAM1 MBED_RAM_START (MBED_RAM_SIZE - MINIMUM_HEAP) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
||||
}
|
||||
|
||||
RW_IRAM2 MBED_IRAM2_START MBED_IRAM2_SIZE {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,228 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "../cmsis_nvic.h"
|
||||
|
||||
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START MBED_ROM_START
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE MBED_ROM_SIZE
|
||||
#endif
|
||||
|
||||
M_CRASH_DATA_RAM_SIZE = 0x100;
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
/* This value is normally defined by the tools
|
||||
to 0x1000 for bare metal and 0x400 for RTOS */
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
/* Round up VECTORS_SIZE to 8 bytes */
|
||||
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
|
||||
SRAM2 (rwx) : ORIGIN = MBED_RAM1_START + VECTORS_SIZE, LENGTH = MBED_RAM1_SIZE - VECTORS_SIZE
|
||||
SRAM1 (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* _estack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.crash_data_ram :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__CRASH_DATA_RAM__ = .;
|
||||
__CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
|
||||
KEEP(*(.keep.crash_data_ram))
|
||||
*(.m_crash_data_ram) /* This is a user defined section */
|
||||
. += M_CRASH_DATA_RAM_SIZE;
|
||||
. = ALIGN(8);
|
||||
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
|
||||
} > SRAM2
|
||||
|
||||
/* .stack section doesn't contains any symbols. It is only
|
||||
* used for linker to reserve space for the isr stack section
|
||||
* WARNING: .stack should come immediately after the last secure memory
|
||||
* section. This provides stack overflow detection. */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
__StackLimit = .;
|
||||
*(.stack*);
|
||||
. += MBED_BOOT_STACK_SIZE - (. - __StackLimit);
|
||||
} > SRAM2
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ADDR(.stack) + SIZEOF(.stack);
|
||||
_estack = __StackTop;
|
||||
__StackLimit = ADDR(.stack);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Place holder for additional heap */
|
||||
.heap_0 (COPY):
|
||||
{
|
||||
__mbed_sbrk_start_0 = .;
|
||||
. += (ORIGIN(SRAM2) + LENGTH(SRAM2) - .);
|
||||
__mbed_krbs_start_0 = .;
|
||||
} > SRAM2
|
||||
|
||||
/* Check if heap exceeds SRAM2 */
|
||||
ASSERT(__mbed_krbs_start_0 <= (ORIGIN(SRAM2)+LENGTH(SRAM2)), "Heap is too big for SRAM2")
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
_sdata = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(8);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(8);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > SRAM1
|
||||
|
||||
/* Check if bss exceeds SRAM1 */
|
||||
ASSERT(__data_end__ <= (ORIGIN(SRAM1)+LENGTH(SRAM1)), ".data is too big for SRAM1")
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__bss_start__ = .;
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > SRAM1
|
||||
|
||||
/* Check if bss exceeds SRAM1 */
|
||||
ASSERT(__bss_end__ <= (ORIGIN(SRAM1)+LENGTH(SRAM1)), "BSS is too big for SRAM1")
|
||||
|
||||
/* Placeholder for default single heap */
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
__mbed_sbrk_start = .;
|
||||
*(.heap*)
|
||||
. += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
|
||||
__mbed_krbs_start = .;
|
||||
__HeapLimit = .;
|
||||
} > SRAM1
|
||||
|
||||
/* Check if heap exceeds SRAM1 */
|
||||
ASSERT(__HeapLimit <= (ORIGIN(SRAM1)+LENGTH(SRAM1)), "Heap is too big for SRAM1")
|
||||
}
|
||||
@@ -0,0 +1,495 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32l476xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32L476xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* Atollic update: set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
//bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
//bl main
|
||||
// Calling the crt0 'cold-start' entry point. There __libc_init_array is called
|
||||
// and when existing hardware_init_hook() and software_init_hook() before
|
||||
// starting main(). software_init_hook() is available and has to be called due
|
||||
// to initializsation when using rtos.
|
||||
bl _start
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_2_IRQHandler
|
||||
.word CAN1_TX_IRQHandler
|
||||
.word CAN1_RX0_IRQHandler
|
||||
.word CAN1_RX1_IRQHandler
|
||||
.word CAN1_SCE_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_TIM15_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word DFSDM1_FLT3_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC3_IRQHandler
|
||||
.word FMC_IRQHandler
|
||||
.word SDMMC1_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word TIM6_DAC_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word DFSDM1_FLT0_IRQHandler
|
||||
.word DFSDM1_FLT1_IRQHandler
|
||||
.word DFSDM1_FLT2_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word OTG_FS_IRQHandler
|
||||
.word DMA2_Channel6_IRQHandler
|
||||
.word DMA2_Channel7_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word QUADSPI_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word SAI2_IRQHandler
|
||||
.word SWPMI1_IRQHandler
|
||||
.word TSC_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word 0
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM15_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,621 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32l476xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32L476xx Ultra Low Power Devices vector
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1, ADC2
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
|
||||
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
|
||||
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
|
||||
DCD COMP_IRQHandler ; COMP Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
|
||||
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
|
||||
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
|
||||
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
|
||||
DCD LCD_IRQHandler ; LCD global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_IRQHandler
|
||||
B TAMP_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_2_IRQHandler
|
||||
B ADC1_2_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SCE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_SCE_IRQHandler
|
||||
B CAN1_SCE_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_TIM15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
B TIM1_BRK_TIM15_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT3_IRQHandler
|
||||
B DFSDM1_FLT3_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_BRK_IRQHandler
|
||||
B TIM8_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_UP_IRQHandler
|
||||
B TIM8_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
B TIM8_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK ADC3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC3_IRQHandler
|
||||
B ADC3_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC1_IRQHandler
|
||||
B SDMMC1_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_DAC_IRQHandler
|
||||
B TIM6_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT0_IRQHandler
|
||||
B DFSDM1_FLT0_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT1_IRQHandler
|
||||
B DFSDM1_FLT1_IRQHandler
|
||||
|
||||
PUBWEAK DFSDM1_FLT2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DFSDM1_FLT2_IRQHandler
|
||||
B DFSDM1_FLT2_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_IRQHandler
|
||||
B SAI2_IRQHandler
|
||||
|
||||
PUBWEAK SWPMI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SWPMI1_IRQHandler
|
||||
B SWPMI1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,67 @@
|
||||
/* Linker script to configure memory regions.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
|
||||
|
||||
/* [ROM = 1024kb = 0x100000] */
|
||||
define symbol __intvec_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
|
||||
/* [RAM = 96kb + 32kb = 0x20000] */
|
||||
/* Vector table dynamic copy: Total: 98 vectors * 4 = 392 bytes (0x188) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x10000000;
|
||||
define symbol __NVIC_end__ = 0x10000187;
|
||||
define symbol __region_CSTACK_start__ = 0x10000188;
|
||||
define symbol __region_CSTACK_end__ = __region_CSTACK_start__ + MBED_BOOT_STACK_SIZE;
|
||||
define symbol __region_SRAM2_start__ = __region_CSTACK_end__;
|
||||
define symbol __region_SRAM2_end__ = 0x10007FFF;
|
||||
define symbol __region_CRASH_DATA_RAM_start__ = 0x20000000;
|
||||
define symbol __region_CRASH_DATA_RAM_end__ = 0x200000FF;
|
||||
define symbol __region_SRAM1_start__ = 0x20000100;
|
||||
define symbol __region_SRAM1_end__ = 0x20017FFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region CSTACK_region = mem:[from __region_CSTACK_start__ to __region_CSTACK_end__];
|
||||
define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__];
|
||||
define region RAM_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]
|
||||
| mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
|
||||
|
||||
/* Define Crash Data Symbols */
|
||||
define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__;
|
||||
define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__;
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __size_heap__ = 0x10000;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with expanding size, alignment = 8, minimum size = __size_heap__ { };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
place in RAM_region { block HEAP, readwrite, zeroinit };
|
||||
@@ -0,0 +1,47 @@
|
||||
/* mbed Microcontroller Library
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#if !defined(MBED_ROM_START)
|
||||
#define MBED_ROM_START 0x8000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_ROM_SIZE)
|
||||
#define MBED_ROM_SIZE 0x100000 // 1.0 MB
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_START)
|
||||
#define MBED_RAM_START 0x20000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_SIZE)
|
||||
#define MBED_RAM_SIZE 0x18000 // 96 KB
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM1_START)
|
||||
#define MBED_RAM1_START 0x10000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM1_SIZE)
|
||||
#define MBED_RAM1_SIZE 0x8000 // 32 KB
|
||||
#endif
|
||||
|
||||
#define NVIC_NUM_VECTORS 98
|
||||
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM1_START // Vectors positioned at start of SRAM2
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,45 @@
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2018 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef __US_TICKER_DATA_H
|
||||
#define __US_TICKER_DATA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "stm32l4xx_ll_tim.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define TIM_MST TIM5
|
||||
#define TIM_MST_IRQ TIM5_IRQn
|
||||
#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE()
|
||||
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5()
|
||||
|
||||
#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET()
|
||||
#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET()
|
||||
|
||||
#define TIM_MST_BIT_WIDTH 32 // 16 or 32
|
||||
|
||||
#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __US_TICKER_DATA_H
|
||||
|
||||
@@ -0,0 +1,67 @@
|
||||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2015, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct gpio_irq_s {
|
||||
IRQn_Type irq_n;
|
||||
uint32_t irq_index;
|
||||
uint32_t event;
|
||||
PinName pin;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
PinDirection direction;
|
||||
__IO uint32_t *reg_in;
|
||||
__IO uint32_t *reg_out;
|
||||
};
|
||||
|
||||
struct trng_s {
|
||||
RNG_HandleTypeDef handle;
|
||||
};
|
||||
|
||||
#include "common_objects.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user