Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
@@ -0,0 +1,517 @@
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;******************************************************************************
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;* File Name : startup_stm32wb55xx_cm4.s
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;* Author : MCD Application Team
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;* Description : M4 core vector table of the STM32WB55xx devices for the
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;* IAR (EWARM) toolchain.
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;*
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == _iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* - Branches to main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;******************************************************************************
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;* @attention
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;*
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;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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;* All rights reserved.</center></h2>
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;******************************************************************************
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;
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
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DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
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DCD FLASH_IRQHandler ; FLASH global Interrupt
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DCD RCC_IRQHandler ; RCC Interrupt
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DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
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DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
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DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
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DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
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DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
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DCD ADC1_IRQHandler ; ADC1 Interrupt
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DCD USB_HP_IRQHandler ; USB High Priority Interrupt
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DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
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DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
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DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
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DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
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DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
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DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
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DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
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DCD TIM2_IRQHandler ; TIM2 Global Interrupt
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DCD PKA_IRQHandler ; PKA Interrupt
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DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
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DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
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DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
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DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
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DCD SPI1_IRQHandler ; SPI1 Interrupt
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DCD SPI2_IRQHandler ; SPI2 Interrupt
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DCD USART1_IRQHandler ; USART1 Interrupt
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DCD LPUART1_IRQHandler ; LPUART1 Interrupt
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DCD SAI1_IRQHandler ; SAI Interrupt
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DCD TSC_IRQHandler ; TSC Interrupt
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DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
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DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
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DCD CRS_IRQHandler ; CRS interrupt
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DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
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DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
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DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
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DCD HSEM_IRQHandler ; HSEM0 Interrupt
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DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
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DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
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DCD LCD_IRQHandler ; LCD Interrupt
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DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
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DCD AES1_IRQHandler ; AES1 Interrupt
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DCD AES2_IRQHandler ; AES2 Interrupt
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DCD RNG_IRQHandler ; RNG1 Interrupt
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DCD FPU_IRQHandler ; FPU Interrupt
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DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
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DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
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DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
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DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
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DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
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DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
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DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
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DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK PVD_PVM_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PVD_PVM_IRQHandler
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B PVD_PVM_IRQHandler
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PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TAMP_STAMP_LSECSS_IRQHandler
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B TAMP_STAMP_LSECSS_IRQHandler
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PUBWEAK RTC_WKUP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RTC_WKUP_IRQHandler
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B RTC_WKUP_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI0_IRQHandler
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B EXTI0_IRQHandler
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PUBWEAK EXTI1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI1_IRQHandler
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B EXTI1_IRQHandler
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PUBWEAK EXTI2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI2_IRQHandler
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B EXTI2_IRQHandler
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PUBWEAK EXTI3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI3_IRQHandler
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B EXTI3_IRQHandler
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PUBWEAK EXTI4_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI4_IRQHandler
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B EXTI4_IRQHandler
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PUBWEAK DMA1_Channel1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel1_IRQHandler
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B DMA1_Channel1_IRQHandler
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PUBWEAK DMA1_Channel2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel2_IRQHandler
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B DMA1_Channel2_IRQHandler
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PUBWEAK DMA1_Channel3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel3_IRQHandler
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B DMA1_Channel3_IRQHandler
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PUBWEAK DMA1_Channel4_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel4_IRQHandler
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B DMA1_Channel4_IRQHandler
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PUBWEAK DMA1_Channel5_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel5_IRQHandler
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B DMA1_Channel5_IRQHandler
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PUBWEAK DMA1_Channel6_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel6_IRQHandler
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B DMA1_Channel6_IRQHandler
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PUBWEAK DMA1_Channel7_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA1_Channel7_IRQHandler
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B DMA1_Channel7_IRQHandler
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PUBWEAK ADC1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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ADC1_IRQHandler
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B ADC1_IRQHandler
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PUBWEAK USB_HP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USB_HP_IRQHandler
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B USB_HP_IRQHandler
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PUBWEAK USB_LP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USB_LP_IRQHandler
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B USB_LP_IRQHandler
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PUBWEAK C2SEV_PWR_C2H_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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C2SEV_PWR_C2H_IRQHandler
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B C2SEV_PWR_C2H_IRQHandler
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PUBWEAK COMP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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COMP_IRQHandler
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B COMP_IRQHandler
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PUBWEAK EXTI9_5_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI9_5_IRQHandler
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B EXTI9_5_IRQHandler
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PUBWEAK TIM1_BRK_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_BRK_IRQHandler
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B TIM1_BRK_IRQHandler
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PUBWEAK TIM1_UP_TIM16_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_UP_TIM16_IRQHandler
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B TIM1_UP_TIM16_IRQHandler
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PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_TRG_COM_TIM17_IRQHandler
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B TIM1_TRG_COM_TIM17_IRQHandler
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PUBWEAK TIM1_CC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM1_CC_IRQHandler
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B TIM1_CC_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK PKA_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PKA_IRQHandler
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B PKA_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_EV_IRQHandler
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B I2C1_EV_IRQHandler
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PUBWEAK I2C1_ER_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_ER_IRQHandler
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B I2C1_ER_IRQHandler
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PUBWEAK I2C3_EV_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C3_EV_IRQHandler
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B I2C3_EV_IRQHandler
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PUBWEAK I2C3_ER_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C3_ER_IRQHandler
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B I2C3_ER_IRQHandler
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PUBWEAK SPI1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI1_IRQHandler
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B SPI1_IRQHandler
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PUBWEAK SPI2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI2_IRQHandler
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B SPI2_IRQHandler
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PUBWEAK USART1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART1_IRQHandler
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B USART1_IRQHandler
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PUBWEAK LPUART1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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||||
LPUART1_IRQHandler
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B LPUART1_IRQHandler
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||||
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||||
PUBWEAK SAI1_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
SAI1_IRQHandler
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||||
B SAI1_IRQHandler
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||||
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||||
PUBWEAK TSC_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
TSC_IRQHandler
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||||
B TSC_IRQHandler
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||||
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||||
PUBWEAK EXTI15_10_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
EXTI15_10_IRQHandler
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||||
B EXTI15_10_IRQHandler
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||||
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||||
PUBWEAK RTC_Alarm_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
RTC_Alarm_IRQHandler
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||||
B RTC_Alarm_IRQHandler
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||||
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||||
PUBWEAK CRS_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
CRS_IRQHandler
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||||
B CRS_IRQHandler
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||||
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||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
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B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
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||||
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||||
PUBWEAK IPCC_C1_RX_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
IPCC_C1_RX_IRQHandler
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||||
B IPCC_C1_RX_IRQHandler
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||||
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PUBWEAK IPCC_C1_TX_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
IPCC_C1_TX_IRQHandler
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||||
B IPCC_C1_TX_IRQHandler
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||||
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||||
PUBWEAK HSEM_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
HSEM_IRQHandler
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||||
B HSEM_IRQHandler
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||||
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||||
PUBWEAK LPTIM1_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
LPTIM1_IRQHandler
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||||
B LPTIM1_IRQHandler
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||||
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||||
PUBWEAK LPTIM2_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
LPTIM2_IRQHandler
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||||
B LPTIM2_IRQHandler
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||||
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||||
PUBWEAK LCD_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
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||||
B LCD_IRQHandler
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||||
|
||||
PUBWEAK QUADSPI_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
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||||
QUADSPI_IRQHandler
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||||
B QUADSPI_IRQHandler
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||||
|
||||
PUBWEAK AES1_IRQHandler
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||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES1_IRQHandler
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||||
B AES1_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@@ -0,0 +1,72 @@
|
||||
/* Linker script to configure memory regions.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016-2020 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Device specific values */
|
||||
|
||||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0xC0000; }
|
||||
|
||||
/* [ROM = 768kb = 0xC0000] */
|
||||
define symbol __intvec_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
|
||||
|
||||
/* [RAM1 = 192kb = 0x30000] */
|
||||
/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x20000000;
|
||||
define symbol __NVIC_end__ = 0x2000013F;
|
||||
define symbol __region_RAM_start__ = 0x20000140; /* Aligned on 8 bytes */
|
||||
define symbol __region_RAM_end__ = 0x2002FFFF;
|
||||
/* [RAM2aRet = 10kb = 0x2800] */
|
||||
define symbol __ICFEDIT_region_RAM2aRet_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM2aRet_SHARED_end__ = 0x200327FF;
|
||||
/* [RAM2bRet = 20kb = 0x5000] */
|
||||
define symbol __ICFEDIT_region_RAM2b_SHARED_start__ = 0x20038000;
|
||||
define symbol __ICFEDIT_region_RAM2b_SHARED_end__ = 0x2003CFFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
define region RAM2aRet_SHARED_region = mem:[from __ICFEDIT_region_RAM2aRet_SHARED_start__ to __ICFEDIT_region_RAM2aRet_SHARED_end__];
|
||||
define region RAM2b_SHARED_region = mem:[from __ICFEDIT_region_RAM2b_SHARED_start__ to __ICFEDIT_region_RAM2b_SHARED_end__];
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
/* Stack and Heap */
|
||||
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
define symbol __size_heap__ = 0x10000;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1,
|
||||
section MB_MEM2
|
||||
};
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block STACKHEAP };
|
||||
|
||||
place in RAM2aRet_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM2aRet_SHARED_region { section MB_MEM1};
|
||||
place in RAM2b_SHARED_region { section MB_MEM2};
|
||||
Reference in New Issue
Block a user