beslan/mbed-os-hardfp
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Import Mbed OS hard-float snapshot

Browse Source
This commit is contained in:
Beslan
2026-06-01 20:15:04 +03:00
commit d3738e2f89
16278 changed files with 10628036 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/TOOLCHAIN_ARM_STD/sidk_s5js100.sct Normal file
View File

@@ -0,0 +1,54 @@
#! armcc -E
;/****************************************************************************
; *
; * Copyright 2020 Samsung Electronics All Rights Reserved.
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing,
; * software distributed under the License is distributed on an
; * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
; * either express or implied. See the License for the specific
; * language governing permissions and limitations under the License.
; *
; ****************************************************************************/
#define S5JS100_BOOTMEM_BASE (0x00000000)
#define S5JS100_BOOTMEM_END (S5JS100_BOOTMEM_BASE + 0x2000)
#define S5JS100_IRAM_BASE (0x00100000)
#define S5JS100_IRAM_SIZE (0x00080000)
#define S5JS100_IRAM_END (S5JS100_IRAM_BASE + S5JS100_IRAM_SIZE)
#define S5JS100_CODE_BASE (0x406F4000)
#define S5JS100_CODE_SIZE (0x00100000)
#define S5JS100_CODE_END (S5JS100_CODE_BASE + S5JS100_CODE_SIZE)
#define S5JS100_FLASH_BASE (0x40000000)
#define S5JS100_VECTOR_SIZE (0x00000200)
#ifndef MBED_BOOT_STACK_SIZE
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 S5JS100_CODE_BASE S5JS100_CODE_SIZE { ; XIP region size_region
ER_IROM1 S5JS100_CODE_BASE S5JS100_CODE_SIZE { ; XIP address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;leave VECTOR address empty
;
RW_IRAM1 (S5JS100_IRAM_BASE+S5JS100_VECTOR_SIZE) (S5JS100_IRAM_SIZE-S5JS100_VECTOR_SIZE-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (S5JS100_IRAM_END) EMPTY -Stack_Size { ; stack
}
}

248
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/TOOLCHAIN_ARM_STD/startup_sidk_s5js100.S Normal file
View File

@@ -0,0 +1,248 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
/* External interrupts */
DCD WDT_Handler /* 0:Watchdog Timer Interrupt */
DCD PMU_APTIMER_Handler /* 1:PMU ATimer wakeup source */
DCD PMU_ALIVEPAD_Handler /* 2:PMU AlivePad wakeup source */
DCD PMU_JTAG_Handler /* 3:PMU JTAG wakeup source */
DCD SSS_SSSINT_Handler /* 4:SSS Secure Interrupt */
DCD SSS_MB_Handler /* 5:SSS Mailbox Interrupt */
DCD SSS_KM_Handler /* 6:SSS Key Manager Interrupt */
DCD DMAC_Handler /* 7:PDMAC Interrupt */
DCD SDIO_Handler /* 8:SDIO CTRL Interrupt */
DCD TINT0_Handler /* 9:ATIMER 0 Interrupt */
DCD TINT1_Handler /* 10:ATIMER 1 Interrupt */
DCD TINT2_Handler /* 11:ATIMER 2 Interrupt */
DCD TINT3_Handler /* 12:ATIMER 3 Interrupt */
DCD TINT4_Handler /* 13:ATIMER 4 Interrupt */
DCD TINT5_Handler /* 14:ATIMER 5 Interrupt */
DCD GPIO_INTR0_Handler /* 15:Gpio Group0 Interrupt */
DCD GPIO_INTR1_Handler /* 16:Gpio Group1 Interrupt */
DCD GPIO_INTR2_Handler /* 17:Gpio Group2 Interrupt */
DCD USI0_Handler /* 18:USI 0 Interrupt */
DCD USI1_Handler /* 19:USI 1 Interrupt */
DCD SPI_Handler /* 20:SPI Interrupt */
DCD I2C_Handler /* 21:I2C Interrupt */
DCD PWM0_Handler /* 22:PWM Port0 Interrupt */
DCD PWM1_Handler /* 23:PWM Port1 Interrupt */
DCD PWM2_Handler /* 24:PWM Port2 Interrupt */
DCD PWM3_Handler /* 25:PWM Port3 Interrupt */
DCD PWM4_Handler /* 26:PWM Port4 Interrupt */
DCD PPMU_Handler /* 27:Performance Monitor Interrupt */
DCD EFUSE_WR_Handler /* 28:Efuse Writer Interrupt */
DCD CM7_CTT0_Handler /* 29:CM7 CTI0 Interrupt */
DCD CM7_CTT1_Handler /* 30:CM7 CTI1 Interrupt */
DCD MB_AP_Handler /* 31:Mailbox AP Interrupt */
DCD UART0_Handler /* 32:UART0 Interrupt */
DCD UART1_Handler /* 33:UART1 Interrupt */
DCD GPADC_Handler /* 34:ADC Interrupt */
DCD MCPU_WDT_Handler /* 35:MCPU Watchdog Timer Interrupt */
DCD SSS1_Handler /* 36:SSS1 Host Interrupt */
DCD SSS2_Handler /* 37:SSS2 Host Interrupt */
DCD SSS_RESET_Handler /* 38:SSS Reset Interrupt */
DCD SLEEP_Handler /* 39:SLEEP Counter Interrupt */
DCD TSU0_Handler /* 40:TSU0 Interrupt */
DCD TSU1_Handler /* 41:TSU1 Interrupt */
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit| ;ARMCC should intentionally change stack point?
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
/* External interrupts */
EXPORT WDT_Handler [WEAK]/* 0:Watchdog Timer Interrupt */
EXPORT PMU_APTIMER_Handler [WEAK]/* 1:PMU ATimer wakeup source */
EXPORT PMU_ALIVEPAD_Handler [WEAK]/* 2:PMU AlivePad wakeup source */
EXPORT PMU_JTAG_Handler [WEAK]/* 3:PMU JTAG wakeup source */
EXPORT SSS_SSSINT_Handler [WEAK]/* 4:SSS Secure Interrupt */
EXPORT SSS_MB_Handler [WEAK]/* 5:SSS Mailbox Interrupt */
EXPORT SSS_KM_Handler [WEAK]/* 6:SSS Key Manager Interrupt */
EXPORT DMAC_Handler [WEAK]/* 7:PDMAC Interrupt */
EXPORT SDIO_Handler [WEAK]/* 8:SDIO CTRL Interrupt */
EXPORT TINT0_Handler [WEAK]/* 9:ATIMER 0 Interrupt */
EXPORT TINT1_Handler [WEAK]/* 10:ATIMER 1 Interrupt */
EXPORT TINT2_Handler [WEAK]/* 11:ATIMER 2 Interrupt */
EXPORT TINT3_Handler [WEAK]/* 12:ATIMER 3 Interrupt */
EXPORT TINT4_Handler [WEAK]/* 13:ATIMER 4 Interrupt */
EXPORT TINT5_Handler [WEAK]/* 14:ATIMER 5 Interrupt */
EXPORT GPIO_INTR0_Handler [WEAK]/* 15:Gpio Group0 Interrupt */
EXPORT GPIO_INTR1_Handler [WEAK]/* 16:Gpio Group1 Interrupt */
EXPORT GPIO_INTR2_Handler [WEAK]/* 17:Gpio Group2 Interrupt */
EXPORT USI0_Handler [WEAK]/* 18:USI 0 Interrupt */
EXPORT USI1_Handler [WEAK]/* 19:USI 1 Interrupt */
EXPORT SPI_Handler [WEAK]/* 20:SPI Interrupt */
EXPORT I2C_Handler [WEAK]/* 21:I2C Interrupt */
EXPORT PWM0_Handler [WEAK]/* 22:PWM Port0 Interrupt */
EXPORT PWM1_Handler [WEAK]/* 23:PWM Port1 Interrupt */
EXPORT PWM2_Handler [WEAK]/* 24:PWM Port2 Interrupt */
EXPORT PWM3_Handler [WEAK]/* 25:PWM Port3 Interrupt */
EXPORT PWM4_Handler [WEAK]/* 26:PWM Port4 Interrupt */
EXPORT PPMU_Handler [WEAK]/* 27:Performance Monitor Interrupt */
EXPORT EFUSE_WR_Handler [WEAK]/* 28:Efuse Writer Interrupt */
EXPORT CM7_CTT0_Handler [WEAK]/* 29:CM7 CTI0 Interrupt */
EXPORT CM7_CTT1_Handler [WEAK]/* 30:CM7 CTI1 Interrupt */
EXPORT MB_AP_Handler [WEAK]/* 31:Mailbox AP Interrupt */
EXPORT UART0_Handler [WEAK]/* 32:UART0 Interrupt */
EXPORT UART1_Handler [WEAK]/* 33:UART1 Interrupt */
EXPORT GPADC_Handler [WEAK]/* 34:ADC Interrupt */
EXPORT MCPU_WDT_Handler [WEAK]/* 35:MCPU Watchdog Timer Interrupt */
EXPORT SSS1_Handler [WEAK]/* 36:SSS1 Host Interrupt */
EXPORT SSS2_Handler [WEAK]/* 37:SSS2 Host Interrupt */
EXPORT SSS_RESET_Handler [WEAK]/* 38:SSS Reset Interrupt */
EXPORT SLEEP_Handler [WEAK]/* 39:SLEEP Counter Interrupt */
EXPORT TSU0_Handler [WEAK]/* 40:TSU0 Interrupt */
EXPORT TSU1_Handler [WEAK]/* 41:TSU1 Interrupt */
WDT_Handler
PMU_APTIMER_Handler
PMU_ALIVEPAD_Handler
PMU_JTAG_Handler
SSS_SSSINT_Handler
SSS_MB_Handler
SSS_KM_Handler
DMAC_Handler
SDIO_Handler
TINT0_Handler
TINT1_Handler
TINT2_Handler
TINT3_Handler
TINT4_Handler
TINT5_Handler
GPIO_INTR0_Handler
GPIO_INTR1_Handler
GPIO_INTR2_Handler
USI0_Handler
USI1_Handler
SPI_Handler
I2C_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PPMU_Handler
EFUSE_WR_Handler
CM7_CTT0_Handler
CM7_CTT1_Handler
MB_AP_Handler
UART0_Handler
UART1_Handler
GPADC_Handler
MCPU_WDT_Handler
SSS1_Handler
SSS2_Handler
SSS_RESET_Handler
SLEEP_Handler
TSU0_Handler
TSU1_Handler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT Samsung electronics *****END OF FILE*****

259
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/TOOLCHAIN_GCC_ARM/sidk_s5js100.ld Normal file
View File

@@ -0,0 +1,259 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/*
* This file is derivative of CMSIS V5.00 gcc_arm.ld
*/
/* Linker script to configure memory regions. */
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x406F4000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 1492K
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x00100000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 320K
#endif
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
VECTORS (rwx) : ORIGIN = 0x00000000, LENGTH = 8K
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
/* Heap 1/4 of ram and stack 1/8 */
__stack_size__ = 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = 0x140;
SECTIONS
{
/* Note: The uVisor expects this section at a fixed location, as specified
by the porting process configuration parameter: FLASH_OFFSET. */
__UVISOR_TEXT_OFFSET = 0x0;
__UVISOR_TEXT_START = ORIGIN(FLASH) + __UVISOR_TEXT_OFFSET;
.text __UVISOR_TEXT_START :
{
__vector_table = .;
KEEP(*(.vector_table))
__vector_table_end = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.isr_vector :
{
. = ALIGN(4);
_v_start = ABSOLUTE(.);
*(.vector_table)
_v_end = ABSOLUTE(.);
} > VECTORS AT > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.cordio :
{
*CORDIO_RO_2.1.o
*TRIM_2.1.o
} > FLASH
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
/* ensure that uvisor bss is at the beginning of memory */
/* Note: The uVisor expects this section at a fixed location, as specified by
* the porting process configuration parameter: SRAM_OFFSET. */
__UVISOR_SRAM_OFFSET = 0x140;
__UVISOR_BSS_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.ramfunc ALIGN(4): {
_sramfuncs = ABSOLUTE(.);
KEEP(*(.ramfunc .ramfunc.*))
_eramfuncs = ABSOLUTE(.);
} > RAM AT > FLASH
_framfuncs = LOADADDR(.ramfunc);
/* From now on you can insert any other SRAM region. */
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE - 0x1000;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

286
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/TOOLCHAIN_GCC_ARM/startup_sidk_s5js100.S Normal file
View File

@@ -0,0 +1,286 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
;/****************************************************************************
; *
; * Copyright 2020 Samsung Electronics All Rights Reserved.
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing,
; * software distributed under the License is distributed on an
; * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
; * either express or implied. See the License for the specific
; * language governing permissions and limitations under the License.
; *
; ****************************************************************************/
/* @file : startup_sidk_s5js100.S
* @brief : start up code for GCC_ARM
* @date : June 2019
*
* @note : Add chip dependent isr vectors and register handlers
*
*/
/*
* This file is derivative of CMSIS V5.00 startup_ARMCM3.S
*/
.syntax unified
.arch armv7-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long WDT_Handler /* 0:Watchdog Timer Interrupt */
.long PMU_APTIMER_Handler /* 1:PMU ATimer wakeup source */
.long PMU_ALIVEPAD_Handler /* 2:PMU AlivePad wakeup source */
.long PMU_JTAG_Handler /* 3:PMU JTAG wakeup source */
.long SSS_SSSINT_Handler /* 4:SSS Secure Interrupt */
.long SSS_MB_Handler /* 5:SSS Mailbox Interrupt */
.long SSS_KM_Handler /* 6:SSS Key Manager Interrupt */
.long DMAC_Handler /* 7:PDMAC Interrupt */
.long SDIO_Handler /* 8:SDIO CTRL Interrupt */
.long TINT0_Handler /* 9:ATIMER 0 Interrupt */
.long TINT1_Handler /* 10:ATIMER 1 Interrupt */
.long TINT2_Handler /* 11:ATIMER 2 Interrupt */
.long TINT3_Handler /* 12:ATIMER 3 Interrupt */
.long TINT4_Handler /* 13:ATIMER 4 Interrupt */
.long TINT5_Handler /* 14:ATIMER 5 Interrupt */
.long GPIO_INTR0_Handler /* 15:Gpio Group0 Interrupt */
.long GPIO_INTR1_Handler /* 16:Gpio Group1 Interrupt */
.long GPIO_INTR2_Handler /* 17:Gpio Group2 Interrupt */
.long USI0_Handler /* 18:USI 0 Interrupt */
.long USI1_Handler /* 19:USI 1 Interrupt */
.long SPI_Handler /* 20:SPI Interrupt */
.long I2C_Handler /* 21:I2C Interrupt */
.long PWM0_Handler /* 22:PWM Port0 Interrupt */
.long PWM1_Handler /* 23:PWM Port1 Interrupt */
.long PWM2_Handler /* 24:PWM Port2 Interrupt */
.long PWM3_Handler /* 25:PWM Port3 Interrupt */
.long PWM4_Handler /* 26:PWM Port4 Interrupt */
.long PPMU_Handler /* 27:Performance Monitor Interrupt */
.long EFUSE_WR_Handler /* 28:Efuse Writer Interrupt */
.long CM7_CTT0_Handler /* 29:CM7 CTI0 Interrupt */
.long CM7_CTT1_Handler /* 30:CM7 CTI1 Interrupt */
.long MB_AP_Handler /* 31:Mailbox AP Interrupt */
.long UART0_Handler /* 32:UART0 Interrupt */
.long UART1_Handler /* 33:UART1 Interrupt */
.long GPADC_Handler /* 34:ADC Interrupt */
.long MCPU_WDT_Handler /* 35:MCPU Watchdog Timer Interrupt */
.long SSS1_Handler /* 36:SSS1 Host Interrupt */
.long SSS2_Handler /* 37:SSS2 Host Interrupt */
.long SSS_RESET_Handler /* 38:SSS Reset Interrupt */
.long SLEEP_Handler /* 39:SLEEP Counter Interrupt */
.long TSU0_Handler /* 40:TSU0 Interrupt */
.long TSU1_Handler /* 41:TSU1 Interrupt */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*b . */
ldr r0, =SystemInit
blx r0
/* The call to uvisor_init() happens independently of uVisor being enabled or
* not, so it is conditionally compiled only based on FEATURE_UVISOR. */
#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
/* Call uvisor_init() */
ldr r0, =uvisor_init
blx r0
#endif /* FEATURE_UVISOR && TARGET_UVISOR_SUPPORTED */
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* copy ramfunc from FLASH to RAM */
ldr r1, =_framfuncs
ldr r2, =_sramfuncs
ldr r3, =_eramfuncs
subs r3, r2
ble .Lramfunc_loop_end
movs r4, 0
.Lramfunc_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lramfunc_loop
.Lramfunc_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
nop
nop
nop
nop
nop
nop
b .
b HardFault_Handler
nop
nop
nop
nop
nop
nop
nop
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler WDT_Handler /* 0:Watchdog Timer Interrupt */
def_irq_default_handler PMU_APTIMER_Handler /* 1:PMU ATimer wakeup source */
def_irq_default_handler PMU_ALIVEPAD_Handler /* 2:PMU AlivePad wakeup source */
def_irq_default_handler PMU_JTAG_Handler /* 3:PMU JTAG wakeup source */
def_irq_default_handler SSS_SSSINT_Handler /* 4:SSS Secure Interrupt */
def_irq_default_handler SSS_MB_Handler /* 5:SSS Mailbox Interrupt */
def_irq_default_handler SSS_KM_Handler /* 6:SSS Key Manager Interrupt */
def_irq_default_handler DMAC_Handler /* 7:PDMAC Interrupt */
def_irq_default_handler SDIO_Handler /* 8:SDIO CTRL Interrupt */
def_irq_default_handler TINT0_Handler /* 9:ATIMER 0 Interrupt */
def_irq_default_handler TINT1_Handler /* 10:ATIMER 1 Interrupt */
def_irq_default_handler TINT2_Handler /* 11:ATIMER 2 Interrupt */
def_irq_default_handler TINT3_Handler /* 12:ATIMER 3 Interrupt */
def_irq_default_handler TINT4_Handler /* 13:ATIMER 4 Interrupt */
def_irq_default_handler TINT5_Handler /* 14:ATIMER 5 Interrupt */
def_irq_default_handler GPIO_INTR0_Handler /* 15:Gpio Group0 Interrupt */
def_irq_default_handler GPIO_INTR1_Handler /* 16:Gpio Group1 Interrupt */
def_irq_default_handler GPIO_INTR2_Handler /* 17:Gpio Group2 Interrupt */
def_irq_default_handler USI0_Handler /* 18:USI 0 Interrupt */
def_irq_default_handler USI1_Handler /* 19:USI 1 Interrupt */
def_irq_default_handler SPI_Handler /* 20:SPI Interrupt */
def_irq_default_handler I2C_Handler /* 21:I2C Interrupt */
def_irq_default_handler PWM0_Handler /* 22:PWM Port0 Interrupt */
def_irq_default_handler PWM1_Handler /* 23:PWM Port1 Interrupt */
def_irq_default_handler PWM2_Handler /* 24:PWM Port2 Interrupt */
def_irq_default_handler PWM3_Handler /* 25:PWM Port3 Interrupt */
def_irq_default_handler PWM4_Handler /* 26:PWM Port4 Interrupt */
def_irq_default_handler PPMU_Handler /* 27:Performance Monitor Interrupt */
def_irq_default_handler EFUSE_WR_Handler /* 28:Efuse Writer Interrupt */
def_irq_default_handler CM7_CTT0_Handler /* 29:CM7 CTI0 Interrupt */
def_irq_default_handler CM7_CTT1_Handler /* 30:CM7 CTI1 Interrupt */
def_irq_default_handler MB_AP_Handler /* 31:Mailbox AP Interrupt */
def_irq_default_handler UART0_Handler /* 32:UART0 Interrupt */
def_irq_default_handler UART1_Handler /* 33:UART1 Interrupt */
def_irq_default_handler GPADC_Handler /* 34:ADC Interrupt */
def_irq_default_handler MCPU_WDT_Handler /* 35:MCPU Watchdog Timer Interrupt */
def_irq_default_handler SSS1_Handler /* 36:SSS1 Host Interrupt */
def_irq_default_handler SSS2_Handler /* 37:SSS2 Host Interrupt */
def_irq_default_handler SSS_RESET_Handler /* 38:SSS Reset Interrupt */
def_irq_default_handler SLEEP_Handler /* 39:SLEEP Counter Interrupt */
def_irq_default_handler TSU0_Handler /* 40:TSU0 Interrupt */
def_irq_default_handler TSU1_Handler /* 41:TSU1 Interrupt */
.end

56
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/TOOLCHAIN_IAR/sidk_s5js100.icf Normal file
View File

@@ -0,0 +1,56 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/* Linker file for the IAR Compiler for ARM */
/* Specials */
/* Meory Regions */
define symbol S5JS100_BOOTMEM_BASE = 0x00000000;
define symbol S5JS100_BOOTMEM_END = S5JS100_BOOTMEM_BASE + 8K;
define symbol S5JS100_IRAM_BASE = 0x00100000;
define symbol S5JS100_IRAM_END = S5JS100_IRAM_BASE + 512K;
define symbol S5JS100_CODE_BASE = 0x406F4000;
define symbol S5JS100_CODE_END = S5JS100_CODE_BASE + 1492K;
define symbol S5JS100_FLASH_BASE = 0x40000000;
/* Stack Size & Heap Size*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol CSTACK_SIZE = MBED_BOOT_STACK_SIZE;
define symbol __ICFEDIT_size_heap__ = 0x50000;
/*Meory regions*/
define memory mem with size = 4G;
define region VECTOR_REGION = mem:[from S5JS100_BOOTMEM_BASE to S5JS100_BOOTMEM_END];
define region ROM_REGION = mem:[from S5JS100_CODE_BASE to S5JS100_CODE_END];
define region IRAM_REGION = mem:[from S5JS100_IRAM_BASE to S5JS100_IRAM_END];
define block CSTACK with alignment = 8, size = CSTACK_SIZE { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:S5JS100_CODE_BASE { readonly section .intvec};
/* place at address mem:S5JS100_BOOTMEM_BASE { readwrite section .isr_vector }; */
place in ROM_REGION { readonly };
place in IRAM_REGION { block RW, block ZI, block HEAP, block CSTACK};

255
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/TOOLCHAIN_IAR/startup_s5js100.S Normal file
View File

@@ -0,0 +1,255 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
MODULE ?cstartup
SECTION .isr_vector:DATA:NOROOT(3)
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
EXTERN _start
PUBLIC __vector_table
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD WDT_Handler /* 0:Watchdog Timer Interrupt */
DCD PMU_APTIMER_Handler /* 1:PMU ATimer wakeup source */
DCD PMU_ALIVEPAD_Handler /* 2:PMU AlivePad wakeup source */
DCD PMU_JTAG_Handler /* 3:PMU JTAG wakeup source */
DCD SSS_SSSINT_Handler /* 4:SSS Secure Interrupt */
DCD SSS_MB_Handler /* 5:SSS Mailbox Interrupt */
DCD SSS_KM_Handler /* 6:SSS Key Manager Interrupt */
DCD DMAC_Handler /* 7:PDMAC Interrupt */
DCD SDIO_Handler /* 8:SDIO CTRL Interrupt */
DCD TINT0_Handler /* 9:ATIMER 0 Interrupt */
DCD TINT1_Handler /* 10:ATIMER 1 Interrupt */
DCD TINT2_Handler /* 11:ATIMER 2 Interrupt */
DCD TINT3_Handler /* 12:ATIMER 3 Interrupt */
DCD TINT4_Handler /* 13:ATIMER 4 Interrupt */
DCD TINT5_Handler /* 14:ATIMER 5 Interrupt */
DCD GPIO_INTR0_Handler /* 15:Gpio Group0 Interrupt */
DCD GPIO_INTR1_Handler /* 16:Gpio Group1 Interrupt */
DCD GPIO_INTR2_Handler /* 17:Gpio Group2 Interrupt */
DCD USI0_Handler /* 18:USI 0 Interrupt */
DCD USI1_Handler /* 19:USI 1 Interrupt */
DCD SPI_Handler /* 20:SPI Interrupt */
DCD I2C_Handler /* 21:I2C Interrupt */
DCD PWM0_Handler /* 22:PWM Port0 Interrupt */
DCD PWM1_Handler /* 23:PWM Port1 Interrupt */
DCD PWM2_Handler /* 24:PWM Port2 Interrupt */
DCD PWM3_Handler /* 25:PWM Port3 Interrupt */
DCD PWM4_Handler /* 26:PWM Port4 Interrupt */
DCD PPMU_Handler /* 27:Performance Monitor Interrupt */
DCD EFUSE_WR_Handler /* 28:Efuse Writer Interrupt */
DCD CM7_CTT0_Handler /* 29:CM7 CTI0 Interrupt */
DCD CM7_CTT1_Handler /* 30:CM7 CTI1 Interrupt */
DCD MB_AP_Handler /* 31:Mailbox AP Interrupt */
DCD UART0_Handler /* 32:UART0 Interrupt */
DCD UART1_Handler /* 33:UART1 Interrupt */
DCD GPADC_Handler /* 34:ADC Interrupt */
DCD MCPU_WDT_Handler /* 35:MCPU Watchdog Timer Interrupt */
DCD SSS1_Handler /* 36:SSS1 Host Interrupt */
DCD SSS2_Handler /* 37:SSS2 Host Interrupt */
DCD SSS_RESET_Handler /* 38:SSS Reset Interrupt */
DCD SLEEP_Handler /* 39:SLEEP Counter Interrupt */
DCD TSU0_Handler /* 40:TSU0 Interrupt */
DCD TSU1_Handler /* 41:TSU1 Interrupt */
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =sfe(CSTACK)
MSR MSP, R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBLIC Default_Handler
Default_Handler
/* External interrupts */
PUBWEAK WDT_Handler /* 0:Watchdog Timer Interrupt */
PUBWEAK PMU_APTIMER_Handler /* 1:PMU ATimer wakeup source */
PUBWEAK PMU_ALIVEPAD_Handler /* 2:PMU AlivePad wakeup source */
PUBWEAK PMU_JTAG_Handler /* 3:PMU JTAG wakeup source */
PUBWEAK SSS_SSSINT_Handler /* 4:SSS Secure Interrupt */
PUBWEAK SSS_MB_Handler /* 5:SSS Mailbox Interrupt */
PUBWEAK SSS_KM_Handler /* 6:SSS Key Manager Interrupt */
PUBWEAK DMAC_Handler /* 7:PDMAC Interrupt */
PUBWEAK SDIO_Handler /* 8:SDIO CTRL Interrupt */
PUBWEAK TINT0_Handler /* 9:ATIMER 0 Interrupt */
PUBWEAK TINT1_Handler /* 10:ATIMER 1 Interrupt */
PUBWEAK TINT2_Handler /* 11:ATIMER 2 Interrupt */
PUBWEAK TINT3_Handler /* 12:ATIMER 3 Interrupt */
PUBWEAK TINT4_Handler /* 13:ATIMER 4 Interrupt */
PUBWEAK TINT5_Handler /* 14:ATIMER 5 Interrupt */
PUBWEAK GPIO_INTR0_Handler /* 15:Gpio Group0 Interrupt */
PUBWEAK GPIO_INTR1_Handler /* 16:Gpio Group1 Interrupt */
PUBWEAK GPIO_INTR2_Handler /* 17:Gpio Group2 Interrupt */
PUBWEAK USI0_Handler /* 18:USI 0 Interrupt */
PUBWEAK USI1_Handler /* 19:USI 1 Interrupt */
PUBWEAK SPI_Handler /* 20:SPI Interrupt */
PUBWEAK I2C_Handler /* 21:I2C Interrupt */
PUBWEAK PWM0_Handler /* 22:PWM Port0 Interrupt */
PUBWEAK PWM1_Handler /* 23:PWM Port1 Interrupt */
PUBWEAK PWM2_Handler /* 24:PWM Port2 Interrupt */
PUBWEAK PWM3_Handler /* 25:PWM Port3 Interrupt */
PUBWEAK PWM4_Handler /* 26:PWM Port4 Interrupt */
PUBWEAK PPMU_Handler /* 27:Performance Monitor Interrupt */
PUBWEAK EFUSE_WR_Handler /* 28:Efuse Writer Interrupt */
PUBWEAK CM7_CTT0_Handler /* 29:CM7 CTI0 Interrupt */
PUBWEAK CM7_CTT1_Handler /* 30:CM7 CTI1 Interrupt */
PUBWEAK MB_AP_Handler /* 31:Mailbox AP Interrupt */
PUBWEAK UART0_Handler /* 32:UART0 Interrupt */
PUBWEAK UART1_Handler /* 33:UART1 Interrupt */
PUBWEAK GPADC_Handler /* 34:ADC Interrupt */
PUBWEAK MCPU_WDT_Handler /* 35:MCPU Watchdog Timer Interrupt */
PUBWEAK SSS1_Handler /* 36:SSS1 Host Interrupt */
PUBWEAK SSS2_Handler /* 37:SSS2 Host Interrupt */
PUBWEAK SSS_RESET_Handler /* 38:SSS Reset Interrupt */
PUBWEAK SLEEP_Handler /* 39:SLEEP Counter Interrupt */
PUBWEAK TSU0_Handler /* 40:TSU0 Interrupt */
PUBWEAK TSU1_Handler /* 41:TSU1 Interrupt */
WDT_Handler
PMU_APTIMER_Handler
PMU_ALIVEPAD_Handler
PMU_JTAG_Handler
SSS_SSSINT_Handler
SSS_MB_Handler
SSS_KM_Handler
DMAC_Handler
SDIO_Handler
TINT0_Handler
TINT1_Handler
TINT2_Handler
TINT3_Handler
TINT4_Handler
TINT5_Handler
GPIO_INTR0_Handler
GPIO_INTR1_Handler
GPIO_INTR2_Handler
USI0_Handler
USI1_Handler
SPI_Handler
I2C_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PPMU_Handler
EFUSE_WR_Handler
CM7_CTT0_Handler
CM7_CTT1_Handler
MB_AP_Handler
UART0_Handler
UART1_Handler
GPADC_Handler
MCPU_WDT_Handler
SSS1_Handler
SSS2_Handler
SSS_RESET_Handler
SLEEP_Handler
TSU0_Handler
TSU1_Handler
END

43
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/cmsis.h Normal file
View File

@@ -0,0 +1,43 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "s5js100.h"
#include "s5js100_type.h"
#include "s5js100_rtos.h"
/* s5js100 System Core */
#include "system_s5js100.h"
#include "system_core_s5js100.h"
/* s5js100 System Clock */
#include "s5js100_cmu.h"
#include "s5js100_vclk.h"
/* Embedded Flash Driver */
#include "sflash_api.h"
/* s5js100 Power */
#include "s5js100_pwr.h"
/* NVIC Driver */
#include "cmsis_nvic.h"
/* System Core Version */
#include "system_core_version.h"
/* HAL implementation */
#include "s5js100_hal.h"
#endif

26
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/cmsis_nvic.h Normal file
View File

@@ -0,0 +1,26 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 48)
#define NVIC_RAM_VECTOR_ADDRESS 0x00000000 //Location of vectors in RAM
#endif

76
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/cmsis_nvic_virtual.h Normal file
View File

@@ -0,0 +1,76 @@
/*
* Copyright (c) 2020 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* @file : cmsis_nvic_virtual.h
* @brief : NVIC functions list
* @date : December 2019
* @note : List of NVIC macro and customize TFM interrupt
*/
#include "cmsis.h"
#ifndef NVIC_VIRTUAL_H
#define NVIC_VIRTUAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "s5js100_type.h"
/* NVIC functions */
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_TFMSystemReset
/**
* \brief Overriding the default CMSIS system reset implementation by calling
* secure TFM service.
*
*/
__NO_RETURN __STATIC_INLINE void __NVIC_TFMSystemReset(void)
{
putreg32(0x1, 0x8301100C);
putreg32(0x1 << 1, 0x82020018);
putreg32(0x4, 0x83011000); // enable watchdog
putreg32(0x1, 0x83011010);
putreg32(0x1, 0x83011020);
putreg32(327, 0x83011004); //set 10ms to be reset , 1 sec=32768
putreg32(0xFF, 0x83011008); // force to load value to be reset
/* Wait for the reset */
for (;;) {
}
}
#ifdef __cplusplus
}
#endif
#endif

651
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100.h Normal file
View File

@@ -0,0 +1,651 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef S5JS100_H
#define S5JS100_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
#define S5JS100_IRQ_FIRST (16) /* Vector number of the first external interrupt */
typedef enum IRQn {
/* ------------------- Cortex-M7 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* --------------------- S5JS100 Specific Interrupt Numbers ---------------- */
S5JS100_IRQ_WDG = 0,
S5JS100_IRQ_PMU_ApTimer = 1,
S5JS100_IRQ_PMU_AlivePad = 2,
S5JS100_IRQ_PMU_JtagInt = 3,
S5JS100_IRQ_SSS_SSSINT = 4,
S5JS100_IRQ_SSS_MBINT = 5,
S5JS100_IRQ_SSS_KMINT = 6,
S5JS100_IRQ_DMACINTR = 7,
S5JS100_IRQ_SDIO_INTREQ_L = 8,
S5JS100_IRQ_TINT0 = 9,
S5JS100_IRQ_TINT1 = 10,
S5JS100_IRQ_TINT2 = 11,
S5JS100_IRQ_TINT3 = 12,
S5JS100_IRQ_TINT4 = 13,
S5JS100_IRQ_TINT5 = 14,
S5JS100_IRQ_GPIO_INTR0 = 15,
S5JS100_IRQ_GPIO_INTR1 = 16,
S5JS100_IRQ_GPIO_INTR2 = 17,
S5JS100_IRQ_USI0 = 18,
S5JS100_IRQ_USI1 = 19,
S5JS100_IRQ_SPI = 20,
S5JS100_IRQ_I2C = 21,
S5JS100_IRQ_PWM_INT0 = 22,
S5JS100_IRQ_PWM_INT1 = 23,
S5JS100_IRQ_PWM_INT2 = 24,
S5JS100_IRQ_PWM_INT3 = 25,
S5JS100_IRQ_PWM_INT4 = 26,
S5JS100_IRQ_PPMU = 27,
S5JS100_IRQ_EFUSE_WR = 28,
S5JS100_IRQ_CM7_CTT_0 = 29,
S5JS100_IRQ_CM7_CTT_1 = 30,
S5JS100_IRQ_MAILBOX_AP_INT = 31,
S5JS100_IRQ_UART0 = 32,
S5JS100_IRQ_UART1 = 33,
S5JS100_IRQ_GPADC = 34,
S5JS100_IRQ_MCPU_WDT = 35,
S5JS100_IRQ_SSS_INT1 = 36,
S5JS100_IRQ_SSS_INT2 = 37,
S5JS100_IRQ_SSS_RESET = 38,
S5JS100_IRQ_SLEEP = 39,
S5JS100_IRQ_TSU0 = 40,
S5JS100_IRQ_TSU1 = 41,
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M7 Processor and Core Peripherals ------- */
#define __CM7_REV 0x0201U /* Core revision r2p1 */
#define __MPU_PRESENT 1 /* MPU present */
#define __DCACHE_PRESENT 1 /* 32KB d-cache */
#define __ICACHE_PRESENT 1 /* 32KB I-cache */
#define __VTOR_PRESENT 1 /* VTOR present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include <core_cm7.h> /* Processor and core peripherals */
#include "system_s5js100.h" /* System Header */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/*------------- Universal Asynchronous Receiver Transmitter (USI_UART) -----------*/
typedef struct {
__IO uint32_t ULCON; /* Offset : 0x000 (R/W) Line Control Register */
__IO uint32_t UCON; /* Offset: 0x004 (R/W) Control Register */
__IO uint32_t UFCON; /* Offset: 0x008 (R/W) FIFO Control Register */
__IO uint32_t UMCON; /* Offset: 0x00C (R/W) Modem Control Register */
__IO uint32_t UTRSTAT; /* Offset: 0x010 (R/W) Tx/Rx Status Register */
__IO uint32_t UERSTAT; /* Offset: 0x014 (R) Rx Error Status Register */
__IO uint32_t UFSTAT; /* Offset: 0x018 (R) FIFO Status Register */
__IO uint32_t UMSTAT; /* Offset: 0x01C (R) Modem Status Register */
__IO uint32_t UTXH; /* Offset: 0x020 (W) Transmit Buffer Register */
__IO uint32_t URXH; /* Offset: 0x024 (R) Receive Buffer Register */
__IO uint32_t UBRDIV; /* Offset: 0x028 (R/W) Baud Rate Divisor Register */
__IO uint32_t UFRACVAL; /* Offset: 0x02C (R/W) Divisor Fractional value Register */
__IO uint32_t UINTP; /* Offset: 0x030 (R/W) Interrupt Pending Register */
__IO uint32_t UINTS; /* Offset: 0x034 (R) Interrupt Source Register */
__IO uint32_t UINTM; /* Offset: 0x038 (R/W) Interrupt Mask Register */
__IO uint32_t RESERVED0[1];
__IO uint32_t UFTL_CONF; /* Offset: 0x040 (R/W) Filter Configuration Register */
} S5JS100_USI_UART_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct {
__IO uint32_t DR; // 0x0000
__IO uint32_t SR; // 0x0004
__IO uint32_t RESERVED0[4]; // 0x008~0x014
__IO uint32_t FR; // 0x018
__IO uint32_t RESERVED1; // 0x01c
__IO uint32_t ILPR; // 0x020
__IO uint32_t IBRD; // 0x024
__IO uint32_t FBRD; // 0x028
__IO uint32_t LCRH; // 0x02c
__IO uint32_t CR; // 0x030
__IO uint32_t IFLS; // 0x034
__IO uint32_t IMSC; // 0x038
__IO uint32_t RIS; // 0x03C
__IO uint32_t MIS; // 0x040
__IO uint32_t ICR; // 0x044
__IO uint32_t DMACR; // 0x048
__IO uint32_t MODESEL; // 0x04C
} S5JS100_UART_TypeDef;
/* S5JS100 DATA Register Definitions */
/* Line Control register ****************************************************/
#define UART_ULCON_SAMPLING_SHIFT 7
#define UART_ULCON_SAMPLING_MASK (0x1 << UART_ULCON_SAMPLING_SHIFT)
#define UART_ULCON_SAMPLING_16 (0x0 << UART_ULCON_SAMPLING_SHIFT)
#define UART_ULCON_SAMPLING_8 (0x1 << UART_ULCON_SAMPLING_SHIFT)
#define UART_ULCON_INFRARED_SHIFT 6
#define UART_ULCON_INFRARED_MASK (0x1 << UART_ULCON_INFRARED_SHIFT)
#define UART_ULCON_INFRARED_NORMAL (0x0 << UART_ULCON_INFRARED_SHIFT)
#define UART_ULCON_INFRARED_IRTXRX (0x1 << UART_ULCON_INFRARED_SHIFT)
#define UART_ULCON_PARITY_SHIFT 5
#define UART_ULCON_PARITY_MASK (0x7 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_NONE (0x0 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_ODD (0x4 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_EVEN (0x5 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_FORCE1 (0x6 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_PARITY_FORCE0 (0x7 << UART_ULCON_PARITY_SHIFT)
#define UART_ULCON_STOPBITS_SHIFT 2
#define UART_ULCON_STOPBITS_MASK (0x1 << UART_ULCON_STOPBITS_SHIFT)
#define UART_ULCON_STOPBITS_1BIT (0x0 << UART_ULCON_STOPBITS_SHIFT)
#define UART_ULCON_STOPBITS_2BITS (0x1 << UART_ULCON_STOPBITS_SHIFT)
#define UART_ULCON_DATABITS_SHIFT 0
#define UART_ULCON_DATABITS_MASK (0x3 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_5BITS (0x0 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_6BITS (0x1 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_7BITS (0x2 << UART_ULCON_DATABITS_SHIFT)
#define UART_ULCON_DATABITS_8BITS (0x3 << UART_ULCON_DATABITS_SHIFT)
/* Control register *********************************************************/
#define UART_UCON_TX_DMA_BURST_SHIFT 20
#define UART_UCON_TX_DMA_BURST_MASK (0x7 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_TX_DMA_BURST_1BYTE (0x0 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_TX_DMA_BURST_4BYTES (0x1 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_TX_DMA_BURST_8BYTES (0x2 << UART_UCON_TX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_SHIFT 16
#define UART_UCON_RX_DMA_BURST_MASK (0x7 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_1BYTE (0x0 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_4BYTES (0x1 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_8BYTES (0x2 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_DMA_BURST_16BYTES (0x3 << UART_UCON_RX_DMA_BURST_SHIFT)
#define UART_UCON_RX_TOUT_SHIFT 12
#define UART_UCON_RX_TOUT_MASK (0x7 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_8FRAMES (0x0 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_16FRAMES (0x1 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_24FRAMES (0x2 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_32FRAMES (0x3 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_40FRAMES (0x4 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_48FRAMES (0x5 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_56FRAMES (0x6 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_TOUT_64FRAMES (0x7 << UART_UCON_RX_TOUT_SHIFT)
#define UART_UCON_RX_FIFO_EMPTY_SHIFT 11
#define UART_UCON_RX_FIFO_EMPTY_MASK (0x1 << UART_UCON_RX_FIFO_EMPTY_SHIFT)
#define UART_UCON_RX_FIFO_EMPTY_DISABLE (0x0 << UART_UCON_RX_FIFO_EMPTY_SHIFT)
#define UART_UCON_RX_FIFO_EMPTY_ENABLE (0x1 << UART_UCON_RX_FIFO_EMPTY_SHIFT)
#define UART_UCON_RX_TOUT_DMAS_SHIFT 10
#define UART_UCON_RX_TOUT_DMAS_MASK (0x1 << UART_UCON_RX_TOUT_DMAS_SHIFT)
#define UART_UCON_RX_TOUT_DMAS_DISABLE (0x0 << UART_UCON_RX_TOUT_DMAS_SHIFT)
#define UART_UCON_RX_TOUT_DMAS_ENABLE (0x1 << UART_UCON_RX_TOUT_DMAS_SHIFT)
#define UART_UCON_TX_INTTYPE_SHIFT 9
#define UART_UCON_TX_INTTYPE_MASK (UART_UCON_TX_INTTYPE_SHIFT)
#define UART_UCON_TX_INTTYPE_PULSE (0x0 << UART_UCON_TX_INTTYPE_SHIFT)
#define UART_UCON_TX_INTTYPE_LEVEL (0x1 << UART_UCON_TX_INTTYPE_SHIFT)
#define UART_UCON_RX_INTTYPE_SHIFT 8
#define UART_UCON_RX_INTTYPE_MASK (UART_UCON_RX_INTTYPE_SHIFT)
#define UART_UCON_RX_INTTYPE_PULSE (0x0 << UART_UCON_RX_INTTYPE_SHIFT)
#define UART_UCON_RX_INTTYPE_LEVEL (0x1 << UART_UCON_RX_INTTYPE_SHIFT)
#define UART_UCON_RX_TOUTINT_SHIFT 7
#define UART_UCON_RX_TOUTINT_MASK (0x1 << UART_UCON_RX_TOUTINT_SHIFT)
#define UART_UCON_RX_TOUTINT_DISABLE (0x0 << UART_UCON_RX_TOUTINT_SHIFT)
#define UART_UCON_RX_TOUTINT_ENABLE (0x1 << UART_UCON_RX_TOUTINT_SHIFT)
#define UART_UCON_RX_ERRINT_SHIFT 6
#define UART_UCON_RX_ERRINT_MASK (0x1 << UART_UCON_RX_ERRINT_SHIFT)
#define UART_UCON_RX_ERRINT_DISABLE (0x0 << UART_UCON_RX_ERRINT_SHIFT)
#define UART_UCON_RX_ERRINT_ENABLE (0x1 << UART_UCON_RX_ERRINT_SHIFT)
#define UART_UCON_LOOPBACK_SHIFT 5
#define UART_UCON_LOOPBACK_MASK (0x1 << UART_UCON_LOOPBACK_SHIFT)
#define UART_UCON_LOOPBACK_DISABLE (0x0 << UART_UCON_LOOPBACK_SHIFT)
#define UART_UCON_LOOPBACK_ENABLE (0x1 << UART_UCON_LOOPBACK_SHIFT)
#define UART_UCON_SEND_BREAK_SHIFT 4
#define UART_UCON_SEND_BREAK (0x1 << UART_UCON_SEND_BREAK_SHIFT)
#define UART_UCON_TX_MODE_SHIFT 2
#define UART_UCON_TX_MODE_MASK (0x3 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_DISABLE (0x0 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_IRQPOLL (0x1 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_DMA (0x2 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_TX_MODE_RESERVED (0x3 << UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_RX_MODE_SHIFT 0
#define UART_UCON_RX_MODE_MASK (0x3 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_DISABLE (0x0 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_IRQPOLL (0x1 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_DMA (0x2 << UART_UCON_RX_MODE_SHIFT)
#define UART_UCON_RX_MODE_RESERVED (0x3 << UART_UCON_RX_MODE_SHIFT)
/* FIFO Control register ****************************************************/
#define UART_UFCON_TX_FIFO_TRIG_SHIFT 8
#define UART_UFCON_TX_FIFO_TRIG_MASK (0x7 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_0BYTE (0x0 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_2BYTES (0x1 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_4BYTES (0x2 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_6BYTES (0x3 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_8BYTES (0x4 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_10BYTES (0x4 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_12BYTES (0x5 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_14BYTES (0x6 << UART_UFCON_TX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_SHIFT 4
#define UART_UFCON_RX_FIFO_TRIG_MASK (0x7 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_0BYTE (0x0 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_2BYTES (0x1 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_4BYTES (0x2 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_6BYTES (0x3 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_8BYTES (0x4 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_10BYTES (0x4 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_12BYTES (0x5 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_14BYTES (0x6 << UART_UFCON_RX_FIFO_TRIG_SHIFT)
#define UART_UFCON_TX_FIFO_RESET_SHIFT 2
#define UART_UFCON_TX_FIFO_RESET (0x1 << UART_UFCON_TX_FIFO_RESET_SHIFT)
#define UART_UFCON_RX_FIFO_RESET_SHIFT 1
#define UART_UFCON_RX_FIFO_RESET (0x1 << UART_UFCON_RX_FIFO_RESET_SHIFT)
#define UART_UFCON_FIFO_SHIFT 0
#define UART_UFCON_FIFO_MASK (0x1 << UART_UFCON_FIFO_SHIFT)
#define UART_UFCON_FIFO_DISABLE (0x0 << UART_UFCON_FIFO_SHIFT)
#define UART_UFCON_FIFO_ENABLE (0x1 << UART_UFCON_FIFO_SHIFT)
/* Modem Control register ***************************************************/
#define UART_UMCON_RTS_TRIG_SHIFT 5
#define UART_UMCON_RTS_TRIG_MASK (0x7 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_15BYTES (0x0 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_14BYTES (0x1 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_12BYTES (0x2 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_10BYTES (0x3 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_8BYTES (0x4 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_6BYTES (0x5 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_4BYTES (0x6 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_RTS_TRIG_2BYTES (0x7 << UART_UMCON_RTS_TRIG_SHIFT)
#define UART_UMCON_AFC_SHIFT 4
#define UART_UMCON_AFC_MASK (0x1 << UART_UMCON_AFC_SHIFT)
#define UART_UMCON_AFC_DISABLE (0x0 << UART_UMCON_AFC_SHIFT)
#define UART_UMCON_AFC_ENABLE (0x1 << UART_UMCON_AFC_SHIFT)
#define UART_UMCON_MODEM_INT_SHIFT 3
#define UART_UMCON_MODEM_INT_MASK (0x1 << UART_UMCON_MODEM_INT_SHIFT)
#define UART_UMCON_MODEM_INT_DISABLE (0x0 << UART_UMCON_MODEM_INT_SHIFT)
#define UART_UMCON_MODEM_INT_ENABLE (0x1 << UART_UMCON_MODEM_INT_SHIFT)
#define UART_UMCON_REQ_TO_SEND_SHIFT 0
#define UART_UMCON_REQ_TO_SEND_MASK (0x1 << UART_UMCON_REQ_TO_SEND_SHIFT)
#define UART_UMCON_REQ_TO_SEND_HIGH (0x0 << UART_UMCON_REQ_TO_SEND_SHIFT)
#define UART_UMCON_REQ_TO_SEND_LOW (0x1 << UART_UMCON_REQ_TO_SEND_SHIFT)
/* Tx/Rx Status register ****************************************************/
#define UART_UTRSTAT_RX_FIFO_CNT_SHIFT 16
#define UART_UTRSTAT_RX_FIFO_CNT_MASK (0xff << UART_UTRSTAT_RXFIFO_CNT_SHIFT)
#define UART_UTRSTAT_TX_DMA_SHIFT 12
#define UART_UTRSTAT_TX_DMA_MASK (0xf << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_IDLE (0x0 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_BURST_REQ (0x1 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_BURST_ACK (0x2 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_BURST_NEXT (0x3 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_SINGLE_REQ (0x4 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_SINGLE_ACK (0x5 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_SINGLE_NEXT (0x6 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LBURST_REQ (0x7 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LBURST_ACK (0x8 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LSINGLE_REQ (0x9 << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_TX_DMA_LSINGLE_ACK (0xa << UART_UTRSTAT_TX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SHIFT 8
#define UART_UTRSTAT_RX_DMA_MASK (0xf << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_IDLE (0x0 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_BURST_REQ (0x1 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_BURST_ACK (0x2 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_BURST_NEXT (0x3 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SINGLE_REQ (0x4 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SINGLE_ACK (0x5 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_SINGLE_NEXT (0x6 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LBURST_REQ (0x7 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LBURST_ACK (0x8 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LSINGLE_REQ (0x9 << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_DMA_LSINGLE_ACK (0xa << UART_UTRSTAT_RX_DMA_SHIFT)
#define UART_UTRSTAT_RX_TOUT_SHIFT 3
#define UART_UTRSTAT_RX_TOUT_MASK (0x1 << UART_UTRSTAT_RX_TOUT_SHIFT)
#define UART_UTRSTAT_RX_TOUT_NONE (0x0 << UART_UTRSTAT_RX_TOUT_SHIFT)
#define UART_UTRSTAT_RX_TOUT_TIMEOUT (0x1 << UART_UTRSTAT_RX_TOUT_SHIFT)
#define UART_UTRSTAT_TX_SHIFT 2
#define UART_UTRSTAT_TX_MASK (0x1 << UART_UTRSTAT_TX_SHIFT)
#define UART_UTRSTAT_TX_NOT_EMPTY (0x0 << UART_UTRSTAT_TX_SHIFT)
#define UART_UTRSTAT_TX_EMPTY (0x1 << UART_UTRSTAT_TX_SHIFT)
#define UART_UTRSTAT_TX_BUF_SHIFT 1
#define UART_UTRSTAT_TX_BUF_MASK (0x1 << UART_UTRSTAT_TX_BUF_SHIFT)
#define UART_UTRSTAT_TX_BUF_NOT_EMPTY (0x0 << UART_UTRSTAT_TX_BUF_SHIFT)
#define UART_UTRSTAT_TX_BUF_EMPTY (0x1 << UART_UTRSTAT_TX_BUF_SHIFT)
#define UART_UTRSTAT_RX_BUF_SHIFT 0
#define UART_UTRSTAT_RX_BUF_MASK (0x1 << UART_UTRSTAT_RX_BUF_SHIFT)
#define UART_UTRSTAT_RX_BUF_NOT_EMPTY (0x1 << UART_UTRSTAT_RX_BUF_SHIFT)
#define UART_UTRSTAT_RX_BUF_EMPTY (0x0 << UART_UTRSTAT_RX_BUF_SHIFT)
/* Rx Error Status register *************************************************/
#define UART_UERSTAT_BREAK_DETECT 0x8
#define UART_UERSTAT_FRAME_ERROR 0x4
#define UART_UERSTAT_PARITY_ERROR 0x2
#define UART_UERSTAT_OVERRUN_ERROR 0x1
/* FIFO status register *****************************************************/
#define UART_UFSTAT_TX_FIFO_FULL_SHIFT 24
#define UART_UFSTAT_TX_FIFO_FULL_MASK (0x1 << UART_UFSTAT_TX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_TX_FIFO_FULL (0x1 << UART_UFSTAT_TX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_TX_FIFO_COUNT_SHIFT 16
#define UART_UFSTAT_TX_FIFO_COUNT_MASK (0xff << UART_UFSTAT_TX_FIFO_COUNT_SHIFT)
#define UART_UFSTAT_RX_FIFO_ERROR_SHIFT 9
#define UART_UFSTAT_RX_FIFO_ERROR_MASK (0x1 << UART_UFSTAT_RX_FIFO_ERROR_SHIFT)
#define UART_UFSTAT_RX_FIFO_ERROR (0x1 << UART_UFSTAT_RX_FIFO_ERROR_SHIFT)
#define UART_UFSTAT_RX_FIFO_FULL_SHIFT 8
#define UART_UFSTAT_RX_FIFO_FULL_MASK (0x1 << UART_UFSTAT_RX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_RX_FIFO_FULL (0x1 << UART_UFSTAT_RX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_RX_FIFO_COUNT_SHIFT 0
#define UART_UFSTAT_RX_FIFO_COUNT_MASK (0xff << UART_UFSTAT_RX_FIFO_COUNT_SHIFT)
/* Modem Status register ****************************************************/
#define UART_UMSTAT_DELTA_CTS_SHIFT 4
#define UART_UMSTAT_DELTA_CTS_MASK (0x1 << UART_UMSTAT_DELTA_CTS_SHIFT)
#define UART_UMSTAT_DELTA_CTS_NOCHANGE (0x0 << UART_UMSTAT_DELTA_CTS_SHIFT)
#define UART_UMSTAT_DELTA_CTS_CHANGED (0x1 << UART_UMSTAT_DELTA_CTS_SHIFT)
#define UART_UMSTAT_NCTS_SHIFT 0
#define UART_UMSTAT_NCTS_MASK (0x1 << UART_UMSTAT_NCTS_SHIFT)
#define UART_UMSTAT_NCTS_HIGH (0x0 << UART_UMSTAT_NCTS_SHIFT)
#define UART_UMSTAT_NCTS_LOW (0x1 << UART_UMSTAT_NCTS_SHIFT)
/* INterrupt Pending register ***********************************************/
#define UART_UINTP_MODEM_SHIFT 3
#define UART_UINTP_MODEM_MASK (0x1 << UART_UINTP_MODEM_SHIFT)
#define UART_UINTP_MODEM (0x1 << UART_UINTP_MODEM_SHIFT)
#define UART_UINTP_TXD_SHIFT 2
#define UART_UINTP_TXD_MASK (0x1 << UART_UINTP_TXD_SHIFT)
#define UART_UINTP_TXD (0x1 << UART_UINTP_TXD_SHIFT)
#define UART_UINTP_ERROR_SHIFT 1
#define UART_UINTP_ERROR_MASK (0x1 << UART_UINTP_ERROR_SHIFT)
#define UART_UINTP_ERROR (0x1 << UART_UINTP_ERROR_SHIFT)
#define UART_UINTP_RXD_SHIFT 0
#define UART_UINTP_RXD_MASK (0x1 << UART_UINTP_RXD_SHIFT)
#define UART_UINTP_RXD (0x1 << UART_UINTP_RXD_SHIFT)
/* Interrupt Source register ************************************************/
#define UART_UINTS_MODEM_SHIFT 3
#define UART_UINTS_MODEM_MASK (0x1 << UART_UINTS_MODEM_SHIFT)
#define UART_UINTS_MODEM (0x1 << UART_UINTS_MODEM_SHIFT)
#define UART_UINTS_TXD_SHIFT 2
#define UART_UINTS_TXD_MASK (0x1 << UART_UINTS_TXD_SHIFT)
#define UART_UINTS_TXD (0x1 << UART_UINTS_TXD_SHIFT)
#define UART_UINTS_ERROR_SHIFT 1
#define UART_UINTS_ERROR_MASK (0x1 << UART_UINTS_ERROR_SHIFT)
#define UART_UINTS_ERROR (0x1 << UART_UINTS_ERROR_SHIFT)
#define UART_UINTS_RXD_SHIFT 0
#define UART_UINTS_RXD_MASK (0x1 << UART_UINTS_RXD_SHIFT)
#define UART_UINTS_RXD (0x1 << UART_UINTS_RXD_SHIFT)
/* Interrupt Mask register **************************************************/
#define UART_UINTM_MODEM_SHIFT 3
#define UART_UINTM_MODEM_MASK (0x1 << UART_UINTM_MODEM_SHIFT)
#define UART_UINTM_TXD_SHIFT 2
#define UART_UINTM_TXD_MASK (0x1 << UART_UINTM_TXD_SHIFT)
#define UART_UINTM_ERROR_SHIFT 1
#define UART_UINTM_ERROR_MASK (0x1 << UART_UINTM_ERROR_SHIFT)
#define UART_UINTM_RXD_SHIFT 0
#define UART_UINTM_RXD_MASK (0x1 << UART_UINTM_RXD_SHIFT)
/*----------------------------- S5JS100 ATimer (TIMER) -------------------------------*/
typedef struct {
__IO uint32_t LOAD_VALUE; /* 0x0 */
__IO uint32_t CTRL; /* 0x4 */
__IO uint32_t LOAD_CON_VALUE; /* 0x8 */
__IO uint32_t INT_STATUS; /* 0xC */
__IO uint32_t INT_CLEAR; /* 0x10 */
__IO uint32_t INT_ENABLE; /* 0x14 */
__IO uint32_t RSVD3; /* 0x18 */
__IO uint32_t RSVD4; /* 0x1C */
__IO uint32_t RSVD5; /* 0x20 */
__IO uint32_t RSVD6; /* 0x24 */
__IO uint32_t RSVD7; /* 0x28 */
__IO uint32_t RSVD8; /* 0x2C */
__IO uint32_t RSVD9; /* 0x30 */
__IO uint32_t CNT_VALUE; /* 0x34 */
__IO uint32_t RSVD10; /* 0x38 */
__IO uint32_t RSVD11; /* 0x3C */
} S5JS100_TIMER_TypeDef;
/*----------------------------- S5JS100 USI (UART/SPI/I2C) -------------------------------*/
typedef struct {
__IO uint32_t CONFIG; // 0x0000
__IO uint32_t CON; // 0x0004
__IO uint32_t OPTION; // 0x008~0x014
__IO uint32_t VERSION; // 0x018
__IO uint32_t UART_VERSION; // 0x01c
__IO uint32_t SPI_VERSION; // 0x020
__IO uint32_t I2C_VERSION; // 0x024
__IO uint32_t FIFO_DEPTH; // 0x028
} S5JS100_USI_TypeDef;
#define USI_CONFIG_UART 1
#define USI_CONFIG_SPI 2
#define USI_CONFIG_I2C 4
#define USI_CON_RST 1
#define USI_OPTION_MASTER 1
#define USI_OPTION_HWACG(x) ((0x3 & (x)) << 1)
#define USI_VERSION_HW(x) ((x) & 0xFF)
#define USI_VERSION_SW(x) (((x) >> 8) & 0xFF)
#define USI_VERSION_UART(x) (((x) >> 16) & 1)
#define USI_VERSION_SPI(x) (((x) >> 17) & 1)
#define USI_VERSION_USI(x) (((x) >> 24) & 0xFF)
#define USI_TXFIFO(x) (((x) >> 16) & 0x1FF)
#define USI_RXFIFO(x) ((x) & 0x1FF)
/*-------------------- General Purpose Input Output (GPIO) -------------------*/
/*------------------- Watchdog ----------------------------------------------*/
/* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM )
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* Peripheral and SRAM base address */
#define S5JS100_FLASH_BASE 0x00000000
#define S5JS100_TIMER0_BASE 0x83012000
#define S5JS100_TIMER1_BASE 0x83012100
#define S5JS100_USI0_BASE 0x83014000
#define S5JS100_USI1_BASE 0x83015000
#define S5JS100_ACPU_SFR_PADDR 0x80000000
#define S5JS100_MCPU_ROM 0x80140000
#define S5JS100_MCPU_Debug 0x80150000
#define S5JS100_MCPU_CTI 0x80158000
#define S5JS100_PMU_ALIVE 0x81000000
#define S5JS100_SCMU 0x82000000
#define S5JS100_EFUSE 0x82010000
#define S5JS100_PMU_SYS 0x82020000
#define S5JS100_REG_PAD_CONTROL 0x82021000
#define S5JS100_ACMU 0x83000000
#define S5JS100_WDT_BASE 0x83011000
#define S5JS100_ATIMER 0x83012000
#define S5JS100_SDIOC 0x83020000
#define S5JS100_USI0 0x83014000
#define S5JS100_USI1 0x83015000
#define S5JS100_SPI 0x83016000
#define S5JS100_I2C 0x83017000
#define S5JS100_PWM 0x83018000
#define S5JS100_SSS_SS 0x83100000
#define S5JS100_SSS_MB 0x83110000
#define S5JS100_SSS_KM 0x83120000
#define S5JS100_PUF 0x83130000
#define S5JS100_PDMAC 0x83200000
#define S5JS100_ACPU_BUS_GPV 0x83300000
#define S5JS100_PPMU_ACPU 0x83400000
#define S5JS100_MCMU 0x84000000
#define S5JS100_MWDOG 0x84010000
#define S5JS100_MTIMER 0x84011000
#define S5JS100_NBSLEEP 0x84012000
#define S5JS100_USIM 0x84013000
#define S5JS100_GIC_DST 0x84100000
#define S5JS100_GIC_CPU 0x84101000
#define S5JS100_MDMAC 0x84200000
#define S5JS100_MCPU_BUS_GPV 0x84300000
#define S5JS100_MCPU_BUS_CFG 0x84400000
#define S5JS100_BUS_MONITOR 0x84401000
#define S5JS100_PPMU_MCPU 0x84410000
#define S5JS100_MIFCMU 0x85000000
#define S5JS100_BAAW 0x85010000
#define S5JS100_QSPI_SFR 0x85020000
#define S5JS100_GPADCIF0 0x85021000
#define S5JS100_GPADCIF1 0x85022000
#define S5JS100_MAILBOX 0x85023000
#define S5JS100_UART0_BASE 0x85024000
#define S5JS100_UART1_BASE 0x85025000
#define S5JS100_GPIO_BASE 0x85026000
#define S5JS100_PPMU_MCPU2MIF 0x85030000
#define S5JS100_SYS_CFG 0x85040000
#define S5JS100_MIF_BUS_GPV 0x85300000
#define S5JS100_PPMU_ACPU2MIF 0x85400000
#define S5JS100_RFIP 0x86000000
#define S5JS100_DCXO_CFG 0x87000000
#define S5JS100_MCPU2GNSS0 0x88000000
#define S5JS100_MCPU2GNSS1 0xC0000000
#define S5JS100_NB_MDM00 0xDC000000
#define S5JS100_NB_MDM01 0xDC400000
#define S5JS100_NB_MDM02 0xDC800000
#define S5JS100_NB_MDM03 0xDCC00000
#define S5JS100_NB_MDM04 0xDD000000
#define S5JS100_NB_MDM05 0xDD400000
#define S5JS100_NB_MDM06 0xDD800000
#define S5JS100_NB_MDM07 0xDDC00000
#define S5JS100_NB_MDM08 0xDE000000
#define S5JS100_NB_MDM09 0xDE400000
#define S5JS100_NB_MDM10 0xDE800000
#define S5JS100_NB_MDM11 0xDEC00000
#define S5JS100_NB_MDM12 0xDF000000
#define S5JS100_NB_MDM13 0xDF400000
#define S5JS100_ACPU_CM7_PERI 0xE0000000
#define S5JS100_BOOTMEM_MIRROR 0xFFFF0000
/* ================================================================================ */
/* ================ Peripheral declaration ================ */
/* ================================================================================ */
#define S5JS100_USI0_UART ((S5JS100_USI_UART_TypeDef *) S5JS100_USI0_BASE )
#define S5JS100_USI1_UART ((S5JS100_USI_UART_TypeDef *) S5JS100_USI1_BASE )
#define S5JS100_UART0 ((S5JS100_UART_TypeDef *) S5JS100_UART0_BASE )
#define S5JS100_UART1 ((S5JS100_UART_TypeDef *) S5JS100_UART1_BASE )
#define S5JS100_TIMER0 ((S5JS100_TIMER_TypeDef *) S5JS100_TIMER0_BASE )
#define S5JS100_TIMER1 ((S5JS100_TIMER_TypeDef *) S5JS100_TIMER1_BASE )
#define S5JS100_USI0_REG ((S5JS100_USI_TypeDef *) (S5JS100_USI0 + 0xC0))
#define S5JS100_USI1_REG ((S5JS100_USI_TypeDef *) (S5JS100_USI1 + 0xC0))
#define S5JS100_SYSCFG_USI0_CONF (*(uint32_t *)(S5JS100_SYS_CFG + 0x1030))
#define S5JS100_SYSCFG_USI0_IPCLK (*(uint32_t *)(S5JS100_SYS_CFG + 0x1034))
#define S5JS100_SYSCFG_USI1_CONF (*(uint32_t *)(S5JS100_SYS_CFG + 0x1038))
#define S5JS100_SYSCFG_USI1_IPCLK (*(uint32_t *)(S5JS100_SYS_CFG + 0x103C))
/*********************************************************************
* GPIO 2 / 3 BIT FEILD POS, OUTPUTS
*************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* S5JS100_H */

378
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100_cmu.h Normal file
View File

@@ -0,0 +1,378 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_S5JS100_S5JS100_CMU_H__
#define __ARCH_ARM_SRC_S5JS100_S5JS100_CMU_H__
#define OSCCLK ((unsigned long) 26000000)
#define SLPCLK_CP ((unsigned long) 32000)
#define S5JS100_SCMU_BASE 0x82000000
#define S5JS100_ACMU_BASE 0x83000000
#define S5JS100_MIFCMU_BASE 0x85000000
#define ACMU_AP_ACMU_CONTROLLER_OPTION ((S5JS100_ACMU_BASE + 0x800))
#define ACMU_SPARE0 ((S5JS100_ACMU_BASE + 0x880))
#define ACMU_VER ((S5JS100_ACMU_BASE + 0x890))
#define ACMU_ACMU_CONFIG0 ((S5JS100_ACMU_BASE + 0x904))
#define ACMU_ACMU_CONFIG1 ((S5JS100_ACMU_BASE + 0x908))
#define ACMU_ACMU_DFSC_CFG0 ((S5JS100_ACMU_BASE + 0x910))
#define ACMU_ACMU_DFSC_CFG1 ((S5JS100_ACMU_BASE + 0x914))
#define ACMU_ACMU_DFSC_CTL ((S5JS100_ACMU_BASE + 0x920))
#define ACMU_ACMU_BUS_ACT_MSK ((S5JS100_ACMU_BASE + 0x950))
#define ACMU_ACMU_MON_CLK ((S5JS100_ACMU_BASE + 0x9e0))
#define ACMU_MR_REGISTER_A00 ((S5JS100_ACMU_BASE + 0xa00))
#define ACMU_MR_REGISTER_A04 ((S5JS100_ACMU_BASE + 0xa04))
#define ACMU_MR_REGISTER_C00 ((S5JS100_ACMU_BASE + 0xc00))
#define ACMU_CLK_CON_MUX_CKMUXA_TIMER0_CLK ((S5JS100_ACMU_BASE + 0x1000))
#define ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK ((S5JS100_ACMU_BASE + 0x1004))
#define ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK ((S5JS100_ACMU_BASE + 0x1008))
#define ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK ((S5JS100_ACMU_BASE + 0x100c))
#define ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK ((S5JS100_ACMU_BASE + 0x1010))
#define ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK ((S5JS100_ACMU_BASE + 0x1014))
#define ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK ((S5JS100_ACMU_BASE + 0x1804))
#define ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK ((S5JS100_ACMU_BASE + 0x1808))
#define ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK ((S5JS100_ACMU_BASE + 0x1810))
#define ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK ((S5JS100_ACMU_BASE + 0x1814))
#define ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK ((S5JS100_ACMU_BASE + 0x1818))
#define ACMU_CLK_CON_BUF_BUF_AP_SRC_CLK ((S5JS100_ACMU_BASE + 0x2000))
#define ACMU_CLK_CON_GAT_CKCGA_AP_PERI_CLK ((S5JS100_ACMU_BASE + 0x2004))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_AP_CMU_IPCLKPORT_PCLK ((S5JS100_ACMU_BASE + 0x2008))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_ATIMER0_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x200c))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_ATIMER1_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x2010))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_ATIMER2_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x2014))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_ATIMER3_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x2018))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_ATIMER4_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x201c))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_ATIMER5_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x2020))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_AWDOG_IPCLKPORT_SLPCLK ((S5JS100_ACMU_BASE + 0x2024))
#define ACMU_CLK_CON_GAT_CLK_AP_UID_PWM_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x2028))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_ACPU2MCPU_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x202c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_ACPU2MIF_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x2030))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2034))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2038))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L2CLK ((S5JS100_ACMU_BASE + 0x203c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L3CLK ((S5JS100_ACMU_BASE + 0x2040))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_APMEM_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2044))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ATIMER0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2048))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ATIMER1_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x204c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ATIMER2_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2050))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ATIMER3_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2054))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ATIMER4_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2058))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_ATIMER5_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x205c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_AWDOG_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2060))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_BS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2064))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_BS_MEM_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2068))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_CM7_IPCLKPORT_L1CLK ((S5JS100_ACMU_BASE + 0x206c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_CM7_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2070))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_CS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2074))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_CS_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2078))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_I2C0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x207c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_PDMA_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2080))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_PUF_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2084))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_PWM_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x2088))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x208c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x2090))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_SDIO_HCLK ((S5JS100_ACMU_BASE + 0x2094))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SPI0_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x2098))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SPI0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x209c))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SSS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x20a0))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SSS_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x20a4))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_SSS_IPCLKPORT_SLVHCLK ((S5JS100_ACMU_BASE + 0x20a8))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_USI0_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x20ac))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_USI0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x20b0))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_USI1_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x20b4))
#define ACMU_CLK_CON_GAT_GOUT_AP_UID_USI1_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x20b8))
#define ACMU_DMYQCH_CON_ABUS_QCH_PPMU_CLK ((S5JS100_ACMU_BASE + 0x3000))
#define ACMU_DMYQCH_CON_ATIMER0_QCH ((S5JS100_ACMU_BASE + 0x3004))
#define ACMU_DMYQCH_CON_ATIMER1_QCH ((S5JS100_ACMU_BASE + 0x3008))
#define ACMU_DMYQCH_CON_ATIMER2_QCH ((S5JS100_ACMU_BASE + 0x300c))
#define ACMU_DMYQCH_CON_ATIMER3_QCH ((S5JS100_ACMU_BASE + 0x3010))
#define ACMU_DMYQCH_CON_ATIMER4_QCH ((S5JS100_ACMU_BASE + 0x3014))
#define ACMU_DMYQCH_CON_ATIMER5_QCH ((S5JS100_ACMU_BASE + 0x3018))
#define ACMU_DMYQCH_CON_AWDOG_QCH ((S5JS100_ACMU_BASE + 0x301c))
#define ACMU_DMYQCH_CON_CS_QCH ((S5JS100_ACMU_BASE + 0x3020))
#define ACMU_DMYQCH_CON_PUF_QCH ((S5JS100_ACMU_BASE + 0x3024))
#define ACMU_DMYQCH_CON_PWM_QCH_CLK ((S5JS100_ACMU_BASE + 0x3028))
#define ACMU_DMYQCH_CON_SDIO_QCH_HCLK ((S5JS100_ACMU_BASE + 0x302c))
#define ACMU_DMYQCH_CON_SPI0_QCH ((S5JS100_ACMU_BASE + 0x3030))
#define ACMU_DMYQCH_CON_SSS_QCH_DEBUG ((S5JS100_ACMU_BASE + 0x3034))
#define ACMU_QCH_CON_ABUS_QCH_ACPU2MCPU_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x3038))
#define ACMU_QCH_CON_ABUS_QCH_ACPU2MIF_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x303c))
#define ACMU_QCH_CON_ABUS_QCH_L2CLK ((S5JS100_ACMU_BASE + 0x3040))
#define ACMU_QCH_CON_APMEM_QCH ((S5JS100_ACMU_BASE + 0x3044))
#define ACMU_QCH_CON_AP_CMU_QCH ((S5JS100_ACMU_BASE + 0x3048))
#define ACMU_QCH_CON_BS_MEM_QCH ((S5JS100_ACMU_BASE + 0x304c))
#define ACMU_QCH_CON_BS_QCH ((S5JS100_ACMU_BASE + 0x3050))
#define ACMU_QCH_CON_CM7_QCH ((S5JS100_ACMU_BASE + 0x3054))
#define ACMU_QCH_CON_I2C0_QCH ((S5JS100_ACMU_BASE + 0x3058))
#define ACMU_QCH_CON_PDMA_QCH ((S5JS100_ACMU_BASE + 0x305c))
#define ACMU_QCH_CON_PWM_QCH_L3CLK ((S5JS100_ACMU_BASE + 0x3060))
#define ACMU_QCH_CON_SDIO_QCH ((S5JS100_ACMU_BASE + 0x3064))
#define ACMU_QCH_CON_SSS_QCH ((S5JS100_ACMU_BASE + 0x3068))
#define ACMU_QCH_CON_USI0_QCH ((S5JS100_ACMU_BASE + 0x306c))
#define ACMU_QCH_CON_USI1_QCH ((S5JS100_ACMU_BASE + 0x3070))
#define ACMU_QUEUE_CTRL_REG_AP_CMU ((S5JS100_ACMU_BASE + 0x3c00))
#define ACMU_DBG_NFO_CKMUXA_TIMER0_CLK ((S5JS100_ACMU_BASE + 0x5000))
#define ACMU_DBG_NFO_CKMUXA_TIMER1_CLK ((S5JS100_ACMU_BASE + 0x5004))
#define ACMU_DBG_NFO_CKMUXA_TIMER2_CLK ((S5JS100_ACMU_BASE + 0x5008))
#define ACMU_DBG_NFO_CKMUXA_TIMER3_CLK ((S5JS100_ACMU_BASE + 0x500c))
#define ACMU_DBG_NFO_CKMUXA_TIMER4_CLK ((S5JS100_ACMU_BASE + 0x5010))
#define ACMU_DBG_NFO_CKMUXA_TIMER5_CLK ((S5JS100_ACMU_BASE + 0x5014))
#define ACMU_DBG_NFO_CKDIVA_ACPU_CLK ((S5JS100_ACMU_BASE + 0x5800))
#define ACMU_DBG_NFO_CKDIVA_SDIO_CLK ((S5JS100_ACMU_BASE + 0x5808))
#define ACMU_DBG_NFO_CKDIVA_SPI0_CLK ((S5JS100_ACMU_BASE + 0x580c))
#define ACMU_DBG_NFO_CKDIVA_USI0_CLK ((S5JS100_ACMU_BASE + 0x5814))
#define ACMU_DBG_NFO_CKDIVA_USI1_CLK ((S5JS100_ACMU_BASE + 0x5818))
#define ACMU_DBG_NFO_BUF_AP_SRC_CLK ((S5JS100_ACMU_BASE + 0x6000))
#define ACMU_DBG_NFO_CKCGA_AP_PERI_CLK ((S5JS100_ACMU_BASE + 0x6004))
#define ACMU_DBG_NFO_CLK_AP_UID_AP_CMU_IPCLKPORT_PCLK ((S5JS100_ACMU_BASE + 0x6008))
#define ACMU_DBG_NFO_CLK_AP_UID_ATIMER0_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x600c))
#define ACMU_DBG_NFO_CLK_AP_UID_ATIMER1_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x6010))
#define ACMU_DBG_NFO_CLK_AP_UID_ATIMER2_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x6014))
#define ACMU_DBG_NFO_CLK_AP_UID_ATIMER3_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x6018))
#define ACMU_DBG_NFO_CLK_AP_UID_ATIMER4_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x601c))
#define ACMU_DBG_NFO_CLK_AP_UID_ATIMER5_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x6020))
#define ACMU_DBG_NFO_CLK_AP_UID_AWDOG_IPCLKPORT_SLPCLK ((S5JS100_ACMU_BASE + 0x6024))
#define ACMU_DBG_NFO_CLK_AP_UID_PWM_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x6028))
#define ACMU_DBG_NFO_GOUT_AP_UID_ABUS_IPCLKPORT_ACPU2MCPU_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x602c))
#define ACMU_DBG_NFO_GOUT_AP_UID_ABUS_IPCLKPORT_ACPU2MIF_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x6030))
#define ACMU_DBG_NFO_GOUT_AP_UID_ABUS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6034))
#define ACMU_DBG_NFO_GOUT_AP_UID_ABUS_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6038))
#define ACMU_DBG_NFO_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L2CLK ((S5JS100_ACMU_BASE + 0x603c))
#define ACMU_DBG_NFO_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L3CLK ((S5JS100_ACMU_BASE + 0x6040))
#define ACMU_DBG_NFO_GOUT_AP_UID_APMEM_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6044))
#define ACMU_DBG_NFO_GOUT_AP_UID_ATIMER0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6048))
#define ACMU_DBG_NFO_GOUT_AP_UID_ATIMER1_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x604c))
#define ACMU_DBG_NFO_GOUT_AP_UID_ATIMER2_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6050))
#define ACMU_DBG_NFO_GOUT_AP_UID_ATIMER3_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6054))
#define ACMU_DBG_NFO_GOUT_AP_UID_ATIMER4_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6058))
#define ACMU_DBG_NFO_GOUT_AP_UID_ATIMER5_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x605c))
#define ACMU_DBG_NFO_GOUT_AP_UID_AWDOG_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6060))
#define ACMU_DBG_NFO_GOUT_AP_UID_BS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6064))
#define ACMU_DBG_NFO_GOUT_AP_UID_BS_MEM_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6068))
#define ACMU_DBG_NFO_GOUT_AP_UID_CM7_IPCLKPORT_L1CLK ((S5JS100_ACMU_BASE + 0x606c))
#define ACMU_DBG_NFO_GOUT_AP_UID_CM7_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6070))
#define ACMU_DBG_NFO_GOUT_AP_UID_CS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6074))
#define ACMU_DBG_NFO_GOUT_AP_UID_CS_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6078))
#define ACMU_DBG_NFO_GOUT_AP_UID_I2C0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x607c))
#define ACMU_DBG_NFO_GOUT_AP_UID_PDMA_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6080))
#define ACMU_DBG_NFO_GOUT_AP_UID_PUF_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6084))
#define ACMU_DBG_NFO_GOUT_AP_UID_PWM_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x6088))
#define ACMU_DBG_NFO_GOUT_AP_UID_SDIO_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x608c))
#define ACMU_DBG_NFO_GOUT_AP_UID_SDIO_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x6090))
#define ACMU_DBG_NFO_GOUT_AP_UID_SDIO_IPCLKPORT_SDIO_HCLK ((S5JS100_ACMU_BASE + 0x6094))
#define ACMU_DBG_NFO_GOUT_AP_UID_SPI0_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x6098))
#define ACMU_DBG_NFO_GOUT_AP_UID_SPI0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x609c))
#define ACMU_DBG_NFO_GOUT_AP_UID_SSS_IPCLKPORT_L2CLK ((S5JS100_ACMU_BASE + 0x60a0))
#define ACMU_DBG_NFO_GOUT_AP_UID_SSS_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x60a4))
#define ACMU_DBG_NFO_GOUT_AP_UID_SSS_IPCLKPORT_SLVHCLK ((S5JS100_ACMU_BASE + 0x60a8))
#define ACMU_DBG_NFO_GOUT_AP_UID_USI0_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x60ac))
#define ACMU_DBG_NFO_GOUT_AP_UID_USI0_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x60b0))
#define ACMU_DBG_NFO_GOUT_AP_UID_USI1_IPCLKPORT_CLK ((S5JS100_ACMU_BASE + 0x60b4))
#define ACMU_DBG_NFO_GOUT_AP_UID_USI1_IPCLKPORT_L3CLK ((S5JS100_ACMU_BASE + 0x60b8))
#define ACMU_DBG_NFO_DMYQCH_CON_ABUS_QCH_PPMU_CLK ((S5JS100_ACMU_BASE + 0x7000))
#define ACMU_DBG_NFO_DMYQCH_CON_ATIMER0_QCH ((S5JS100_ACMU_BASE + 0x7004))
#define ACMU_DBG_NFO_DMYQCH_CON_ATIMER1_QCH ((S5JS100_ACMU_BASE + 0x7008))
#define ACMU_DBG_NFO_DMYQCH_CON_ATIMER2_QCH ((S5JS100_ACMU_BASE + 0x700c))
#define ACMU_DBG_NFO_DMYQCH_CON_ATIMER3_QCH ((S5JS100_ACMU_BASE + 0x7010))
#define ACMU_DBG_NFO_DMYQCH_CON_ATIMER4_QCH ((S5JS100_ACMU_BASE + 0x7014))
#define ACMU_DBG_NFO_DMYQCH_CON_ATIMER5_QCH ((S5JS100_ACMU_BASE + 0x7018))
#define ACMU_DBG_NFO_DMYQCH_CON_AWDOG_QCH ((S5JS100_ACMU_BASE + 0x701c))
#define ACMU_DBG_NFO_DMYQCH_CON_CS_QCH ((S5JS100_ACMU_BASE + 0x7020))
#define ACMU_DBG_NFO_DMYQCH_CON_PUF_QCH ((S5JS100_ACMU_BASE + 0x7024))
#define ACMU_DBG_NFO_DMYQCH_CON_PWM_QCH_CLK ((S5JS100_ACMU_BASE + 0x7028))
#define ACMU_DBG_NFO_DMYQCH_CON_SDIO_QCH_HCLK ((S5JS100_ACMU_BASE + 0x702c))
#define ACMU_DBG_NFO_DMYQCH_CON_SPI0_QCH ((S5JS100_ACMU_BASE + 0x7030))
#define ACMU_DBG_NFO_DMYQCH_CON_SSS_QCH_DEBUG ((S5JS100_ACMU_BASE + 0x7034))
#define ACMU_DBG_NFO_QCH_CON_ABUS_QCH_ACPU2MCPU_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x7038))
#define ACMU_DBG_NFO_QCH_CON_ABUS_QCH_ACPU2MIF_LH_SI_L2CLK ((S5JS100_ACMU_BASE + 0x703c))
#define ACMU_DBG_NFO_QCH_CON_ABUS_QCH_L2CLK ((S5JS100_ACMU_BASE + 0x7040))
#define ACMU_DBG_NFO_QCH_CON_APMEM_QCH ((S5JS100_ACMU_BASE + 0x7044))
#define ACMU_DBG_NFO_QCH_CON_AP_CMU_QCH ((S5JS100_ACMU_BASE + 0x7048))
#define ACMU_DBG_NFO_QCH_CON_BS_MEM_QCH ((S5JS100_ACMU_BASE + 0x704c))
#define ACMU_DBG_NFO_QCH_CON_BS_QCH ((S5JS100_ACMU_BASE + 0x7050))
#define ACMU_DBG_NFO_QCH_CON_CM7_QCH ((S5JS100_ACMU_BASE + 0x7054))
#define ACMU_DBG_NFO_QCH_CON_I2C0_QCH ((S5JS100_ACMU_BASE + 0x7058))
#define ACMU_DBG_NFO_QCH_CON_PDMA_QCH ((S5JS100_ACMU_BASE + 0x705c))
#define ACMU_DBG_NFO_QCH_CON_PWM_QCH_L3CLK ((S5JS100_ACMU_BASE + 0x7060))
#define ACMU_DBG_NFO_QCH_CON_SDIO_QCH ((S5JS100_ACMU_BASE + 0x7064))
#define ACMU_DBG_NFO_QCH_CON_SSS_QCH ((S5JS100_ACMU_BASE + 0x7068))
#define ACMU_DBG_NFO_QCH_CON_USI0_QCH ((S5JS100_ACMU_BASE + 0x706c))
#define ACMU_DBG_NFO_QCH_CON_USI1_QCH ((S5JS100_ACMU_BASE + 0x7070))
#define SCMU_PLL_LOCKTIME_UPLL ((S5JS100_SCMU_BASE + 0x0))
#define SCMU_PLL_CON0_UPLL ((S5JS100_SCMU_BASE + 0x100))
#define SCMU_PLL_CON1_UPLL ((S5JS100_SCMU_BASE + 0x104))
#define SCMU_PLL_CON2_UPLL ((S5JS100_SCMU_BASE + 0x108))
#define SCMU_PLL_CON4_UPLL ((S5JS100_SCMU_BASE + 0x110))
#define SCMU_SYS_SCMU_CONTROLLER_OPTION ((S5JS100_SCMU_BASE + 0x800))
#define SCMU_SPARE0 ((S5JS100_SCMU_BASE + 0x880))
#define SCMU_VER ((S5JS100_SCMU_BASE + 0x890))
#define SCMU_SCMU_MON_CLK ((S5JS100_SCMU_BASE + 0x9e0))
#define SCMU_MR_REGISTER_A04 ((S5JS100_SCMU_BASE + 0xa04))
#define SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP ((S5JS100_SCMU_BASE + 0x1800))
#define SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_CP ((S5JS100_SCMU_BASE + 0x1804))
#define SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_GNSS ((S5JS100_SCMU_BASE + 0x1808))
#define SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF ((S5JS100_SCMU_BASE + 0x180c))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_EFUSE_IPCLKPORT_CLK ((S5JS100_SCMU_BASE + 0x2000))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_EFUSE_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x2004))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_GNSS_IPCLKPORT_CLK ((S5JS100_SCMU_BASE + 0x2008))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_PADCON_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x200c))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_PMU_SYS_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x2010))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_SYSBUS_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x2014))
#define SCMU_CLK_CON_GAT_CLK_SYS_UID_SYS_CMU_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x2018))
#define SCMU_CLK_CON_GAT_CP_SRC_CLK ((S5JS100_SCMU_BASE + 0x201c))
#define SCMU_CLK_CON_GAT_GNSS_SRC_CLK ((S5JS100_SCMU_BASE + 0x2020))
#define SCMU_CLK_CON_GAT_MIF_SRC_CLK ((S5JS100_SCMU_BASE + 0x2024))
#define SCMU_DMYQCH_CON_EFUSE_QCH_CLK ((S5JS100_SCMU_BASE + 0x3000))
#define SCMU_DMYQCH_CON_GNSS_QCH ((S5JS100_SCMU_BASE + 0x3004))
#define SCMU_DMYQCH_CON_PADCON_QCH ((S5JS100_SCMU_BASE + 0x3008))
#define SCMU_DMYQCH_CON_PMU_SYS_QCH ((S5JS100_SCMU_BASE + 0x300c))
#define SCMU_DMYQCH_CON_SYSBUS_QCH ((S5JS100_SCMU_BASE + 0x3010))
#define SCMU_QCH_CON_EFUSE_QCH_PCLK ((S5JS100_SCMU_BASE + 0x3014))
#define SCMU_QCH_CON_SYS_CMU_QCH ((S5JS100_SCMU_BASE + 0x3018))
#define SCMU_QUEUE_CTRL_REG_SYS_CMU ((S5JS100_SCMU_BASE + 0x3c00))
#define SCMU_DBG_NFO_UPLL ((S5JS100_SCMU_BASE + 0x4100))
#define SCMU_DBG_NFO_CKDIVS_UPLL_CLK_AP ((S5JS100_SCMU_BASE + 0x5800))
#define SCMU_DBG_NFO_CKDIVS_UPLL_CLK_CP ((S5JS100_SCMU_BASE + 0x5804))
#define SCMU_DBG_NFO_CKDIVS_UPLL_CLK_GNSS ((S5JS100_SCMU_BASE + 0x5808))
#define SCMU_DBG_NFO_CKDIVS_UPLL_CLK_MIF ((S5JS100_SCMU_BASE + 0x580c))
#define SCMU_DBG_NFO_CLK_SYS_UID_EFUSE_IPCLKPORT_CLK ((S5JS100_SCMU_BASE + 0x6000))
#define SCMU_DBG_NFO_CLK_SYS_UID_EFUSE_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x6004))
#define SCMU_DBG_NFO_CLK_SYS_UID_GNSS_IPCLKPORT_CLK ((S5JS100_SCMU_BASE + 0x6008))
#define SCMU_DBG_NFO_CLK_SYS_UID_PADCON_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x600c))
#define SCMU_DBG_NFO_CLK_SYS_UID_PMU_SYS_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x6010))
#define SCMU_DBG_NFO_CLK_SYS_UID_SYSBUS_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x6014))
#define SCMU_DBG_NFO_CLK_SYS_UID_SYS_CMU_IPCLKPORT_PCLK ((S5JS100_SCMU_BASE + 0x6018))
#define SCMU_DBG_NFO_CP_SRC_CLK ((S5JS100_SCMU_BASE + 0x601c))
#define SCMU_DBG_NFO_GNSS_SRC_CLK ((S5JS100_SCMU_BASE + 0x6020))
#define SCMU_DBG_NFO_MIF_SRC_CLK ((S5JS100_SCMU_BASE + 0x6024))
#define SCMU_DBG_NFO_DMYQCH_CON_EFUSE_QCH_CLK ((S5JS100_SCMU_BASE + 0x7000))
#define SCMU_DBG_NFO_DMYQCH_CON_GNSS_QCH ((S5JS100_SCMU_BASE + 0x7004))
#define SCMU_DBG_NFO_DMYQCH_CON_PADCON_QCH ((S5JS100_SCMU_BASE + 0x7008))
#define SCMU_DBG_NFO_DMYQCH_CON_PMU_SYS_QCH ((S5JS100_SCMU_BASE + 0x700c))
#define SCMU_DBG_NFO_DMYQCH_CON_SYSBUS_QCH ((S5JS100_SCMU_BASE + 0x7010))
#define SCMU_DBG_NFO_QCH_CON_EFUSE_QCH_PCLK ((S5JS100_SCMU_BASE + 0x7014))
#define SCMU_DBG_NFO_QCH_CON_SYS_CMU_QCH ((S5JS100_SCMU_BASE + 0x7018))
#define MIFCMU_MIF_MIFCMU_CONTROLLER_OPTION ((S5JS100_MIFCMU_BASE + 0x800))
#define MIFCMU_SPARE0 ((S5JS100_MIFCMU_BASE + 0x880))
#define MIFCMU_VER ((S5JS100_MIFCMU_BASE + 0x890))
#define MIFCMU_MIFCMU_MON_CLK ((S5JS100_MIFCMU_BASE + 0x9e0))
#define MIFCMU_MR_REGISTER_A00 ((S5JS100_MIFCMU_BASE + 0xa00))
#define MIFCMU_MR_REGISTER_A04 ((S5JS100_MIFCMU_BASE + 0xa04))
#define MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK ((S5JS100_MIFCMU_BASE + 0x1800))
#define MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK ((S5JS100_MIFCMU_BASE + 0x1804))
#define MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK ((S5JS100_MIFCMU_BASE + 0x1808))
#define MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK ((S5JS100_MIFCMU_BASE + 0x180c))
#define MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK ((S5JS100_MIFCMU_BASE + 0x1810))
#define MIFCMU_CLK_CON_BUF_CKBUF_MIF_SRC_CLK ((S5JS100_MIFCMU_BASE + 0x2000))
#define MIFCMU_CLK_CON_GAT_CLK_MIF_UID_GPADCIF_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x2004))
#define MIFCMU_CLK_CON_GAT_CLK_MIF_UID_MIF_CMU_IPCLKPORT_PCLK ((S5JS100_MIFCMU_BASE + 0x2008))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_GPADCIF_IPCLKPORT_S0_L3CLK ((S5JS100_MIFCMU_BASE + 0x200c))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_GPADCIF_IPCLKPORT_S1_L3CLK ((S5JS100_MIFCMU_BASE + 0x2010))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_GPIO_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x2014))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_IPCMEM_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x2018))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MBOX_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x201c))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_ACPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x2020))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_BAAW_SFR_L3CLK ((S5JS100_MIFCMU_BASE + 0x2024))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x2028))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_MCPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x202c))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L2CLK ((S5JS100_MIFCMU_BASE + 0x2030))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L3CLK ((S5JS100_MIFCMU_BASE + 0x2034))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L2CLK ((S5JS100_MIFCMU_BASE + 0x2038))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L3CLK ((S5JS100_MIFCMU_BASE + 0x203c))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_QSPI_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x2040))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_QSPI_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x2044))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SMC_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x2048))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SMC_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x204c))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SYSCFG_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x2050))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_UART0_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x2054))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_UART0_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x2058))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_UART1_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x205c))
#define MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_UART1_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x2060))
#define MIFCMU_DMYQCH_CON_GPADCIF_QCH_CLK ((S5JS100_MIFCMU_BASE + 0x3000))
#define MIFCMU_DMYQCH_CON_GPIO_QCH ((S5JS100_MIFCMU_BASE + 0x3004))
#define MIFCMU_DMYQCH_CON_MIFBUS_QCH_PPMU_ACPU2MIF_CLK ((S5JS100_MIFCMU_BASE + 0x3008))
#define MIFCMU_DMYQCH_CON_MIFBUS_QCH_PPMU_MCPU2MIF_CLK ((S5JS100_MIFCMU_BASE + 0x300c))
#define MIFCMU_DMYQCH_CON_QSPI_QCH ((S5JS100_MIFCMU_BASE + 0x3010))
#define MIFCMU_DMYQCH_CON_SMC_QCH ((S5JS100_MIFCMU_BASE + 0x3014))
#define MIFCMU_DMYQCH_CON_SYSCFG_QCH ((S5JS100_MIFCMU_BASE + 0x3018))
#define MIFCMU_DMYQCH_CON_UART0_QCH ((S5JS100_MIFCMU_BASE + 0x301c))
#define MIFCMU_DMYQCH_CON_UART1_QCH ((S5JS100_MIFCMU_BASE + 0x3020))
#define MIFCMU_QCH_CON_GPADCIF_QCH_S0_L3CLK ((S5JS100_MIFCMU_BASE + 0x3024))
#define MIFCMU_QCH_CON_GPADCIF_QCH_S1_L3CLK ((S5JS100_MIFCMU_BASE + 0x3028))
#define MIFCMU_QCH_CON_IPCMEM_QCH ((S5JS100_MIFCMU_BASE + 0x302c))
#define MIFCMU_QCH_CON_MBOX_QCH ((S5JS100_MIFCMU_BASE + 0x3030))
#define MIFCMU_QCH_CON_MIFBUS_QCH_ACPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x3034))
#define MIFCMU_QCH_CON_MIFBUS_QCH_BAAW_SFR_L3CLK ((S5JS100_MIFCMU_BASE + 0x3038))
#define MIFCMU_QCH_CON_MIFBUS_QCH_L2CLK ((S5JS100_MIFCMU_BASE + 0x303c))
#define MIFCMU_QCH_CON_MIFBUS_QCH_MCPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x3040))
#define MIFCMU_QCH_CON_MIF_CMU_QCH ((S5JS100_MIFCMU_BASE + 0x3044))
#define MIFCMU_QUEUE_CTRL_REG_MIF_CMU ((S5JS100_MIFCMU_BASE + 0x3c00))
#define MIFCMU_DBG_NFO_CKDIVF_MIF_SRC_CLK ((S5JS100_MIFCMU_BASE + 0x5800))
#define MIFCMU_DBG_NFO_CKDIVF_QSPI_CLK ((S5JS100_MIFCMU_BASE + 0x5804))
#define MIFCMU_DBG_NFO_CKDIVF_SMC_CLK ((S5JS100_MIFCMU_BASE + 0x5808))
#define MIFCMU_DBG_NFO_CKDIVF_UART0_CLK ((S5JS100_MIFCMU_BASE + 0x580c))
#define MIFCMU_DBG_NFO_CKDIVF_UART1_CLK ((S5JS100_MIFCMU_BASE + 0x5810))
#define MIFCMU_DBG_NFO_CKBUF_MIF_SRC_CLK ((S5JS100_MIFCMU_BASE + 0x6000))
#define MIFCMU_DBG_NFO_CLK_MIF_UID_GPADCIF_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x6004))
#define MIFCMU_DBG_NFO_CLK_MIF_UID_MIF_CMU_IPCLKPORT_PCLK ((S5JS100_MIFCMU_BASE + 0x6008))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_GPADCIF_IPCLKPORT_S0_L3CLK ((S5JS100_MIFCMU_BASE + 0x600c))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_GPADCIF_IPCLKPORT_S1_L3CLK ((S5JS100_MIFCMU_BASE + 0x6010))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_GPIO_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x6014))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_IPCMEM_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x6018))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MBOX_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x601c))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_ACPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x6020))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_BAAW_SFR_L3CLK ((S5JS100_MIFCMU_BASE + 0x6024))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x6028))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_MCPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x602c))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L2CLK ((S5JS100_MIFCMU_BASE + 0x6030))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L3CLK ((S5JS100_MIFCMU_BASE + 0x6034))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L2CLK ((S5JS100_MIFCMU_BASE + 0x6038))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L3CLK ((S5JS100_MIFCMU_BASE + 0x603c))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_QSPI_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x6040))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_QSPI_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x6044))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_SMC_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x6048))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_SMC_IPCLKPORT_L2CLK ((S5JS100_MIFCMU_BASE + 0x604c))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_SYSCFG_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x6050))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_UART0_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x6054))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_UART0_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x6058))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_UART1_IPCLKPORT_CLK ((S5JS100_MIFCMU_BASE + 0x605c))
#define MIFCMU_DBG_NFO_GOUT_MIF_UID_UART1_IPCLKPORT_L3CLK ((S5JS100_MIFCMU_BASE + 0x6060))
#define MIFCMU_DBG_NFO_DMYQCH_CON_GPADCIF_QCH_CLK ((S5JS100_MIFCMU_BASE + 0x7000))
#define MIFCMU_DBG_NFO_DMYQCH_CON_GPIO_QCH ((S5JS100_MIFCMU_BASE + 0x7004))
#define MIFCMU_DBG_NFO_DMYQCH_CON_MIFBUS_QCH_PPMU_ACPU2MIF_CLK ((S5JS100_MIFCMU_BASE + 0x7008))
#define MIFCMU_DBG_NFO_DMYQCH_CON_MIFBUS_QCH_PPMU_MCPU2MIF_CLK ((S5JS100_MIFCMU_BASE + 0x700c))
#define MIFCMU_DBG_NFO_DMYQCH_CON_QSPI_QCH ((S5JS100_MIFCMU_BASE + 0x7010))
#define MIFCMU_DBG_NFO_DMYQCH_CON_SMC_QCH ((S5JS100_MIFCMU_BASE + 0x7014))
#define MIFCMU_DBG_NFO_DMYQCH_CON_SYSCFG_QCH ((S5JS100_MIFCMU_BASE + 0x7018))
#define MIFCMU_DBG_NFO_DMYQCH_CON_UART0_QCH ((S5JS100_MIFCMU_BASE + 0x701c))
#define MIFCMU_DBG_NFO_DMYQCH_CON_UART1_QCH ((S5JS100_MIFCMU_BASE + 0x7020))
#define MIFCMU_DBG_NFO_QCH_CON_GPADCIF_QCH_S0_L3CLK ((S5JS100_MIFCMU_BASE + 0x7024))
#define MIFCMU_DBG_NFO_QCH_CON_GPADCIF_QCH_S1_L3CLK ((S5JS100_MIFCMU_BASE + 0x7028))
#define MIFCMU_DBG_NFO_QCH_CON_IPCMEM_QCH ((S5JS100_MIFCMU_BASE + 0x702c))
#define MIFCMU_DBG_NFO_QCH_CON_MBOX_QCH ((S5JS100_MIFCMU_BASE + 0x7030))
#define MIFCMU_DBG_NFO_QCH_CON_MIFBUS_QCH_ACPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x7034))
#define MIFCMU_DBG_NFO_QCH_CON_MIFBUS_QCH_BAAW_SFR_L3CLK ((S5JS100_MIFCMU_BASE + 0x7038))
#define MIFCMU_DBG_NFO_QCH_CON_MIFBUS_QCH_L2CLK ((S5JS100_MIFCMU_BASE + 0x703c))
#define MIFCMU_DBG_NFO_QCH_CON_MIFBUS_QCH_MCPU2MIF_LH_MI_L2CLK ((S5JS100_MIFCMU_BASE + 0x7040))
#define MIFCMU_DBG_NFO_QCH_CON_MIF_CMU_QCH ((S5JS100_MIFCMU_BASE + 0x7044))
#endif /* __ARCH_ARM_SRC_S5JS100_S5JS100_CMU_H__ */

27
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100_hal.h Normal file
View File

@@ -0,0 +1,27 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
typedef enum {
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;

479
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100_pwrcal.c Normal file
View File

@@ -0,0 +1,479 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include "cmsis.h"
unsigned int cal_clk_is_enabled(unsigned int id)
{
return 0;
}
int cal_clk_setrate(unsigned int id, unsigned long rate)
{
unsigned long parents;
unsigned int div;
unsigned int sel;
switch (id) {
case p1_upll:
if (rate == 0) {
modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 0 << 4);
modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 0);
} else if ((getreg32(SCMU_PLL_CON0_UPLL) & (1 << 31)) == 0) {
modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 1);
while (!(getreg32(SCMU_PLL_CON0_UPLL) & (1 << 29))) {
};
modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 1 << 4);
}
break;
case m1_timer1:
if ((rate >= OSCCLK) || (rate == 0)) {
sel = 0;
} else {
sel = 1;
}
modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK, 1, sel);
break;
case m1_timer2:
if ((rate >= OSCCLK) || (rate == 0)) {
sel = 0;
} else {
sel = 1;
}
modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK, 1, sel);
break;
case m1_timer3:
if ((rate >= OSCCLK) || (rate == 0)) {
sel = 0;
} else {
sel = 1;
}
modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK, 1, sel);
break;
case m1_timer4:
if ((rate >= OSCCLK) || (rate == 0)) {
sel = 0;
} else {
sel = 1;
}
modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK, 1, sel);
break;
case m1_timer5:
if ((rate >= OSCCLK) || (rate == 0)) {
sel = 0;
} else {
sel = 1;
}
modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK, 1, sel);
break;
case d1_upll_clk_ap:
parents = cal_clk_getrate(p1_upll);
div = (parents + rate - 1) / rate;
if (div > 0xf) {
div = 0xf;
}
modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP, 0xF, div - 1);
break;
case d1_upll_clk_cp:
parents = cal_clk_getrate(p1_upll);
div = (parents + rate - 1) / rate;
if (div > 0xf) {
div = 0xf;
}
modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_CP, 0xF, div - 1);
break;
case d1_upll_clk_mif:
parents = cal_clk_getrate(p1_upll);
div = (parents + rate - 1) / rate;
if (div > 0xf) {
div = 0xf;
}
modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF, 0xF, div - 1);
break;
case d1_upll_clk_gnss:
parents = cal_clk_getrate(p1_upll);
div = (parents + rate - 1) / rate;
if (div > 0xf) {
div = 0xf;
}
modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_GNSS, 0xF, div - 1);
break;
case d1_acpu_l1:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x1f) {
div = 0x1f;
}
modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, 0x1F, div - 1);
break;
case d1_acpu_l2:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x1f) {
div = 0x1f;
}
modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, 0x1F << 8, (div - 1) << 8);
break;
case d1_acpu_l3:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x1f) {
div = 0x1f;
}
modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, 0x1F << 16, (div - 1) << 16);
break;
case d1_sdio:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x7f) {
div = 0x7f;
}
modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK, 0x7F, div - 1);
break;
case d1_spi0:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK, 0x1F, div - 1);
break;
case d1_usi0:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK, 0x1F, div - 1);
break;
case d1_usi1:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK, 0x1F, div - 1);
break;
case d1_mif_l2:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (parents + rate - 1) / rate;
if (div > 0x1f) {
div = 0x1f;
}
modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, 0x1F << 0, (div - 1) << 0);
break;
case d1_mif_l3:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (parents + rate - 1) / rate;
if (div > 0x1f) {
div = 0x1f;
}
modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, 0x1F << 8, (div - 1) << 8);
break;
case d1_qspi:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK, 0x1F, div - 1);
break;
case d1_smc:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK, 0x1F, div - 1);
break;
case d1_uart0:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK, 0x1F, div - 1);
break;
case d1_uart1:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (parents + rate - 1) / rate;
if (div > 0x1F) {
div = 0x1F;
}
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK, 0x1F, div - 1);
break;
default:
break;
}
return 0;
}
unsigned long cal_clk_getrate(unsigned int id)
{
unsigned long parents;
unsigned long rate = 0;
unsigned long div;
switch (id) {
case p1_upll:
if (((getreg32(SCMU_PLL_CON0_UPLL) >> 4) & 1) == 0) {
rate = OSCCLK;
} else {
unsigned long p, m, s;
p = (getreg32(SCMU_PLL_CON0_UPLL) >> 8) & 0x3f;
m = (getreg32(SCMU_PLL_CON0_UPLL) >> 16) & 0x3ff;
s = (getreg32(SCMU_PLL_CON0_UPLL) >> 0) & 0x7;
rate = (OSCCLK / p * m) >> s;
}
break;
case m1_timer0:
if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER0_CLK) & 1) == 0) {
rate = OSCCLK;
} else {
rate = SLPCLK_CP;
}
break;
case m1_timer1:
if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK) & 1) == 0) {
rate = OSCCLK;
} else {
rate = SLPCLK_CP;
}
break;
case m1_timer2:
if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK) & 1) == 0) {
rate = OSCCLK;
} else {
rate = SLPCLK_CP;
}
break;
case m1_timer3:
if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK) & 1) == 0) {
rate = OSCCLK;
} else {
rate = SLPCLK_CP;
}
break;
case m1_timer4:
if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK) & 1) == 0) {
rate = OSCCLK;
} else {
rate = SLPCLK_CP;
}
break;
case m1_timer5:
if ((getreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK) & 1) == 0) {
rate = OSCCLK;
} else {
rate = SLPCLK_CP;
}
break;
case d1_upll_clk_ap:
parents = cal_clk_getrate(p1_upll);
div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP) & 0xF) + 1;
rate = parents / div;
break;
case d1_upll_clk_cp:
parents = cal_clk_getrate(p1_upll);
div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_CP) & 0xF) + 1;
rate = parents / div;
break;
case d1_upll_clk_mif:
parents = cal_clk_getrate(p1_upll);
div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF) & 0xF) + 1;
rate = parents / div;
break;
case d1_upll_clk_gnss:
parents = cal_clk_getrate(p1_upll);
div = (getreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_GNSS) & 0xF) + 1;
rate = parents / div;
break;
case d1_acpu_l1:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (getreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_acpu_l2:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = ((getreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK) >> 8) & 0x1F) + 1;
rate = parents / div;
break;
case d1_acpu_l3:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = ((getreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK) >> 16) & 0x1F) + 1;
rate = parents / div;
break;
case d1_sdio:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK) & 0x7F) + 1;
rate = parents / div;
break;
case d1_spi0:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_usi0:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_usi1:
parents = cal_clk_getrate(d1_upll_clk_ap);
div = (getreg32(ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_mif_l2:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = ((getreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK) >> 0) & 0x1F) + 1;
rate = parents / div;
break;
case d1_mif_l3:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = ((getreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK) >> 8) & 0x1F) + 1;
rate = parents / div;
break;
case d1_qspi:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_smc:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_uart0:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK) & 0x1F) + 1;
rate = parents / div;
break;
case d1_uart1:
parents = cal_clk_getrate(d1_upll_clk_mif);
div = (getreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK) & 0x1F) + 1;
rate = parents / div;
break;
default:
break;
}
return rate;
}
int cal_clk_enable(unsigned int id)
{
switch (id) {
case p1_upll:
modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 1);
while (!(getreg32(SCMU_PLL_CON0_UPLL) & (1 << 29))) {
};
modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 1 << 4);
break;
default:
break;
}
return 0;
}
int cal_clk_disable(unsigned int id)
{
switch (id) {
case p1_upll:
modifyreg32(SCMU_PLL_CON0_UPLL, (1 << 4), 0 << 4);
modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), 0);
break;
default:
break;
}
return 0;
}
int cal_init(void)
{
/* disable 0 value setting to reduce binary size */
/* enable UPLL */
modifyreg32(SCMU_PLL_CON0_UPLL, (0x3ff << 16), (0x18c << 16));
modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 31), (1 << 31));
modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_AP, 0xf, 1);
/* need to fix to 0x1 */
modifyreg32(SCMU_CLK_CON_DIV_CKDIVS_UPLL_CLK_MIF, 0xf, 0x1);
// modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, (0x1f << 0), 0); /* L1 CLK */
// modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, (0x1f << 8), 0); /* L2 CLK */
modifyreg32(ACMU_CLK_CON_DIV_MULTI3_CKDIVA_ACPU_CLK, (0x1f << 16), 1 << 16); /* L3 CLK */
// modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SDIO_CLK, 0x7f, 0);
modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_SPI0_CLK, 0x1f, 1);
// modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI0_CLK, 0x1f, 0);
// modifyreg32(ACMU_CLK_CON_DIV_CKDIVA_USI1_CLK, 0x1f, 0);
// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER0_CLK, 0x1, 0);
// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER1_CLK, 0x1, 0);
// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER2_CLK, 0x1, 0);
// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER3_CLK, 0x1, 0);
// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER4_CLK, 0x1, 0);
// modifyreg32(ACMU_CLK_CON_MUX_CKMUXA_TIMER5_CLK, 0x1, 0);
// modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, (0x1f << 0), 0); /* L2 CLK */
modifyreg32(MIFCMU_CLK_CON_DIV_MULTI2_CKDIVF_MIF_SRC_CLK, (0x1f << 8), 1 << 8); /* L3 CLK */
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_QSPI_CLK, 0x1f, 4); //QSPI_CLK to be 40Mhz as first
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_SMC_CLK, 0x1f, 1);
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART0_CLK, 0x1f, 1);
modifyreg32(MIFCMU_CLK_CON_DIV_CKDIVF_UART1_CLK, 0x1f, 1);
/* wait for UPLL lock */
while (!(getreg32(SCMU_PLL_CON0_UPLL) & (1 << 29))) {
};
modifyreg32(SCMU_PLL_CON0_UPLL, (0x1 << 4), (1 << 4));
#if 0
/* Q-CHANNEL enable */
//modifyreg32(ACMU_AP_ACMU_CONTROLLER_OPTION, (0x3 << 28), (0x3 << 28));
modifyreg32(SCMU_SYS_SCMU_CONTROLLER_OPTION, (0x3 << 28), (0x3 << 28));
modifyreg32(MIFCMU_MIF_MIFCMU_CONTROLLER_OPTION, (0x3 << 28), (0x3 << 28));
/* BUS_FREQ_EN, MIN_FREQ_EN enable */
modifyreg32(ACMU_ACMU_DFSC_CTL, (0x3 << 1), (0x3 << 1));
#endif
/* PDMAC Q-CH workaround */
putreg32(0x4046, ACMU_ACMU_BUS_ACT_MSK);
/* Gate clocks of unused peripherals */
// SDIO HOST
putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_CLK);
putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_L2CLK);
putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_SDIO_IPCLKPORT_SDIO_HCLK);
// PPMUs
putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L2CLK);
putreg32(0x100000, ACMU_CLK_CON_GAT_GOUT_AP_UID_ABUS_IPCLKPORT_PPMU_L3CLK);
putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L2CLK);
putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_ACPU2MIF_L3CLK);
putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L2CLK);
putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_MIFBUS_IPCLKPORT_PPMU_MCPU2MIF_L3CLK);
// SMC
putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SMC_IPCLKPORT_CLK);
putreg32(0x100000, MIFCMU_CLK_CON_GAT_GOUT_MIF_UID_SMC_IPCLKPORT_L2CLK);
return 0;
}

102
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100_systemreset.c Normal file
View File

@@ -0,0 +1,102 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/* @file : s5js100_systemreset.c
* @brief : board reset source file
* @date : June 2019
*
* @note : Add chip dependent feature and more detail error status
*
*/
/****************************************************************************
Included Files
****************************************************************************/
#include "cmsis.h"
#include "mbed_interface.h"
#include "mbed_power_mgmt.h"
#include "mbed_stats.h"
#include "mbed_atomic.h"
#include "rtx_os.h"
#include <inttypes.h>
#include <string.h>
/****************************************************************************
* Name: up_systemreset
*
* Description:
* Internal, reset logic.
*
****************************************************************************/
static void up_systemreset(void)
{
putreg32(0x1, 0x8301100C);
putreg32(0x1 << 1, 0x82020018);
putreg32(0x4, 0x83011000); // enable watchdog
putreg32(0x1, 0x83011010);
putreg32(0x1, 0x83011020);
putreg32(327, 0x83011004); //set 10ms to be reset , 1 sec=32768
putreg32(0xFF, 0x83011008); // force to load value to be reset
/* Wait for the reset */
for (; ;) {
}
}
/****************************************************************************
* Name: board_reset
*
* Description:
* Reset board. This function may or may not be supported by a
* particular board architecture.
*
* Input Parameters:
* status - Status information provided with the reset event. This
* meaning of this status information is board-specific. If not used by
* a board, the value zero may be provided in calls to board_reset.
*
* Returned Value:
* If this function returns, then it was not possible to power-off the
* board due to some constraints. The return value int this case is a
* board-specific reason for the failure to shutdown.
*
****************************************************************************/
int board_reset(void)
{
up_systemreset();
return 0;
}

31
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100_type.h Normal file
View File

@@ -0,0 +1,31 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef S5JS100_TYPE_H
#define S5JS100_TYPE_H
#define getreg8(a) (*(volatile unsigned char *)(a))
#define putreg8(v, a) (*(volatile unsigned char *)(a) = (v))
#define getreg32(a) (*(volatile unsigned int *)(a))
#define putreg32(v, a) (*(volatile unsigned int *)(a) = (v))
#define modifyreg32(a, m, v) putreg32((((getreg32(a)) & ~(m)) | ((v) & (m))), (a))
#define is_evt0() (((getreg32(0x82010000)) & 0xF0) == 0)
#endif /* S5JS100_TYPE_H */

88
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/s5js100_vclk.h Normal file
View File

@@ -0,0 +1,88 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S5JS100_VCLK_H__
#define __S5JS100_VCLK_H__
#ifdef __cplusplus
extern "C" {
#endif
enum {
gate_dummy = 0x0A000000,
vclk_group_grpgate_end,
num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
sclk_dummy = 0x0A010000,
vclk_group_m1d1g1_end,
num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
p1_upll = 0x0A020000,
vclk_group_p1_end,
num_of_p1 = vclk_group_p1_end - 0x0A020000,
m1_timer0 = 0x0A030000,
m1_timer1,
m1_timer2,
m1_timer3,
m1_timer4,
m1_timer5,
vclk_group_m1_end,
num_of_m1 = vclk_group_m1_end - 0x0A030000,
d1_upll_clk_ap = 0x0A040000,
d1_upll_clk_cp,
d1_upll_clk_mif,
d1_upll_clk_gnss,
d1_acpu_l1,
d1_acpu_l2,
d1_acpu_l3,
d1_sdio,
d1_spi0,
d1_usi0,
d1_usi1,
d1_mif_l2,
d1_mif_l3,
d1_qspi,
d1_smc,
d1_uart0,
d1_uart1,
vclk_group_d1_end,
num_of_d1 = vclk_group_d1_end - 0x0A040000,
pxmxdx_top = 0x0A050000,
vclk_group_pxmxdx_end,
num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
umux_dummy = 0x0A060000,
vclk_group_umux_end,
num_of_umux = vclk_group_umux_end - 0x0A060000,
dvfs_dummy = 0x0A070000,
vclk_group_dfs_end,
num_of_dfs = vclk_group_dfs_end - 0x0A070000,
};
extern int cal_clk_setrate(unsigned int id, unsigned long rate);
extern unsigned long cal_clk_getrate(unsigned int id);
extern int cal_clk_enable(unsigned int id);
extern int cal_clk_disable(unsigned int id);
#ifdef __cplusplus
}
#endif
#endif

470
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/sflash_api.cpp Normal file
View File

@@ -0,0 +1,470 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <string.h>
#include "mbed.h"
#include "stdlib.h"
#include "cmsis.h"
#include "mbed_wait_api.h"
#include "flash_api.h"
/****************************************************************************
* Private Data
****************************************************************************/
int flash_no_erase;
int flash_idx = 0;
#define S5JS100_FLASH_DELAYTIME 1
#define S5JS100_FLASH_WRITEUNIT 32
#define CACHE_LINE_MASK 0xffffffe0
#define CACHE_LINE_SIZE 32
Semaphore *g_sem = new Semaphore(1);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
static void hw_delay_us(unsigned int Value)
{
volatile unsigned i, j;
for (i = 0; i < (Value * 2); i++)
for (j = 0; j < 100; j++);
}
unsigned int up_progmem_blocksize(void)
{
return S5JS100_FLASH_BLOCK_SIZE;
}
/*
static void sflash_set_page_size(eQSPI_PAGE_SIZE size)
{
//Bytes per Page
modifyreg32(S5JS100_SFLASH_SFCON, 0xF << 8, size << 8);
}
*/
static unsigned int up_progmem_npages(void)
{
return S5JS100_FLASH_SIZE / S5JS100_FLASH_PAGE_SIZE;
}
static int up_progmem_getaddress(int page)
{
return S5JS100_FLASH_PADDR + S5JS100_FLASH_PAGE_SIZE * page;
}
int up_progmem_getpage(int addr)
{
return (addr - S5JS100_FLASH_PADDR) / S5JS100_FLASH_PAGE_SIZE;
}
static void s5js100_sflash_disable_wp(void)
{
/* someone has been disabled wp, we should wait until it's released */
while (getreg32(S5JS100_SFLASH_SFCON) & SFLASH_SFCON_WP_DISABLE) ;
modifyreg32(S5JS100_SFLASH_SFCON, SFLASH_SFCON_WP_MASK, SFLASH_SFCON_WP_DISABLE);
}
static void s5js100_sflash_enable_wp(void)
{
modifyreg32(S5JS100_SFLASH_SFCON, SFLASH_SFCON_WP_MASK, SFLASH_SFCON_WP_ENABLE);
}
static uint8_t s5js100_sflash_read_status(void)
{
return getreg8(S5JS100_SFLASH_RDSR);
}
/* return FLASH capacity in BYTE */
uint32_t s5js100_sflash_read_capacity(void)
{
uint32_t capacity_type;
capacity_type = (getreg32(S5JS100_SFLASH_RDID) & (0xFF << 16)) >> 16;
capacity_type = (0x1 << ((capacity_type & 0xF) - 1)) * 1024 * 1024;
return capacity_type / 8;
}
int s5js100_sflash_write_protect(eQSPI_PROTECTION_AREA area)
{
int status_register;
s5js100_sflash_disable_wp();
status_register = getreg8(S5JS100_SFLASH_RDSR);
//lldbg("status_register : 0x%x, area : 0x%x\n", status_register, area);
/* send Write Enable */
putreg8(1, S5JS100_SFLASH_WREN);
while (!(getreg8(S5JS100_SFLASH_RDSR) & 0x2));
/* write status register */
status_register = (status_register & 0x83) | (area << 2);
//lldbg("status_register write : 0x%x ==> ", status_register);
putreg32(status_register | 0x0200, S5JS100_SFLASH_WRSR);
while (getreg8(S5JS100_SFLASH_RDSR) & 0x1);
status_register = getreg8(S5JS100_SFLASH_RDSR);
//lldbg("0x%x\n", status_register);
/* send Write Disable */
putreg8(1, S5JS100_SFLASH_WRDI);
while (getreg8(S5JS100_SFLASH_RDSR) & 0x2);
s5js100_sflash_enable_wp();
return 0;
}
/* SFlash_DriverInitialize: SFlash Driver Initialize function */
void SFlash_DriverInitialize()
{
putreg32(0x8660060A, S5JS100_SFLASH_SFCON); /*disable write protect for FLASH stage changing*/
modifyreg32(0x85020074, 0x1, 1); /*Set FAST READ */
/* Enable Quad Read */
putreg32(0x4, S5JS100_SFLASH_IO_MODE);
putreg32(0x8, S5JS100_SFLASH_PERF_MODE);
// command 3. RDSR2 read winbond Status Register 2
modifyreg32(0x85020024, 0xFF, 0x35); //Set QE to Status2
while (!(getreg8(S5JS100_SFLASH_BASE + 0xDC) & (0x1 << 1))) {
}; /* Check FLASH has Quad Enabled */
cal_clk_setrate(d1_qspi, 100000000);
putreg32(0x0660061A, S5JS100_SFLASH_SFCON); //enable write protect + winbond + byte program
/* change drive strength */
modifyreg32(0x82021070, 0x3 << 8, 0x0 << 8); //Drive strength CS to (0x0)2mA
modifyreg32(0x82021074, 0x3 << 8, 0x0 << 8); //Drive strength SCK to (x0)2mA
modifyreg32(0x82021078, 0x3 << 8, 0x0 << 8); //Drive strength SI to (0x0)2mA
modifyreg32(0x8202107C, 0x3 << 8, 0x0 << 8); //Drive strength SO to (0x0)2mA
modifyreg32(0x82021080, 0x3 << 8, 0x0 << 8); //Drive strength WP to (0x0)2mA
modifyreg32(0x82021084, 0x3 << 8, 0x0 << 8); //Drive strength HLD to (0x0)2mA
s5js100_sflash_write_protect(SFLASH_PROTECTION_NONE);
}
extern "C" {
void s5js100_sflash_reinit(void)
{
cal_clk_setrate(d1_qspi, 100000000);
}
}
static void local_memcpy(void *dst, void *src, size_t n)
{
unsigned char *pout = (unsigned char *)dst;
unsigned char *pin = (unsigned char *)src;
while (n-- > 0) {
*pout++ = *pin++;
}
}
static int up_progmem_write_disabledcache(unsigned int addr, const void *buf, int count)
{
int remain = count;
char *pos = (char *)buf;
g_sem->try_acquire();
while (remain) {
int tmp = remain;
if (tmp > S5JS100_FLASH_WRITEUNIT) {
tmp = S5JS100_FLASH_WRITEUNIT;
}
s5js100_sflash_disable_wp();
/* Temporary code for testing */
//memcpy((void *)(addr + S5JS100_SFLASH_WOFFSET), (void *)(pos), tmp);
local_memcpy((void *)(addr + S5JS100_SFLASH_WOFFSET), (void *)(pos), tmp);
/* Flash Mirror Address is device attribute, need to POC with Flash Read Address */
/* invalidate cache for read address, not read and write in POC state */
/* CM7 cache line 32bytes, align 32bytes */
invalidate_dcache_by_addr((uint32_t *)(addr & CACHE_LINE_MASK), tmp + CACHE_LINE_SIZE);
s5js100_sflash_enable_wp();
pos += tmp;
addr += tmp;
remain -= tmp;
hw_delay_us(1000 * S5JS100_FLASH_DELAYTIME);
}
g_sem->release();
return count;
}
int sflash_write(unsigned int addr, unsigned char *buf, int count)
{
unsigned int uf_start = (unsigned int)S5JS100_FLASH_FS_PADDR;
unsigned int uf_end = S5JS100_FLASH_PADDR + S5JS100_FLASH_SIZE;
/*
* Check the request address is in a specific userflash area
* We assumed that the userflash area's address is started from the end of
* OS partition to the end of flash.
*/
if (addr >= uf_start && addr < uf_end) {
up_progmem_write_disabledcache(addr, buf, count);
return 0;
}
int pagesize;
int remain = count;
pagesize = S5JS100_FLASH_PAGE_SIZE;
g_sem->try_acquire();
while (remain) {
int tmp = remain;
if (tmp > pagesize) {
tmp = pagesize;
}
s5js100_sflash_disable_wp();
/* Load and write data */
local_memcpy((void *)addr, buf, tmp);
/* Flush cache */
clean_invalidate_dcache_by_addr((uint32_t *)(addr & CACHE_LINE_MASK), tmp + CACHE_LINE_SIZE);
s5js100_sflash_enable_wp();
buf += tmp;
addr += tmp;
remain -= tmp;
}
g_sem->release();
return 0;
}
static int _is_erased(unsigned int address, int size)
{
unsigned int *p = (unsigned int *)address;
while (size > 0) {
if (*p != 0xFFFFFFFF) {
return 0;
} else {
p++;
size -= 4;
}
}
return 1;
}
int up_progmem_erasepage(unsigned int page)
{
int addr;
if (page >= up_progmem_npages()) {
return -1;
}
addr = up_progmem_getaddress(page);
/* skip erased block */
if (_is_erased(addr, up_progmem_blocksize())) {
return 0;
}
g_sem->try_acquire();
//s5js100_flash_take_sem();
s5js100_sflash_disable_wp();
/* Set sector address and then send erase command */
putreg32(addr - S5JS100_FLASH_PADDR, S5JS100_SFLASH_ERASE_ADDRESS);
putreg8(0xff, S5JS100_SFLASH_SE);
/* Wait for the completion */
while (s5js100_sflash_read_status() & 0x1) {
};
/* Invalidate cache */
invalidate_dcache_by_addr((uint32_t *)(addr & CACHE_LINE_MASK)/* + S5JS100_FLASH_PADDR*/, up_progmem_blocksize());
s5js100_sflash_enable_wp();
g_sem->release();
return 0;
}
unsigned int up_progmem_write(unsigned int addr, const void *buf, unsigned int count)
{
return sflash_write(addr, (unsigned char *)buf, count);
}
int sflash_erase(unsigned int address)
{
int page;
page = up_progmem_getpage(address);
return up_progmem_erasepage(page);
}
#define ENV_MAX 20
struct _env_list {
char env_name[11];
char env_val[41];
} env_list[ENV_MAX];
#define BOOTARG_VAL_OFFSET 0x40
#define BOOTARG_VAL_MAX_SIZE 0x40
void sflash_os_env_parser(void)
{
char *env_addr, *ptr;
int argc = 0;
char buf[4096];
uint32_t env_offset;
if (s5js100_sflash_read_capacity() == 8 * 1024 * 1024) {
env_offset = S5JS100_OS_ENV_OFFSET_8MB;
}
if (s5js100_sflash_read_capacity() == 16 * 1024 * 1024) {
env_offset = S5JS100_OS_ENV_OFFSET_16MB;
}
env_addr = (char *)(S5JS100_FLASH_PADDR + env_offset + BOOTARG_VAL_OFFSET);
memcpy(buf, env_addr, 4 * 1024);
ptr = buf;
while (argc < ENV_MAX) {
char *arg = ptr;
int i = 0, j = 1; //j from '='
if (*ptr == 0xFF || *ptr == 0) {
ptr += BOOTARG_VAL_OFFSET;//strtok(NULL, "\n\r\t ,");
argc++;
continue;
}
while (*(arg + i) != '=') {
if (*(arg + i) == 0xFF || i >= 10) {
return;
}
i++;
}
*(arg + i) = '\0';
strcpy(env_list[argc].env_name, arg);
while (j < BOOTARG_VAL_MAX_SIZE - i) {
if (*(arg + i + j) == 0xFF || *(arg + i + j) == 0) {
break;
}
j++;
}
*(arg + i + j) = '\0';
strcpy(env_list[argc++].env_val, arg + i + 1);
ptr += BOOTARG_VAL_OFFSET;//strtok(NULL, "\n\r\t ,");
}
}
char *get_env(const char *name)
{
int i;
for (i = 0; i < ENV_MAX; i++) {
if (!strcmp(name, env_list[i].env_name)) {
return env_list[i].env_val;
}
}
return 0;
}
#ifdef DEVICE_FLASH
/*************** flash_hal API ********************/
/* hal/flash_api.h */
int32_t flash_init(flash_t *obj)
{
SFlash_DriverInitialize();
return 0;
}
int32_t flash_free(flash_t *obj)
{
return 0;
}
uint32_t flash_get_page_size(const flash_t *info)
{
return 4; /*S5JS100_FLASH_PAGE_SIZE*/
}
uint32_t flash_get_sector_size(const flash_t *info, uint32_t addr)
{
return up_progmem_blocksize();
}
uint32_t flash_get_start_address(const flash_t *info)
{
return S5JS100_FLASH_FS_PADDR;
}
uint32_t flash_get_size(const flash_t *info)
{
return S5JS100_FLASH_FS_SIZE;
}
int32_t flash_program_page(flash_t *obj, uint32_t addr, const uint8_t *data, uint32_t size)
{
if (addr > S5JS100_FLASH_PADDR) {
return sflash_write(addr, (unsigned char *)data, size);
} else {
local_memcpy((void *)addr, (void *)data, size);
return 0;
}
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
(void)obj;
return 0xFF;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t addr)
{
if (addr > S5JS100_FLASH_PADDR) {
return sflash_erase(addr);
} else {
memset((void *)addr, 0xFFFFFFFF, 4096);
return 0;
}
}
#endif

226
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/sflash_api.h Normal file
View File

@@ -0,0 +1,226 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef _SFLASH_DRV_H
#define _SFLASH_DRV_H
//#include "fcache_api.h"
#ifdef __cplusplus
extern "C" {
#else
#include <stdio.h>
#endif
#define S5JS100_FLASH_PAGE_SIZE 256
#define S5JS100_FLASH_BLOCK_SIZE 4096
#define S5JS100_FLASH_PADDR (0x40000000)
#define S5JS100_FLASH_FS_PADDR 0x40EF5000
#define S5JS100_FLASH_FS_SIZE 256*1024
#define S5JS100_FLASH_SIZE (16 * 1024 * 1024)
#define S5JS100_OS_ENV_OFFSET_16MB (0x2E000)
#define S5JS100_OS_ENV_OFFSET_8MB (0x3B000)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define S5JS100_SFLASH_BASE (0x85020000)
#define S5JS100_SFLASH_SFCON ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0004))
#define S5JS100_SFLASH_ERASE_ADDRESS ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0010))
#define S5JS100_SFLASH_USER_COMMAND ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0018))
#define S5JS100_SFLASH_COMMAND1 ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x001C))
#define S5JS100_SFLASH_COMMAND2 ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0020))
#define S5JS100_SFLASH_COMMAND3 ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0024))
#define S5JS100_SFLASH_COMMAND4 ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0028))
#define S5JS100_SFLASH_COMMAND5 ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x002C))
#define S5JS100_SFLASH_USER_INSTRUCTION ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0059))
#define S5JS100_SFLASH_SE ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x005E))
#define S5JS100_SFLASH_IO_MODE ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0074))
#define S5JS100_SFLASH_PERF_MODE ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x0078))
#define S5JS100_SFLASH_RDID ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00AC))
#define S5JS100_SFLASH_BE ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00BE))
#define S5JS100_SFLASH_CE ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00CE))
#define S5JS100_SFLASH_RDSR ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00DC))
#define S5JS100_SFLASH_WRDI ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00DD))
#define S5JS100_SFLASH_WRSR ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00E0))
#define S5JS100_SFLASH_WREN ((volatile unsigned int *)(S5JS100_SFLASH_BASE + 0x00EE))
/* Register Bitfield Definitions ********************************************/
/* Control Register */
#define SFLASH_SFCON_WP_SHIFT 31
#define SFLASH_SFCON_WP_MASK (0x1 << SFLASH_SFCON_WP_SHIFT)
#define SFLASH_SFCON_WP_ENABLE (0x0 << SFLASH_SFCON_WP_SHIFT)
#define SFLASH_SFCON_WP_DISABLE (0x1 << SFLASH_SFCON_WP_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_SHIFT 16
#define SFLASH_SFCON_MEMORY_VENDOR_MASK (0x3f << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_WINBOND (0x20 << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_MACRONIX (0x10 << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_ATMEL (0x08 << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_AMD (0x04 << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_STMICRO (0x02 << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_MEMORY_VENDOR_SST (0x01 << SFLASH_SFCON_MEMORY_VENDOR_SHIFT)
#define SFLASH_SFCON_PAGE_EN_SHIFT 15
#define SFLASH_SFCON_PAGE_EN_MASK (0x1 << SFLASH_SFCON_PAGE_EN_SHIFT)
#define SFLASH_SFCON_PAGE_EN_BYTEPROG (0x0 << SFLASH_SFCON_PAGE_EN_SHIFT)
#define SFLASH_SFCON_PAGE_EN_PAGEPROG (0x1 << SFLASH_SFCON_PAGE_EN_SHIFT)
#define SFLASH_SFCON_PAGE_SHIFT 8
#define SFLASH_SFCON_PAGE_MASK (0xf << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_4BYTES (0x0 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_8BYTES (0x1 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_16BYTES (0x2 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_32BYTES (0x3 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_64BYTES (0x4 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_128BYTES (0x5 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_256BYTES (0x6 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_PAGE_RESERVED (0x7 << SFLASH_SFCON_PAGE_SHIFT)
#define SFLASH_SFCON_HALF_DELAY_SHIFT 7
#define SFLASH_SFCON_HALF_DELAY_MASK (0x1 << SFLASH_SFCON_HALF_DELAY_SHIFT)
#define SFLASH_SFCON_HALF_DELAY_OFF (0x0 << SFLASH_SFCON_HALF_DELAY_SHIFT)
#define SFLASH_SFCON_HALF_DELAY_ON (0x1 << SFLASH_SFCON_HALF_DELAY_SHIFT)
#define SFLASH_SFCON_ERASE_WAIT_SHIFT 4
#define SFLASH_SFCON_ERASE_WAIT_MASK (0x1 << SFLASH_SFCON_ERASE_WAIT_SHIFT)
#define SFLASH_SFCON_ERASE_WAIT_OFF (0x0 << SFLASH_SFCON_ERASE_WAIT_SHIFT)
#define SFLASH_SFCON_ERASE_WAIT_ON (0x1 << SFLASH_SFCON_ERASE_WAIT_SHIFT)
#define SFLASH_SFCON_PRE_CHARGE_SHIFT 0
#define SFLASH_SFCON_PRE_CHARGE_MASK (0xf << SFLASH_SFCON_PRE_CHARGE_SHIFT)
/* Flash I/O Mode */
#define SFLASH_IO_MODE_MASK 0xf
#define SFLASH_IO_MODE_READ 0x0
#define SFLASH_IO_MODE_FAST_READ 0x1
#define SFLASH_IO_MODE_DUAL_FAST_READ 0x2
#define SFLASH_IO_MODE_QUAD_FAST_READ 0x4
/* Flash Performance Mode */
#define SFLASH_PERF_MODE_MASK 0x8
#define SFLASH_PERF_MODE_NORMAL 0x0
#define SFLASH_PERF_MODE_DUAL_QUAD 0x8
#define SFLASH_DUMMY_DATA 0x1
#define SFLASH_SECTOR_OFFSET (12)
#define SFLASH_BLOCK32K_OFFSET (15)
#define SFLASH_BLOCK64K_OFFSET (16)
#define SFLASH_SIZE_64KB (1<<SFLASH_BLOCK64K_OFFSET)
#define SFLASH_SIZE_32KB (1<<SFLASH_BLOCK32K_OFFSET)
#define SFLASH_SIZE_4KB (1<<SFLASH_SECTOR_OFFSET)
#define COMMAND_ERASE_32KB (0x52)
#define COMMAND_ERASE_64KB (0xD8)
#define S5JS100_SFLASH_WOFFSET 0x50000000 /* FLASH Mirror Offset */
typedef enum {
TYPE_ERR = 0,
TYPE_4KB = 1,
TYPE_32KB = 2,
TYPE_64KB = 3,
} eERASE_UNIT;
typedef enum {
SFLASH_SINGLE_IO,
SFLASH_DUAL_FAST,
SFLASH_DUAL_IO,
SFLASH_QUAD_FAST,
SFLASH_QUAD_IO,
} eQSPI_MODE;
typedef enum {
SFLASH_VENDOR_SST = 0x1,
SFLASH_VENDOR_STMICRO = 0x2,
SFLASH_VENDOR_AMD = 0x4,
SFLASH_VENDOR_ATMEL = 0x8,
SFLASH_VENDOR_MACRONIX = 0x10,
SFLASH_VENDOR_WINBOND = 0x20,
} eQSPI_VENDOR;
typedef enum {
SFLASH_PAGE_4BYTES = 0x0,
SFLASH_PAGE_8BYTES = 0x1,
SFLASH_PAGE_16BYTES = 0x2,
SFLASH_PAGE_32BYTES = 0x3,
SFLASH_PAGE_64BYTES = 0x4,
SFLASH_PAGE_128BYTES = 0x5,
SFLASH_PAGE_256BYTES = 0x6,
} eQSPI_PAGE_SIZE;
typedef struct _status_register_t {
unsigned char rdsr;
struct {
unsigned WIP: 1;
unsigned WEL: 1;
unsigned BP0: 1;
unsigned BP1: 1;
unsigned BP2: 1;
unsigned BP3: 1;
unsigned QE: 1; //Quad enable
unsigned SRWD: 1; //Status Register Write Disable
} b;
} sRead_Status_Register;
typedef enum {
SFLASH_PROTECTION_NONE = 0x0,
SFLASH_PROTECTION_BOTTOM_256KB = 0x1, /* 0xFC0000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_512KB = 0x2, /* 0xF80000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_1MB = 0x3, /* 0xF00000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_2MB = 0x4, /* 0xE00000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_4MB = 0x5, /* 0xC00000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_8MB = 0x6, /* 0x800000 ~ 0xFFFFFF */
SFLASH_PROTECTION_ALL = 0x7, /* 0x000000 ~ 0xFFFFFF */
SFLASH_PROTECTION_TOP_256KB = 0x9, /* 0x000000 ~ 0x03FFFF */
SFLASH_PROTECTION_TOP_512KB = 0xA, /* 0x000000 ~ 0x07FFFF */
SFLASH_PROTECTION_TOP_1MB = 0xB, /* 0x000000 ~ 0x0FFFFF */
SFLASH_PROTECTION_TOP_2MB = 0xC, /* 0x000000 ~ 0x1FFFFF */
SFLASH_PROTECTION_TOP_4MB = 0xD, /* 0x000000 ~ 0x3FFFFF */
SFLASH_PROTECTION_TOP_8MB = 0xE, /* 0x000000 ~ 0x7FFFFF */
SFLASH_PROTECTION_BOTTOM_4KB = 0x11, /* 0xFFF000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_8KB = 0x12, /* 0xFFE000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_16KB = 0x13, /* 0xFFC000 ~ 0xFFFFFF */
SFLASH_PROTECTION_BOTTOM_32KB = 0x14, /* 0xFF8000 ~ 0xFFFFFF */
SFLASH_PROTECTION_TOP_4KB = 0x19, /* 0x000000 ~ 0x000FFF */
SFLASH_PROTECTION_TOP_8KB = 0x1A, /* 0x000000 ~ 0x001FFF */
SFLASH_PROTECTION_TOP_16KB = 0x1B, /* 0x000000 ~ 0x003FFF */
SFLASH_PROTECTION_TOP_32KB = 0x1C, /* 0x000000 ~ 0x007FFF */
} eQSPI_PROTECTION_AREA;
extern void SFlash_DriverInitialize(void);
extern int sflash_write(unsigned int addr, unsigned char *buf, int const);
extern int sflash_erase(unsigned int addr);
extern void sflash_os_env_parser(void);
extern char *get_env(const char *name);
extern int up_progmem_erasepage(unsigned int page);
extern unsigned int up_progmem_blocksize(void);
extern unsigned int up_progmem_write(unsigned int addr, const void *buf, unsigned int count);
#ifdef __cplusplus
}
#endif
#endif /* _FCACHE_DRV_H */

241
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/system_core_s5js100.c Normal file
View File

@@ -0,0 +1,241 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include "cmsis.h"
#include "os_tick.h"
#ifndef SYSTICK_IRQ_PRIORITY
#define SYSTICK_IRQ_PRIORITY 0xFFU
#endif
static uint8_t PendST;
/**
* @brief HAL Status structures definition
*/
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @brief This function configures the source of the time base:
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
#define SYSTICK_CLOCK (26000000)
#define SYSTICK_RELOAD (SYSTICK_CLOCK / 100) + 1 //10ms
int32_t OS_Tick_Setup(uint32_t freq, IRQHandler_t handler)
{
uint32_t load;
(void)handler;
if (freq == 0U) {
//lint -e{904} "Return statement before end of function"
return (-1);
}
load = (SYSTICK_CLOCK / freq) - 1U;
if (load > 0x00FFFFFFU) {
//lint -e{904} "Return statement before end of function"
return (-1);
}
// Set SysTick Interrupt Priority
#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__CORTEX_M) && (__CORTEX_M == 7U)))
SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;
#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)))
SCB->SHP[11] = SYSTICK_IRQ_PRIORITY;
#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0))
SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
#else
#error "Unknown ARM Core!"
#endif
/*
override systick clock source
NVIC_SYSTICK_CTRL_CLKSOURCE=1 : Use processor clock
NVIC_SYSTICK_CTRL_CLKSOURCE=0 : Use OSC clock
*/
SysTick->CTRL = 0x10003;//SysTick_CTRL_COUNTFLAG_Msk | /*SysTick_CTRL_CLKSOURCE_Msk |*/ SysTick_CTRL_TICKINT_Msk;
SysTick->LOAD = load;
// SysTick->VAL = 0U;
PendST = 0U;
return (0);
}
void OS_Tick_Enable(void)
{
}
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(SYSTICK_RELOAD);
/*Configure the SysTick IRQ priority */
//HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
/* Return function status */
return HAL_OK;
}
#if defined ( __ICCARM__ )
#define S5JS100_BOOTMEM_BASE 0x00000000
extern uint32_t __vector_table;
extern uint32_t __Vectors_Size;
#elif defined (TOOLCHAIN_ARM_STD)/*__ARMCC_VERSION)*/
#define S5JS100_BOOTMEM_BASE 0x00000000
extern uint32_t __Vectors;
extern uint32_t __Vectors_Size;
#elif defined ( __GNUC__ )
extern uint32_t _v_start;
extern uint32_t __vector_table;
extern uint32_t __vector_table_end;
extern uint32_t __isr_vector[];
#endif
extern int cal_init(void);
/*
* SystemCoreConfig(): Configure the System Core
*/
void SystemCoreConfig()
{
const uint32_t *src;
uint32_t *dest, size;
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) 0;
#endif
#if defined ( __ICCARM__ )
src = &__vector_table;
dest = (uint32_t *)S5JS100_BOOTMEM_BASE;
size = (uint32_t)&__Vectors_Size;
/* Move vector table to the right location. */
for (src = &__vector_table, dest = (uint32_t *)S5JS100_BOOTMEM_BASE; dest < ((volatile unsigned int *)S5JS100_BOOTMEM_BASE + size);) {
*dest++ = *src++;
//*dest++ = *src++;
}
#elif defined (TOOLCHAIN_ARM_STD)/*__ARMCC_VERSION)*/
src = (uint32_t *)&__Vectors;
dest = (uint32_t *)S5JS100_BOOTMEM_BASE;
size = (uint32_t)&__Vectors_Size;
/* Move vector table to the right location. */
for (dest = (uint32_t *)S5JS100_BOOTMEM_BASE; (uint32_t)dest < ((uint32_t)S5JS100_BOOTMEM_BASE + size);) {
*dest++ = *src++;
//*dest++ = *src++;
}
#elif defined ( __GNUC__ )
src = __isr_vector;
dest = &_v_start;
size = (uint32_t)&__vector_table_end - (uint32_t)&__vector_table;
/* Move vector table to the right location. */
for (src = __isr_vector, dest = &_v_start; dest < (&_v_start + size);) {
*dest++ = *src++;
}
#endif
cal_init();
HAL_InitTick(TICK_INT_PRIORITY);
}
/* POWER MANAGEMENT */
/*
* SystemPowerConfig(): Configures the System Power Modes
*/
void SystemPowerConfig()
{
}
/*
* SystemPowerSuspend(): Enters in System Suspend
*/
void SystemPowerSuspend(power_mode_t mode)
{
if (mode == POWER_MODE_DEEP_SLEEP) {
/* Enable deepsleep */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Ensure effect of last store takes effect */
__DSB();
/* Enter sleep mode */
__WFI();
} else {
/* Enter sleep mode */
__WFI();
}
}
/*
* SystemPowerResume(): Returns from System Suspend
*/
void SystemPowerResume(power_mode_t mode)
{
if (mode == POWER_MODE_DEEP_SLEEP) {
/* Disable sleeponexit */
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
/* Ensure effect of last store takes effect */
__DSB();
}
}
/*
* System config data storage functions
* Reserved as the data is not strictly persistent
*/

118
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/system_core_s5js100.h Normal file
View File

@@ -0,0 +1,118 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/* @file : system_core_s5js100.h
* @brief : System core configuration header
* @date : June 2019
*
* @note : Add system mode
*
*/
#ifndef SYSTEM_CORE_S5JS100_H
#define SYSTEM_CORE_S5JS100_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* SystemCoreConfig(): Configure the System Core
*/
void SystemCoreConfig(void);
/* POWER MANAGEMENT */
/* Power Mode Type Definition */
typedef enum {
/* Sleep Power Mode */
POWER_MODE_SLEEP = 0,
/* Deep Sleep Power Mode */
POWER_MODE_DEEP_SLEEP = 1
} power_mode_t;
/* APB System Core Clocks */
#define SYSTEM_CORE_TIMER0 (1 << 0)
#define SYSTEM_CORE_TIMER1 (1 << 1)
#define SYSTEM_CORE_DUALTIMER0 (1 << 2)
#define SYSTEM_CORE_UART0 (1 << 4)
#define SYSTEM_CORE_UART1 (1 << 5)
#define SYSTEM_CORE_I2C0 (1 << 7)
#define SYSTEM_CORE_WDOG (1 << 8)
#define SYSTEM_CORE_QSPI (1 << 11)
#define SYSTEM_CORE_SPI0 (1 << 12)
#define SYSTEM_CORE_SPI1 (1 << 13)
#define SYSTEM_CORE_I2C1 (1 << 14)
#define SYSTEM_CORE_TRNG (1 << 15) /* TRNG can not be a wakeup source */
/*
* SystemPowerConfig(): Configures the System Power Modes
*/
void SystemPowerConfig(void);
/*
* SystemPowerSuspend(): Enters in System Suspend
*/
void SystemPowerSuspend(power_mode_t mode);
/*
* SystemPowerResume(): Returns from System Suspend
*/
void SystemPowerResume(power_mode_t mode);
/*
* Definitions for storing static configuration data in Beetle
* This is not strictly persistent data as it will get wiped out on chip erase.
*
* There are only read functions provided.
* No Write function to prevent accidental writes resulting in
* the system being non responsive.
* Use the Flash manual before trying to write anything in the last 4k.
*/
#define SYSTEM_CORE_CONFIG_DATA_SIZE (0x200) /* 512 bytes*/
typedef struct {
uint32_t BD_ADDR[2];
/*rest reserved*/
uint32_t reserved[SYSTEM_CORE_CONFIG_DATA_SIZE - 2];
} SystemCoreConfigData;
/*
* __System_Config_GetBDAddr(): Address for the BLE device on the air.
*/
void __System_Config_GetBDAddr(uint8_t *addr, uint8_t len);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CORE_S5JS100_H */

41
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/system_core_version.c Normal file
View File

@@ -0,0 +1,41 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include "system_core_version.h"
#define REALLY_MAKE_STR(y) #y
#define MAKE_STR(x) REALLY_MAKE_STR(x)
#define SYSTEM_CORE_VERSION() (SYSTEM_CORE_PLATFORM ".SYSTEM.CORE." \
MAKE_STR(SYSTEM_CORE_OS) \
"." MAKE_STR(SYSTEM_CORE_VERSION_MAJOR) \
"." MAKE_STR(SYSTEM_CORE_VERSION_MINOR) \
"." MAKE_STR(SYSTEM_CORE_VERSION_PATCH) \
" " SYSTEM_CORE_DATE \
" " SYSTEM_CORE_TIME)
/* Private Data */
const char *system_core_version = SYSTEM_CORE_VERSION();
/* Get System Core Version */
const char *SystemCoreGetVersion()
{
return system_core_version;
}

45
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/system_core_version.h Normal file
View File

@@ -0,0 +1,45 @@
/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_CORE_VERSION_H
#define SYSTEM_CORE_VERSION_H
#ifdef __cplusplus
extern "C" {
#endif
/* Platform Name */
#define SYSTEM_CORE_PLATFORM "SAMSUNG SIDK S5JS100 "
/* OS Version */
#define SYSTEM_CORE_OS 5
/* System Core Version */
#define SYSTEM_CORE_VERSION_MAJOR 0
#define SYSTEM_CORE_VERSION_MINOR 1
#define SYSTEM_CORE_VERSION_PATCH 0
#define SYSTEM_CORE_DATE __DATE__
#define SYSTEM_CORE_TIME __TIME__
/* Get System Core Version */
const char *SystemCoreGetVersion(void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CORE_VERSION_H */

83
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/system_s5js100.c Normal file
View File

@@ -0,0 +1,83 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/* @file : system_s5js100.c
* @brief : System core configuration source code
* @date : June 2019
*
* @note : fix chip dependent system clock
*
*/
#include "cmsis.h"
/*----------------------------------------------------------------------------
* Define clocks
*----------------------------------------------------------------------------*/
#define __SYSTEM_CLOCK (198000000UL)
/*----------------------------------------------------------------------------
* Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;
/*----------------------------------------------------------------------------
* Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
SystemCoreConfig();
}

56
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/device/system_s5js100.h Normal file
View File

@@ -0,0 +1,56 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef SYSTEM_SIDK_S5JS100_H
#define SYSTEM_SIDK_S5JS100_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_SIDK_S5JS100_H */