Import Mbed OS hard-float snapshot
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Beslan
265
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/gpio_irq_api.c
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265
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/gpio_irq_api.c
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2020 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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/* @file : gpio_irq_api.c
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* @brief : GPIO interrupt API source file
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* @date : June 2019
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*
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* @note : Add chip dependent feature and support up to 72 Pin
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*
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*/
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#include <stddef.h>
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#include "cmsis.h"
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#include "gpio_irq_api.h"
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#include "mbed_error.h"
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#include "mbed_trace.h"
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#include "mbed_assert.h"
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#define TRACE_GROUP "GPIO"
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#define PIN_NUM 73
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#define PININT_IRQ0 S5JS100_IRQ_GPIO_INTR0
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#define PININT_IRQ1 S5JS100_IRQ_GPIO_INTR1
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#define PININT_IRQ2 S5JS100_IRQ_GPIO_INTR2
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struct pin_info {
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uint8_t minor;
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uint32_t ids;
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uint32_t pincfg;
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gpio_irq_event event;
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} pins[PIN_NUM] = {
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{0, (uint32_t)NULL, GPIO_GPIO0, IRQ_NONE},
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{1, (uint32_t)NULL, GPIO_GPIO1, IRQ_NONE},
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{2, (uint32_t)NULL, GPIO_GPIO2, IRQ_NONE},
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{3, (uint32_t)NULL, GPIO_GPIO3, IRQ_NONE},
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{4, (uint32_t)NULL, GPIO_GPIO4, IRQ_NONE},
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{5, (uint32_t)NULL, GPIO_GPIO5, IRQ_NONE},
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{6, (uint32_t)NULL, GPIO_GPIO6, IRQ_NONE},
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{7, (uint32_t)NULL, GPIO_GPIO7, IRQ_NONE},
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{8, (uint32_t)NULL, GPIO_GPIO8, IRQ_NONE},
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{9, (uint32_t)NULL, GPIO_GPIO9, IRQ_NONE},
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{10, (uint32_t)NULL, GPIO_GPIO10, IRQ_NONE},
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{11, (uint32_t)NULL, GPIO_GPIO11, IRQ_NONE},
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{12, (uint32_t)NULL, GPIO_GPIO12, IRQ_NONE},
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{13, (uint32_t)NULL, GPIO_GPIO13, IRQ_NONE},
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{14, (uint32_t)NULL, GPIO_GPIO14, IRQ_NONE},
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{15, (uint32_t)NULL, GPIO_GPIO15, IRQ_NONE},
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{16, (uint32_t)NULL, GPIO_GPIO16, IRQ_NONE},
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{17, (uint32_t)NULL, GPIO_GPIO17, IRQ_NONE},
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{18, (uint32_t)NULL, GPIO_GPIO18, IRQ_NONE},
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{19, (uint32_t)NULL, GPIO_GPIO19, IRQ_NONE},
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{20, (uint32_t)NULL, GPIO_GPIO20, IRQ_NONE},
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{21, (uint32_t)NULL, GPIO_GPIO21, IRQ_NONE},
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{22, (uint32_t)NULL, GPIO_GPIO22, IRQ_NONE},
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{23, (uint32_t)NULL, GPIO_GPIO23, IRQ_NONE},
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{24, (uint32_t)NULL, GPIO_GPIO24, IRQ_NONE},
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{25, (uint32_t)NULL, GPIO_GPIO25, IRQ_NONE},
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{26, (uint32_t)NULL, GPIO_GPIO26, IRQ_NONE},
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{27, (uint32_t)NULL, GPIO_GPIO27, IRQ_NONE},
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{28, (uint32_t)NULL, GPIO_GPIO28, IRQ_NONE},
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{29, (uint32_t)NULL, GPIO_GPIO29, IRQ_NONE},
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{30, (uint32_t)NULL, GPIO_GPIO30, IRQ_NONE},
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{31, (uint32_t)NULL, GPIO_GPIO31, IRQ_NONE},
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{32, (uint32_t)NULL, GPIO_GPIO32, IRQ_NONE},
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{33, (uint32_t)NULL, GPIO_GPIO33, IRQ_NONE},
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{34, (uint32_t)NULL, GPIO_GPIO34, IRQ_NONE},
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{35, (uint32_t)NULL, GPIO_GPIO35, IRQ_NONE},
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{36, (uint32_t)NULL, GPIO_GPIO36, IRQ_NONE},
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{37, (uint32_t)NULL, GPIO_GPIO37, IRQ_NONE},
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{38, (uint32_t)NULL, GPIO_GPIO38, IRQ_NONE},
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{39, (uint32_t)NULL, GPIO_GPIO39, IRQ_NONE},
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{40, (uint32_t)NULL, GPIO_GPIO40, IRQ_NONE},
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{41, (uint32_t)NULL, GPIO_GPIO41, IRQ_NONE},
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{42, (uint32_t)NULL, GPIO_GPIO42, IRQ_NONE},
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{43, (uint32_t)NULL, GPIO_GPIO43, IRQ_NONE},
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{44, (uint32_t)NULL, GPIO_GPIO44, IRQ_NONE},
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{45, (uint32_t)NULL, GPIO_GPIO45, IRQ_NONE},
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{46, (uint32_t)NULL, GPIO_GPIO46, IRQ_NONE},
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{47, (uint32_t)NULL, GPIO_GPIO47, IRQ_NONE},
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{48, (uint32_t)NULL, GPIO_GPIO48, IRQ_NONE},
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{49, (uint32_t)NULL, GPIO_GPIO49, IRQ_NONE},
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{50, (uint32_t)NULL, GPIO_GPIO50, IRQ_NONE},
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{51, (uint32_t)NULL, GPIO_GPIO51, IRQ_NONE},
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{52, (uint32_t)NULL, GPIO_GPIO52, IRQ_NONE},
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{53, (uint32_t)NULL, GPIO_GPIO53, IRQ_NONE},
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{54, (uint32_t)NULL, GPIO_GPIO54, IRQ_NONE},
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{55, (uint32_t)NULL, GPIO_GPIO55, IRQ_NONE},
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{56, (uint32_t)NULL, GPIO_GPIO56, IRQ_NONE},
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{57, (uint32_t)NULL, GPIO_GPIO57, IRQ_NONE},
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{58, (uint32_t)NULL, GPIO_GPIO58, IRQ_NONE},
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{59, (uint32_t)NULL, GPIO_GPIO59, IRQ_NONE},
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{60, (uint32_t)NULL, GPIO_GPIO60, IRQ_NONE},
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{61, (uint32_t)NULL, GPIO_GPIO61, IRQ_NONE},
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{62, (uint32_t)NULL, GPIO_GPIO62, IRQ_NONE},
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{63, (uint32_t)NULL, GPIO_GPIO63, IRQ_NONE},
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{64, (uint32_t)NULL, GPIO_GPIO64, IRQ_NONE},
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{65, (uint32_t)NULL, GPIO_GPIO65, IRQ_NONE},
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{66, (uint32_t)NULL, GPIO_GPIO66, IRQ_NONE},
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{67, (uint32_t)NULL, GPIO_GPIO67, IRQ_NONE},
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{68, (uint32_t)NULL, GPIO_GPIO68, IRQ_NONE},
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{69, (uint32_t)NULL, GPIO_GPIO69, IRQ_NONE},
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{70, (uint32_t)NULL, GPIO_GPIO70, IRQ_NONE},
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{71, (uint32_t)NULL, GPIO_GPIO71, IRQ_NONE},
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{72, (uint32_t)NULL, GPIO_GPIO72, IRQ_NONE}
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};
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static gpio_irq_handler irq_handler;
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uint32_t s5js100_get_intpin(unsigned int ch);
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int s5js100_configinterrupt(uint32_t cfgset, uint32_t nirq);
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void s5js100_gpio_clear_pending(uint32_t pincfg);
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static inline void handle_interrupt_in(uint32_t channel)
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{
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int pin;
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gpio_irq_event event;
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pin = s5js100_get_intpin(channel);
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if (pin < 0) {
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return;
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}
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event = pins[pin].event;
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MBED_ASSERT(pin < PIN_NUM);
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irq_handler(pins[pin].ids, pins[pin].event); //should be fixed by polarity
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#if GPIO_EINT_DEBOUNCE
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hw_delay_us(200000);
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#endif
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// toggle Interrupt condition
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if (event == IRQ_RISE) {
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pins[pin].pincfg &= ~(GPIO_EINT_MASK);
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pins[pin].event = IRQ_FALL;
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pins[pin].pincfg |= GPIO_EINT | GPIO_EINT_FALLING_EDGE;
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}
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if (event == IRQ_FALL) {
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pins[pin].pincfg &= ~(GPIO_EINT_MASK);
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pins[pin].event = IRQ_RISE;
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pins[pin].pincfg |= GPIO_EINT | GPIO_EINT_RISING_EDGE;
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}
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s5js100_configinterrupt(pins[pin].pincfg, (pins[pin].pincfg & GPIO_IRQ_MASK) >> GPIO_IRQ_SHIFT);
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s5js100_gpio_clear_pending(pins[pin].pincfg); //
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}
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void gpio0_irq(void)
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{
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handle_interrupt_in(0);
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}
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void gpio1_irq(void)
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{
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handle_interrupt_in(1);
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}
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void gpio2_irq(void)
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{
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handle_interrupt_in(2);
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}
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int gpio_pin_mode(PinName pin, PinMode mode)
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{
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if (mode == PullUp) {
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pins[pin].pincfg &= ~(GPIO_PUPD_MASK);
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pins[pin].pincfg |= GPIO_PULLUP;
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}
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if (mode == PullDown) {
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pins[pin].pincfg &= ~(GPIO_PUPD_MASK);
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pins[pin].pincfg |= GPIO_PULLDOWN;
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}
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return 0;
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}
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int gpio_irq_init(gpio_irq_t *obj, PinName pin,
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gpio_irq_handler handler, uint32_t id)
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{
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if (pin == NC) {
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return -1;
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}
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MBED_ASSERT(pin < PIN_NUM);
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obj->ch = pin;
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irq_handler = handler;
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// set handler for apps
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pins[obj->ch].ids = id;
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NVIC_SetVector((IRQn_Type)(PININT_IRQ0), (uint32_t)gpio0_irq);
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NVIC_SetVector((IRQn_Type)(PININT_IRQ1), (uint32_t)gpio1_irq);
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NVIC_SetVector((IRQn_Type)(PININT_IRQ2), (uint32_t)gpio2_irq);
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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SCB_InvalidateICache();
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#endif
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ0));
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ1));
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ2));
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return 0;
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}
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void gpio_irq_free(gpio_irq_t *obj)
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{
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}
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void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
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{
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if (IRQ_RISE == event) {
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//obj->flagR = (uint8_t)enable;
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#if GPIO_EINT_LEVEL
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pins[obj->ch].pincfg &= ~(GPIO_INT_MASK | GPIO_EINT_MASK | GPIO_PUPD_MASK);
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pins[obj->ch].pincfg |= GPIO_EINT | GPIO_EINT_HIGH | GPIO_PULLDOWN;
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#else
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pins[obj->ch].pincfg |= GPIO_EINT | GPIO_EINT_RISING_EDGE;
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#endif
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pins[obj->ch].event = event;
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} else {
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//obj->flagF = (uint8_t)enable;
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#if GPIO_EINT_LEVEL
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pins[obj->ch].pincfg &= ~(GPIO_INT_MASK | GPIO_EINT_MASK | GPIO_PUPD_MASK);
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pins[obj->ch].pincfg |= GPIO_EINT | GPIO_EINT_LOW | GPIO_PULLUP;
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#else
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pins[obj->ch].pincfg |= GPIO_EINT | GPIO_EINT_FALLING_EDGE;
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#endif
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pins[obj->ch].event = event;
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}
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s5js100_configgpio(pins[obj->ch].pincfg);
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}
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void gpio_irq_enable(gpio_irq_t *obj)
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{
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NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ0 + (obj->ch / 32)));
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}
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void gpio_irq_disable(gpio_irq_t *obj)
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{
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NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ0 + (obj->ch / 32)));
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}
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