Import Mbed OS hard-float snapshot
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Beslan
329
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_pl011_api.c
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329
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_pl011_api.c
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/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#if DEVICE_SERIAL
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// math.h required for floating point operations for baud rate calculation
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#include <math.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "device.h"
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#include "serial_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PinNames.h"
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#include "mbed_error.h"
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#include "mbed_assert.h"
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#include "gpio_api.h"
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#define UART_PTR(ptr) ((S5JS100_UART_TypeDef *)(ptr))
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static uart_irq_handler irq_handler[PL011_UART_MAX];
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struct serial_context_data_s {
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uint32_t serial_irq_id;
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gpio_t sw_rts, sw_cts;
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uint8_t count, rx_irq_set_flow, rx_irq_set_api;
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};
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static struct serial_context_data_s uart_data[PL011_UART_MAX];
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/******************************************************************************
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* INTERRUPTS HANDLING
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******************************************************************************/
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static inline void uart_irq(t_pl011_ports_enum index,
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UARTName uart)
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{
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(uart);
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int irq_type = 0xFFFF; /* type none */
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if (!(p_PL011_UART->FR & 1u << 5)) {
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if (p_PL011_UART->IMSC & 1u << 5) {
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irq_type = TxIrq;
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}
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}
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if (p_PL011_UART->MIS & (1u << 4) || p_PL011_UART->MIS & (1u << 6)) {
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/*
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Rx Interrupt & Rx Timeout Interrupt
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The receive timeout interrupt is asserted when the receive FIFO is not empty,
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and no further data is received over a 32-bit period.
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*/
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irq_type = RxIrq;
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}
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if (irq_type == RxIrq) {
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if (uart_data[index].rx_irq_set_api) {
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(irq_handler[index])(uart_data[index].serial_irq_id, irq_type);
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}
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}
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if (irq_type == TxIrq) {
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/* Clear the TX interrupt Flag */
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/* UART TX */
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} else {
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/* Clear the Rx interupt Flag */
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/* UART RX */
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}
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}
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static void uart2_irq()
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{
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uart_irq(PL011_UART0_ID, UART_2);
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}
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static void uart3_irq()
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{
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uart_irq(PL011_UART1_ID, UART_3);
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}
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static void pl011_serial_irq_set_internal(void *obj, SerialIrq irq, uint32_t enable)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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if (enable) {
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p_PL011_UART->IMSC = 0x50; //interrupt by Rx Timeout & Rx (for fifo mode)
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} else if ((irq == TxIrq) || (uart_data[priv->index].rx_irq_set_api
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+ uart_data[priv->index].rx_irq_set_flow == 0)) {
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p_PL011_UART->IMSC = 0; //interrupt by Rx Timeout & Rx (for fifo mode)
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}
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}
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// serial_baud
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// set the baud rate, taking in to account the current SystemFrequency
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static void pl011_serial_baud(void *obj, int baudrate)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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uint32_t sclk = 0;
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float div, frac;
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switch (priv->index) {
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case PL011_UART0_ID:
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sclk = cal_clk_getrate(d1_uart0);
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break;
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case PL011_UART1_ID:
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sclk = cal_clk_getrate(d1_uart1);
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break;
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default:
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MBED_ASSERT(false);
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}
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div = ((float)sclk / (float)(baudrate * 16));
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frac = (uint32_t)(((div - (int32_t)div) * 64));
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p_PL011_UART->IBRD = (uint32_t)div;
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p_PL011_UART->FBRD = (uint32_t)frac;
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}
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static void pl011_serial_format(void *obj, int data_bits,
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SerialParity parity, int stop_bits)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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uint32_t reg;
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switch (data_bits) {
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case 5:
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reg = 0;
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break;
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case 6:
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reg = 1 << 5;
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break;
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case 7:
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reg = 2 << 5;
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break;
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default:
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reg = 3 << 5;
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}
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switch (parity) {
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case ParityNone:
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reg |= 0;
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break;
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case ParityOdd:
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reg |= 4;
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break;
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case ParityEven:
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reg |= 6;
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break;
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case ParityForced1:
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reg |= 5;
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break;
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case ParityForced0:
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reg |= 7;
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break;
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}
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if (stop_bits == 2) {
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reg |= 1 << 3;
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}
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/* Enable FIFO */
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reg |= 1 << 4;
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p_PL011_UART->LCRH = reg;
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}
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static void pl011_serial_irq_handler(void *obj, uart_irq_handler handler, uint32_t id)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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irq_handler[priv->index] = handler;
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uart_data[priv->index].serial_irq_id = id;
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}
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static void pl011_serial_irq_set(void *obj, SerialIrq irq, uint32_t enable)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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if (RxIrq == irq) {
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uart_data[priv->index].rx_irq_set_api = enable;
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}
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pl011_serial_irq_set_internal(obj, irq, enable);
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}
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static int pl011_serial_readable(void *obj)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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return !(p_PL011_UART->FR & (1u << 4));
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}
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static int pl011_serial_writable(void *obj)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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return !(p_PL011_UART->FR & (1u << 5));
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}
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static int pl011_serial_getc(void *obj)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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int data;
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while (!serial_readable(priv));
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data = p_PL011_UART->DR & 0xFF;
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return data;
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}
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static void pl011_serial_putc(void *obj, int c)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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while (!serial_writable(priv));
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p_PL011_UART->DR = c;
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}
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#if DEVICE_SERIAL_FC
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static void pl011_serial_set_flow_control(struct serial_s *obj, FlowControl type,
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PinName rxflow, PinName txflow)
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{
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error("pl011 flow control is not implenemted");
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}
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#endif
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void pl011_serial_init(void *obj, PinName tx, PinName rx)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_UART_TypeDef *p_PL011_UART = UART_PTR(priv->uart);
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/* Declare a variable of type IRQn, initialise to 0 */
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IRQn_Type irq_n = (IRQn_Type)0;
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uint32_t vector = 0;
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switch ((int)priv->uart) {
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case UART_2:
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irq_n = S5JS100_IRQ_UART0;
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vector = (uint32_t)&uart2_irq;
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priv->index = PL011_UART0_ID;
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break;
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case UART_3 :
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irq_n = S5JS100_IRQ_UART1;
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vector = (uint32_t)&uart3_irq;
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priv->index = PL011_UART1_ID;
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break;
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}
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/* Enable UART and RX/TX path*/
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p_PL011_UART->CR = 0x301;
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/* RX/TX fifo half full interrupt*/
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p_PL011_UART->IFLS = (2 << 3) | 2;
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/* clear all interrupts mask */
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p_PL011_UART->IMSC = 0x0;
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/* Clear all interripts */
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p_PL011_UART->ICR = 0x7FF;
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/* MODESEL as default UART*/
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p_PL011_UART->MODESEL = 0x0;
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priv->ops.serial_baud = pl011_serial_baud;
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priv->ops.serial_format = pl011_serial_format;
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priv->ops.serial_irq_handler = pl011_serial_irq_handler;
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priv->ops.serial_irq_set = pl011_serial_irq_set;
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priv->ops.serial_putc = pl011_serial_putc;
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priv->ops.serial_writable = pl011_serial_writable;
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priv->ops.serial_getc = pl011_serial_getc;
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priv->ops.serial_readable = pl011_serial_readable;
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#if DEVICE_SERIAL_FC
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priv->ops.serial_set_flow_control = pl011_serial_set_flow_control;
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#endif
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uart_data[priv->index].sw_rts.pin = NC;
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uart_data[priv->index].sw_cts.pin = NC;
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/* Assign IRQ in advance and enable, all are masked anyways */
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NVIC_SetVector(irq_n, vector);
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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SCB_InvalidateICache();
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#endif
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NVIC_EnableIRQ(irq_n);
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/* dissable IRQ by this if needed:
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NVIC_DisableIRQ(irq_n);
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*/
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}
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#endif // DEVICE_SERIAL
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