Import Mbed OS hard-float snapshot
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Beslan
344
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_usi_api.c
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344
targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_usi_api.c
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/****************************************************************************
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*
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* Copyright 2020 Samsung Electronics All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied. See the License for the specific
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* language governing permissions and limitations under the License.
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*
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****************************************************************************/
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#if DEVICE_SERIAL
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// math.h required for floating point operations for baud rate calculation
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#include <math.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "device.h"
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#include "serial_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PinNames.h"
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#include "mbed_error.h"
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#include "gpio_api.h"
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#include "s5js100.h"
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#include "mbed_wait_api.h"
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#include "mbed_thread.h"
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#define USI_PTR(ptr) ((S5JS100_USI_UART_TypeDef *)(ptr))
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static uart_irq_handler irq_handler[USI_MAX_PORTS];
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static uint32_t serial_irq_id[USI_MAX_PORTS] = {0};
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/****************** Internal code ************************/
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static inline void uart_irq(uint32_t intstatus, uint32_t index,
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UARTName uart)
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{
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if (intstatus & (1 << 0)) {
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(irq_handler[index])(serial_irq_id[index], RxIrq);
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} else if (intstatus & (1 << 1)) {
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// RTS Int
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} else if (intstatus & (1 << 2)) {
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(irq_handler[index])(serial_irq_id[index], TxIrq);
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} else if (intstatus & (1 << 3)) {
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// CTS Int
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} else {
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}
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USI_PTR(uart)->UINTP = intstatus;
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}
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static void uart0_irq()
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{
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uart_irq(S5JS100_USI0_UART->UINTP & 0xF, 0, UART_0);
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}
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static void uart1_irq()
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{
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uart_irq(S5JS100_USI1_UART->UINTP & 0xF, 1, UART_1);
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}
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/*********************** API ******************************/
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// serial_baud
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// set the baud rate, taking in to account the current SystemFrequency
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static void usi_serial_baud(void *obj, int baudrate)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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int32_t sclk = 0;
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float div, frac;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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switch ((int)priv->uart) {
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case UART_0:
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/* UBRDIV and UFRACVAL */
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sclk = cal_clk_getrate(d1_usi0);
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break;
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case UART_1:
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/* UBRDIV and UFRACVAL */
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sclk = cal_clk_getrate(d1_usi1);
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break;
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default:
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MBED_ASSERT(false);
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}
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div = ((float)sclk / (float)(baudrate * 16)) - 1.0;
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frac = (uint32_t)(((div - (int32_t)div) * 16));
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p_USI_UART->UBRDIV = (uint32_t)div;
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p_USI_UART->UFRACVAL = (uint32_t)frac;
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}
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static void usi_serial_format(void *obj, int data_bits,
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SerialParity parity, int stop_bits)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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uint32_t reg;
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switch (data_bits) {
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case 5:
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reg = UART_ULCON_DATABITS_5BITS;
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break;
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case 6:
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reg = UART_ULCON_DATABITS_6BITS;
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break;
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case 7:
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reg = UART_ULCON_DATABITS_7BITS;
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break;
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default:
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reg = UART_ULCON_DATABITS_8BITS;
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}
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switch (parity) {
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case ParityNone:
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reg |= UART_ULCON_PARITY_NONE;
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break;
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case ParityOdd:
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reg |= UART_ULCON_PARITY_ODD;
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break;
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case ParityEven:
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reg |= UART_ULCON_PARITY_EVEN;
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break;
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case ParityForced1:
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reg |= UART_ULCON_PARITY_FORCE1;
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break;
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case ParityForced0:
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reg |= UART_ULCON_PARITY_FORCE0;
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break;
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}
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if (stop_bits == 2) {
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reg |= UART_ULCON_STOPBITS_2BITS;
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}
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p_USI_UART->ULCON = reg;
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}
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static void usi_serial_irq_handler(void *obj, uart_irq_handler handler, uint32_t id)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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irq_handler[priv->index] = handler;
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serial_irq_id[priv->index] = id;
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}
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static void usi_serial_irq_set(void *obj, SerialIrq irq, uint32_t enable)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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switch (irq) {
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case RxIrq:
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if (enable) {
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p_USI_UART->UINTM &= ~(UART_UINTM_RXD_MASK);
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} else {
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p_USI_UART->UINTM |= UART_UINTM_RXD_MASK;
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p_USI_UART->UINTP = UART_UINTP_RXD;
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}
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break;
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case TxIrq:
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if (enable) {
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p_USI_UART->UINTM &= ~(UART_UINTM_TXD_MASK);
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} else {
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p_USI_UART->UINTM |= UART_UINTM_TXD_MASK;
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p_USI_UART->UINTP = UART_UINTP_TXD;
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}
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break;
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}
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}
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static int usi_serial_writable(void *obj)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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return !(p_USI_UART->UFSTAT & UART_UFSTAT_TX_FIFO_FULL);
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}
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static void usi_serial_putc(void *obj, int c)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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while (!serial_writable(obj));
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p_USI_UART->UTXH = c;
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}
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static int usi_serial_readable(void *obj)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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return (p_USI_UART->UFSTAT & (UART_UFSTAT_RX_FIFO_COUNT_MASK | UART_UFSTAT_RX_FIFO_FULL));
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}
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static int usi_serial_getc(void *obj)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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int data;
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while (!serial_readable(obj));
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data = p_USI_UART->URXH & 0xFF;
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return data;
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}
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#if DEVICE_SERIAL_FC
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static void usi_serial_set_flow_control(struct serial_s *obj, FlowControl type,
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PinName rxflow, PinName txflow)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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// Checked used UART name (UART_1, UART_2, ...)
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if (type == FlowControlRTSCTS) {
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p_USI_UART->UMCON = UART_UMCON_RTS_TRIG_14BYTES | UART_UMCON_AFC_ENABLE;
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} else {
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p_USI_UART->UMCON = UART_UMCON_AFC_DISABLE;
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}
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}
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#endif
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void usi_serial_init(void *obj, PinName tx, PinName rx)
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{
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struct serial_s *priv = (struct serial_s *)obj;
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S5JS100_USI_UART_TypeDef *p_USI_UART = USI_PTR(priv->uart);
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IRQn_Type irq_n = (IRQn_Type)0;
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uint32_t vector = 0;
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p_USI_UART->UINTM = 0xF;
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p_USI_UART->UINTP = 0xF;
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switch ((int)priv->uart) {
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case UART_0:
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if (! USI_VERSION_UART(S5JS100_USI0_REG->VERSION)) {
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/* UART NOT SUPPORTED */
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MBED_ASSERT(false);
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}
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S5JS100_USI0_REG->CON = USI_CON_RST;
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S5JS100_SYSCFG_USI0_CONF = USI_CONFIG_UART;
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S5JS100_USI0_REG->CON &= ~USI_CON_RST;
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priv->index = USI0_PORT_ID;
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priv->rx_fifo_depth = USI_RXFIFO(S5JS100_USI0_REG->FIFO_DEPTH);
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priv->tx_fifo_depth = USI_TXFIFO(S5JS100_USI0_REG->FIFO_DEPTH);
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irq_n = S5JS100_IRQ_USI0;
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vector = (uint32_t)&uart0_irq;
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break;
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case UART_1:
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if (! USI_VERSION_UART(S5JS100_USI1_REG->VERSION)) {
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/* UART NOT SUPPORTED */
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while (1);
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}
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S5JS100_USI1_REG->CON = USI_CON_RST;
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S5JS100_SYSCFG_USI1_CONF = USI_CONFIG_UART;
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S5JS100_USI1_REG->CON &= ~USI_CON_RST;
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priv->index = USI1_PORT_ID;
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priv-> rx_fifo_depth = USI_RXFIFO(S5JS100_USI1_REG->FIFO_DEPTH);
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priv-> tx_fifo_depth = USI_TXFIFO(S5JS100_USI1_REG->FIFO_DEPTH);
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irq_n = S5JS100_IRQ_USI1;
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vector = (uint32_t)&uart1_irq;
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break;
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}
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// Disable all interrupts and clear pendings
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p_USI_UART->UINTM = UART_UINTM_MODEM_MASK | UART_UINTM_TXD_MASK |
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UART_UINTM_RXD_MASK | UART_UINTM_ERROR_MASK;
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p_USI_UART->UINTP = UART_UINTP_MODEM | UART_UINTP_TXD |
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UART_UINTP_ERROR | UART_UINTP_RXD;
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// reset FIFO and set interrupt trigger level
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p_USI_UART->UFCON = UART_UFCON_TX_FIFO_TRIG_14BYTES | UART_UFCON_RX_FIFO_TRIG_14BYTES |
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UART_UFCON_TX_FIFO_RESET | UART_UFCON_RX_FIFO_RESET |
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UART_UFCON_FIFO_ENABLE ;
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//wait_ms(10);
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thread_sleep_for(10);
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//Enable TX/RX fifo int/poll mode with RX timeout of 32 bits duration
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p_USI_UART->UCON = UART_UCON_RX_TOUT_32FRAMES | UART_UCON_RX_TOUTINT_ENABLE |
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UART_UCON_TX_INTTYPE_LEVEL | UART_UCON_RX_INTTYPE_LEVEL |
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UART_UCON_TX_MODE_IRQPOLL | UART_UCON_RX_MODE_IRQPOLL;
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priv->ops.serial_baud = usi_serial_baud;
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priv->ops.serial_format = usi_serial_format;
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priv->ops.serial_irq_handler = usi_serial_irq_handler;
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priv->ops.serial_irq_set = usi_serial_irq_set;
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priv->ops.serial_putc = usi_serial_putc;
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priv->ops.serial_writable = usi_serial_writable;
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priv->ops.serial_getc = usi_serial_getc;
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priv->ops.serial_readable = usi_serial_readable;
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#if DEVICE_SERIAL_FC
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priv->ops.serial_set_flow_control = usi_serial_set_flow_control;
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#endif
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/* Assign IRQ in advance and enable, all are masked anyways */
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NVIC_SetVector(irq_n, vector);
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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SCB_InvalidateICache();
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#endif
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NVIC_EnableIRQ(irq_n);
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/* dissable IRQ by this if needed:
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NVIC_DisableIRQ(irq_n);
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*/
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}
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#endif // DEVICE_SERIAL
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