Import Mbed OS hard-float snapshot

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h

@@ -0,0 +1,103 @@
+/***************************************************************************//**
+ * @file PinNames.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+#ifndef MBED_COMMONPINNAMES_H
+#define MBED_COMMONPINNAMES_H
+
+#include "em_gpio.h"
+
+/* EFM32 Pin Names
+ * First 4 bits represent pin number, the remaining
+ * bits represent port number (A = 0, B = 1, ...)
+ */
+#define EFM32_STANDARD_PIN_DEFINITIONS                                                             \
+    PA0 =  0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \
+    PB0 =  1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \
+    PC0 =  2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \
+    PD0 =  3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \
+    PE0 =  4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \
+    PF0 =  5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \
+    PG0 =  6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \
+    PH0 =  7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \
+    PI0 =  8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \
+    PJ0 =  9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \
+    PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \
+    NC = (int) 0xFFFFFFFF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT = 0,
+    PIN_OUTPUT = 1
+} PinDirection;
+
+/* 0x10 represents setting the DOUT register (see efm32 modes in ref. manual) */
+typedef enum {
+    /* EFM32 pin modes */
+    Disabled            = gpioModeDisabled,
+    DisabledPullUp      = gpioModeDisabled | 0x10,
+    Input               = gpioModeInput,
+    InputFilter         = gpioModeInput | 0x10,
+    InputPullDown       = gpioModeInputPull,
+    InputPullUp         = gpioModeInputPull | 0x10,
+    InputPullFilterDown = gpioModeInputPullFilter,
+    InputPullFilterUp   = gpioModeInputPullFilter | 0x10,
+    PushPull            = gpioModePushPull,
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )
+    PushPullDrive       = gpioModePushPullDrive,
+#endif
+    WiredOr             = gpioModeWiredOr,
+    WiredOrPullDown     = gpioModeWiredOrPullDown,
+    WiredAnd            = gpioModeWiredAnd,
+    WiredAndFilter      = gpioModeWiredAndFilter,
+    WiredAndPullUp      = gpioModeWiredAndPullUp,
+    WiredAndPullUpFilter = gpioModeWiredAndPullUpFilter,
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )
+    WiredAndDrive       = gpioModeWiredAndDrive,
+    WiredAndDriveFilter = gpioModeWiredAndDriveFilter,
+    WiredAndDrivePullUp = gpioModeWiredAndDrivePullUp,
+    WiredAndDrivePullUpFilter = gpioModeWiredAndDrivePullUpFilter,
+#endif
+
+    /* mbed modes:
+     * PullUp, PullDown, PullNone, OpenDrain
+     *
+     * mbed default digital input mode:
+     * PullDefault
+     *
+     * mbed default digital output mode:
+     * PullNone
+     */
+    PullUp = InputPullUp,
+    PullDown = InputPullDown,
+    OpenDrain = WiredAnd,
+    PullNone = PushPull,
+    PullDefault = PushPull
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h

@@ -0,0 +1,71 @@
+/***************************************************************************//**
+ * @file PortNames.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#include "em_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+#if ( _GPIO_PORT_A_PIN_COUNT > 0 )
+    PortA = gpioPortA, /**< Port A */
+#endif
+#if ( _GPIO_PORT_B_PIN_COUNT > 0 )
+    PortB = gpioPortB, /**< Port B */
+#endif
+#if ( _GPIO_PORT_C_PIN_COUNT > 0 )
+    PortC = gpioPortC, /**< Port C */
+#endif
+#if ( _GPIO_PORT_D_PIN_COUNT > 0 )
+    PortD = gpioPortD, /**< Port D */
+#endif
+#if ( _GPIO_PORT_E_PIN_COUNT > 0 )
+    PortE = gpioPortE, /**< Port E */
+#endif
+#if ( _GPIO_PORT_F_PIN_COUNT > 0 )
+    PortF = gpioPortF, /**< Port F */
+#endif
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 )
+    PortG = gpioPortG, /**< Port G */
+#endif
+#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 )
+    PortH = gpioPortH, /**< Port H */
+#endif
+#if defined( _GPIO_PORT_I_PIN_COUNT ) && ( _GPIO_PORT_I_PIN_COUNT > 0 )
+    PortI = gpioPortI, /**< Port I */
+#endif
+#if defined( _GPIO_PORT_J_PIN_COUNT ) && ( _GPIO_PORT_J_PIN_COUNT > 0 )
+    PortJ = gpioPortJ, /**< Port J */
+#endif
+#if defined( _GPIO_PORT_K_PIN_COUNT ) && ( _GPIO_PORT_K_PIN_COUNT > 0 )
+    PortK = gpioPortK, /**< Port K */
+#endif
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h

@@ -0,0 +1,117 @@
+/***************************************************************************//**
+ * @file clocking.h
+ * @brief Clock selection calculations
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+#ifndef MBED_CLOCKING_H
+#define MBED_CLOCKING_H
+
+#include "em_cmu.h"
+
+/* Clock definitions */
+#define LFXO    0
+#define HFXO    1
+#define LFRCO   2
+#define HFRCO   3
+#if !defined(_EFM32_GECKO_FAMILY)
+#define ULFRCO  4
+#endif
+
+/* Low Energy peripheral clock source.
+ * Options:
+ *  * LFXO: external crystal, please define frequency.
+ *  * LFRCO: internal RC oscillator (32.768kHz)
+ *  * ULFRCO: internal ultra-low power RC oscillator (available down to EM3) (1kHz)
+ */
+#ifndef LOW_ENERGY_CLOCK_SOURCE
+#define LOW_ENERGY_CLOCK_SOURCE LFXO
+#endif
+
+/** Core clock source.
+ * Options:
+ *  * HFXO: external crystal, please define frequency.
+ *  * HFRCO: High-frequency internal RC oscillator. Please select band as well.
+ */
+#ifndef CORE_CLOCK_SOURCE
+#define CORE_CLOCK_SOURCE   HFRCO
+#if defined(_CMU_HFRCOCTRL_BAND_MASK)
+#define HFRCO_FREQUENCY_ENUM   _CMU_HFRCOCTRL_BAND_21MHZ
+#define HFRCO_FREQUENCY        21000000
+#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
+#define HFRCO_FREQUENCY_ENUM   cmuHFRCOFreq_32M0Hz
+#define HFRCO_FREQUENCY        32000000
+#endif
+#endif // CORE_CLOCK_SOURCE
+
+#if !defined(LFXO_FREQUENCY) && (LOW_ENERGY_CLOCK_SOURCE == LFXO)
+#error "LFXO frequency is undefined!"
+#endif
+
+#if !defined(HFXO_FREQUENCY) && (CORE_CLOCK_SOURCE == HFXO)
+#error "HFXO frequency is undefined!"
+#endif
+
+#if (LOW_ENERGY_CLOCK_SOURCE == LFXO)
+#define LOW_ENERGY_CLOCK_FREQUENCY  LFXO_FREQUENCY
+#elif (LOW_ENERGY_CLOCK_SOURCE == LFRCO)
+#define LOW_ENERGY_CLOCK_FREQUENCY  32768
+#elif (LOW_ENERGY_CLOCK_SOURCE == ULFRCO)
+#define LOW_ENERGY_CLOCK_FREQUENCY  1000
+#else
+#error "Unknown Low Energy Clock selection"
+#endif
+
+#if( CORE_CLOCK_SOURCE == HFXO)
+# define REFERENCE_FREQUENCY HFXO_FREQUENCY
+#elif( CORE_CLOCK_SOURCE == HFRCO)
+#if !defined(HFRCO_FREQUENCY)
+# error "HFRCO frequency is not defined!"
+#else
+# define REFERENCE_FREQUENCY HFRCO_FREQUENCY
+#endif
+#endif
+
+#if ( LOW_ENERGY_CLOCK_SOURCE == LFXO )
+# define LEUART_USING_LFXO
+# if ( (defined(CMU_CTRL_HFLE) || defined(CMU_CTRL_WSHFLE) ) && (REFERENCE_FREQUENCY > 24000000) )
+#  define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 4)
+# else
+#  define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 2)
+# endif
+# define LEUART_LF_REF_FREQ LFXO_FREQUENCY
+#else
+# if ( (defined(CMU_CTRL_HFLE) || defined(CMU_CTRL_WSHFLE) ) && (REFERENCE_FREQUENCY > 24000000) )
+#  define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 4)
+# else
+#  define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 2)
+# endif
+#endif
+
+/* Adjust this to change speed of RTC and LP ticker ticks */
+#define RTC_CLOCKDIV        cmuClkDiv_1
+/* Adjust this to match RTC_CLOCKDIV as integer value */
+#define RTC_CLOCKDIV_INT    1U
+/* Adjust this to match RTC_CLOCKDIV as shift for 1 second worth of ticks.
+ * E.g. with 32768 Hz crystal and CLOCKDIV of 8, 1 second is 4096 ticks.
+ * 4096 equals 1 << 12, so RTC_FREQ_SHIFT needs to be 12. */
+#define RTC_FREQ_SHIFT      15U
+
+#endif

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/cmsis.h

@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in EFM32 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "em_device.h"
+#include "cmsis_nvic.h"
+
+#endif

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/cmsis_nvic.h

@@ -0,0 +1,18 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS        (16 + EXT_IRQ_COUNT)     // CORE + MCU Peripherals
+
+/* For GCC, use dynamic vector table placement since otherwise we run into an alignment conflict */
+#if (defined (__GNUC__) && (!defined(__CC_ARM) && (!defined(__ARMCC_VERSION))))
+extern uint32_t __start_vector_table__;       // Dynamic vector positioning in GCC
+#define NVIC_RAM_VECTOR_ADDRESS (&__start_vector_table__)
+#else
+#define NVIC_RAM_VECTOR_ADDRESS 0x20000000    // Vectors positioned at start of RAM
+#endif
+
+#endif /* MBED_CMSIS_NVIC_H */

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/device.h

@@ -0,0 +1,30 @@
+/***************************************************************************//**
+ * @file device.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#include "cmsis.h"
+#include "objects.h"
+#include "device_peripherals.h"
+
+#endif

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c

@@ -0,0 +1,130 @@
+/***************************************************************************//**
+ * @file mbed_overrides.c
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+#include "em_chip.h"
+#include "em_device.h"
+#include "em_cmu.h"
+#include "em_emu.h"
+#include "device_peripherals.h"
+#include "device.h"
+#include "em_usart.h"
+#include "gpio_api.h"
+#include "clocking.h"
+
+gpio_t bc_enable;
+
+/* Called before main - implement here if board needs it.
+ * Otherwise, let the application override this if necessary */
+void mbed_sdk_init()
+{
+    CHIP_Init();
+
+#if defined(_SILICON_LABS_32B_SERIES_1)
+#if defined(EMU_NO_DCDC)
+    EMU_DCDCPowerOff();
+#else
+    EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_STK_DEFAULT;
+    EMU_DCDCInit(&dcdcInit);
+#endif
+
+#if (CORE_CLOCK_SOURCE == HFXO)
+    // Only init HFXO if not already done (e.g. by bootloader)
+    if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) {
+#if defined(_EFR_DEVICE)
+        CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_WSTK_DEFAULT;
+#else
+        CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_STK_DEFAULT;
+#endif
+        CMU_HFXOInit(&hfxoInit);
+    }
+#endif
+#endif
+
+    /* Set up the clock sources for this chip */
+#if( CORE_CLOCK_SOURCE == HFXO)
+    CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
+    SystemHFXOClockSet(HFXO_FREQUENCY);
+#elif( CORE_CLOCK_SOURCE == HFRCO)
+    CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO);
+# if defined _CMU_HFRCOCTRL_BAND_MASK
+    CMU_HFRCOBandSet(HFRCO_FREQUENCY_ENUM);
+# elif defined _CMU_HFRCOCTRL_FREQRANGE_MASK
+    CMU_HFRCOFreqSet(HFRCO_FREQUENCY_ENUM);
+# else
+#  error "Can't set HFRCO frequency"
+# endif
+#else
+# error "Core clock selection not valid (mbed_overrides.c)"
+#endif
+
+    CMU_ClockEnable(cmuClock_CORELE, true);
+
+#if( LOW_ENERGY_CLOCK_SOURCE == LFXO )
+# ifdef _CMU_LFACLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);
+# endif
+# ifdef _CMU_LFBCLKEN0_MASK
+    /* cmuClock_LFB (to date) only has LEUART peripherals.
+    *  This gets set automatically whenever you create serial objects using LEUART
+    */
+# endif
+# ifdef _CMU_LFECLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO);
+# endif
+    SystemLFXOClockSet(LFXO_FREQUENCY);
+
+#elif( LOW_ENERGY_CLOCK_SOURCE == LFRCO )
+# ifdef _CMU_LFACLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO);
+# endif
+# ifdef _CMU_LFBCLKEN0_MASK
+    //CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFRCO);
+# endif
+# ifdef _CMU_LFECLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO);
+# endif
+
+#elif( LOW_ENERGY_CLOCK_SOURCE == ULFRCO)
+# ifdef _CMU_LFACLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_ULFRCO);
+# endif
+# ifdef _CMU_LFBCLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_ULFRCO);
+# endif
+# ifdef _CMU_LFECLKEN0_MASK
+    CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_ULFRCO);
+# endif
+#else
+# error "Low energy clock selection not valid"
+#endif
+
+#if defined(RTCC_PRESENT)
+    /* Turn RTCC clock gate back on to keep RTC time correct */
+    CMU_ClockEnable(cmuClock_RTCC, true);
+#endif
+
+#if defined(EFM_BC_EN)
+    /* Enable BC line driver to avoid garbage on CDC port */
+    gpio_init_out_ex(&bc_enable, EFM_BC_EN, 1);
+#endif
+}

targets/TARGET_Silicon_Labs/TARGET_EFM32/common/objects.h

@@ -0,0 +1,178 @@
+/***************************************************************************//**
+ * @file objects.h
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************/
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "PortNames.h"
+#include "em_i2c.h"
+#include "em_dma.h"
+#include "em_cmu.h"
+#include "dma_api_HAL.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    PinMode mode;
+    PinDirection dir;
+} gpio_t;
+
+#if DEVICE_ANALOGIN
+struct analogin_s {
+    ADC_TypeDef *adc;
+    uint32_t channel;
+};
+#endif
+
+#if DEVICE_ANALOGOUT
+struct dac_s {
+    DAC_TypeDef *dac;
+    uint32_t channel;
+};
+#endif
+
+#if DEVICE_I2C
+struct i2c_s {
+    I2C_TypeDef *i2c;
+    uint32_t location;
+#if DEVICE_I2C_ASYNCH
+    uint32_t events;
+    I2C_TransferSeq_TypeDef xfer;
+#endif
+};
+#endif
+
+#if DEVICE_PORTOUT
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection dir;
+};
+#endif
+
+#if DEVICE_PWMOUT
+struct pwmout_s {
+    //Channel on TIMER
+    uint32_t channel;
+    PinName pin;
+};
+#endif
+
+#if DEVICE_INTERRUPTIN
+struct gpio_irq_s {
+    PinName pin;
+    uint8_t risingEdge;
+    uint8_t fallingEdge;
+};
+#endif
+
+#if DEVICE_SERIAL
+struct serial_s {
+    union {
+        USART_TypeDef *uart;
+        LEUART_TypeDef *leuart;
+    } periph;
+#ifndef _SILICON_LABS_32B_PLATFORM_2
+    uint32_t location;
+#else
+    uint32_t location_tx;
+    uint32_t location_rx;
+#endif
+    PinName rx_pin;
+    PinName tx_pin;
+#if DEVICE_SERIAL_ASYNCH
+    uint32_t events;
+    DMA_OPTIONS_t dmaOptionsTX;
+    DMA_OPTIONS_t dmaOptionsRX;
+#endif
+    uint32_t sleep_blocked;
+};
+#endif
+
+#if DEVICE_SPI
+struct spi_s {
+    USART_TypeDef *spi;
+    uint32_t location;
+    uint32_t route;
+    uint8_t bits;
+    uint8_t master;
+#if DEVICE_SPI_ASYNCH
+    uint32_t event;
+    DMA_OPTIONS_t dmaOptionsTX;
+    DMA_OPTIONS_t dmaOptionsRX;
+#endif
+};
+#endif
+
+#if DEVICE_RTC
+struct lp_timer_s {
+    uint32_t start;
+    uint32_t stop;
+};
+#endif
+
+#if DEVICE_FLASH
+struct flash_s {
+    MSC_TypeDef *msc;
+};
+#endif
+
+#if DEVICE_TRNG
+struct trng_s {
+    TRNG_TypeDef *instance;
+};
+#endif
+
+#if DEVICE_CAN
+struct can_s {
+    CAN_TypeDef *instance;
+};
+#endif
+
+#if DEVICE_QSPI
+struct qspi_s {
+    QSPI_TypeDef *instance;
+    PinName io0;
+    PinName io1;
+    PinName io2;
+    PinName io3;
+    PinName sclk;
+    PinName ssel;
+};
+#endif
+
+#if DEVICE_CRC
+//GPCRC supports any 16-bit poly, but only the CCITT 32-bit poly
+#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 16 || ((width) == 32 && (polynomial) == POLY_32BIT_ANSI))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif