Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
614
targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c
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614
targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c
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/***************************************************************************//**
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* @file i2c_api.c
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************/
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#include "device.h"
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#include "clocking.h"
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#include <stdio.h>
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#if DEVICE_I2C
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#include "mbed_assert.h"
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#include "i2c_api.h"
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#include "PeripheralPins.h"
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#include "pinmap_function.h"
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#include "em_i2c.h"
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#include "em_cmu.h"
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/** Error flags indicating I2C transfer has failed somehow. */
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/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
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/* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
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/* RXUF is only likely to occur with this SW if using a debugger peeking into */
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/* RXDATA register. Thus, we ignore those types of fault. */
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#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
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#define I2C_TIMEOUT 100000
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/* Prototypes */
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int block_and_wait_for_ack(I2C_TypeDef *i2c);
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void i2c_enable(i2c_t *obj, uint8_t enable);
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void i2c_enable_pins(i2c_t *obj, uint8_t enable);
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void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable);
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static uint8_t i2c_get_index(i2c_t *obj)
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{
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uint8_t index = 0;
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switch ((int)obj->i2c.i2c) {
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#ifdef I2C0
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case I2C_0:
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index = 0;
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break;
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#endif
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#ifdef I2C1
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case I2C_1:
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index = 1;
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break;
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#endif
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#ifdef I2C2
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case I2C_2:
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index = 2;
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break;
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#endif
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default:
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printf("I2C module not available.. Out of bound access.");
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break;
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}
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return index;
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}
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static CMU_Clock_TypeDef i2c_get_clock(i2c_t *obj)
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{
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CMU_Clock_TypeDef clock;
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switch ((int)obj->i2c.i2c) {
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#ifdef I2C0
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case I2C_0:
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clock = cmuClock_I2C0;
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break;
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#endif
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#ifdef I2C1
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case I2C_1:
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clock = cmuClock_I2C1;
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break;
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#endif
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#ifdef I2C2
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case I2C_2:
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clock = cmuClock_I2C2;
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break;
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#endif
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default:
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printf("I2C module not available.. Out of bound access. (clock)");
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clock = cmuClock_HFPER;
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break;
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}
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return clock;
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}
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void i2c_init(i2c_t *obj, PinName sda, PinName scl)
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{
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/* Find out which I2C peripheral we're asked to use */
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I2CName i2c_sda = (I2CName) pinmap_peripheral(sda, PinMap_I2C_SDA);
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I2CName i2c_scl = (I2CName) pinmap_peripheral(scl, PinMap_I2C_SCL);
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obj->i2c.i2c = (I2C_TypeDef*) pinmap_merge(i2c_sda, i2c_scl);
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MBED_ASSERT(((unsigned int) obj->i2c.i2c) != NC);
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/* You need both SDA and SCL for I2C, so configuring one of them to NC is illegal */
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MBED_ASSERT((unsigned int)sda != NC);
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MBED_ASSERT((unsigned int)scl != NC);
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/* Enable clock for the peripheral */
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CMU_ClockEnable(i2c_get_clock(obj), true);
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/* Initializing the I2C */
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/* Using default settings */
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i2c_reset(obj);
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I2C_Init_TypeDef i2cInit = I2C_INIT_DEFAULT;
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I2C_Init(obj->i2c.i2c, &i2cInit);
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/* Enable pins at correct location */
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#ifdef I2C_ROUTE_SDAPEN
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/* Find common location in pinmap */
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unsigned int loc_sda = pin_location(sda, PinMap_I2C_SDA);
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unsigned int loc_scl = pin_location(scl, PinMap_I2C_SCL);
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unsigned int loc = pinmap_merge(loc_sda, loc_scl);
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MBED_ASSERT(loc != NC);
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/* Set location */
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obj->i2c.location = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
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obj->i2c.i2c->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
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#else
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obj->i2c.i2c->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN;
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obj->i2c.location = (pin_location(sda, PinMap_I2C_SDA) << _I2C_ROUTELOC0_SDALOC_SHIFT) |
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(pin_location(scl, PinMap_I2C_SCL) << _I2C_ROUTELOC0_SCLLOC_SHIFT);
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obj->i2c.i2c->ROUTELOC0 = obj->i2c.location;
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#endif
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/* Set up the pins for I2C use */
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/* Note: Set up pins in higher drive strength to reduce slew rate */
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/* Though this requires user knowledge, since drive strength is controlled per port, not pin */
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pin_mode(scl, WiredAndPullUp);
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pin_mode(sda, WiredAndPullUp);
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/* Enable General Call Address Mode. That is; we respond to the general address (0x0) */
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obj->i2c.i2c->CTRL |= _I2C_CTRL_GCAMEN_MASK;
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/* We are assuming that there is only one master. So disable automatic arbitration */
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obj->i2c.i2c->CTRL |= _I2C_CTRL_ARBDIS_MASK;
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/* Set to master (needed if this I2C block was used previously as slave) */
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i2c_slave_mode(obj, false);
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/* Enable i2c */
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i2c_enable(obj, true);
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}
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void i2c_enable(i2c_t *obj, uint8_t enable)
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{
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I2C_Enable(obj->i2c.i2c, enable);
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if (!enable) {
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/* After a reset BUSY is usually set. We assume that we are the only master and call abort,
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* which sends nothing on the bus, it just allows us to assume that the bus is idle */
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if (obj->i2c.i2c->STATE & I2C_STATE_BUSY) {
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obj->i2c.i2c->CMD = I2C_CMD_ABORT;
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}
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}
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}
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void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable)
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{
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IRQn_Type irq_number;
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switch (i2c_get_index(obj)) {
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#ifdef I2C0
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case 0:
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irq_number = I2C0_IRQn;
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break;
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#endif
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#ifdef I2C1
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case 1:
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irq_number = I2C1_IRQn;
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break;
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#endif
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#ifdef I2C2
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case 2:
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irq_number = I2C2_IRQn;
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break;
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#endif
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}
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NVIC_SetVector(irq_number, address);
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/* Lower IRQ priority to avoid messing with asynch RX on UART */
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NVIC_SetPriority(irq_number, 1);
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if (enable) {
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NVIC_EnableIRQ(irq_number);
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} else {
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NVIC_DisableIRQ(irq_number);
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}
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}
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/* Set the frequency of the I2C interface */
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void i2c_frequency(i2c_t *obj, int hz)
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{
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/* Set frequency. As the second argument is 0,
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* HFPER clock frequency is used as reference freq */
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if (hz <= 0) return;
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/* In I2C Normal mode (50% duty), we can go up to 100kHz */
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if (hz <= 100000) {
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I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRStandard);
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}
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/* In I2C Fast mode (6:3 ratio), we can go up to 400kHz */
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else if (hz <= 400000) {
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I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRAsymetric);
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}
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/* In I2C Fast+ mode (11:6 ratio), we can go up to 1 MHz */
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else if (hz <= 1000000) {
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I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRFast);
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}
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/* Cap requested frequency at 1MHz */
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else {
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I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, 1000000, i2cClockHLRFast);
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}
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}
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/* Creates a start condition on the I2C bus */
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int i2c_start(i2c_t *obj)
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{
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I2C_TypeDef *i2c = obj->i2c.i2c;
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/* Restore pin configuration in case we changed I2C object */
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#ifdef I2C_ROUTE_SDAPEN
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obj->i2c.i2c->ROUTE = obj->i2c.location;
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#else
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obj->i2c.i2c->ROUTELOC0 = obj->i2c.location;
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#endif
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/* Ensure buffers are empty */
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i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
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if (i2c->IF & I2C_IF_RXDATAV) {
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(void) i2c->RXDATA;
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}
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/* Clear all pending interrupts prior to starting transfer. */
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i2c->IFC = _I2C_IFC_MASK;
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/* Send start */
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obj->i2c.i2c->CMD = I2C_CMD_START;
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return 0;
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}
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/* Creates a stop condition on the I2C bus */
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int i2c_stop(i2c_t *obj)
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{
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obj->i2c.i2c->CMD = I2C_CMD_STOP;
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/* Wait for the stop to be sent */
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int timeout = I2C_TIMEOUT;
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while (!(obj->i2c.i2c->IF & I2C_IF_MSTOP) && !timeout--);
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return 0;
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}
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/* Returns number of bytes read */
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int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
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{
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int retval;
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i2c_start(obj);
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retval = i2c_byte_write(obj, (address | 1));
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if ((!retval) || (length == 0)) { //Write address with W flag (last bit 1)
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obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
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while(obj->i2c.i2c->STATE & I2C_STATE_BUSY); // Wait until the bus is done
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return (retval == 0 ? I2C_ERROR_NO_SLAVE : 0); //NACK or error when writing adress. Return 0 as 0 bytes were read
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}
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int i = 0;
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while (i < length) {
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uint8_t last = (i == length - 1);
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data[i++] = i2c_byte_read(obj, last);
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}
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if (stop) {
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i2c_stop(obj);
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}
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return length;
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}
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int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
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{
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i2c_start(obj);
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if (!i2c_byte_write(obj, (address & 0xFE))) {
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i2c_stop(obj);
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return I2C_ERROR_NO_SLAVE; //NACK or error when writing adress. Return 0 as 0 bytes were written
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}
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int i;
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for (i = 0; i < length; i++) {
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if (!i2c_byte_write(obj, data[i])) {
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i2c_stop(obj);
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return i;
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}
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}
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if (stop) {
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i2c_stop(obj);
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}
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return length;
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}
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void i2c_reset(i2c_t *obj)
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{
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i2c_enable_interrupt(obj, 0, false);
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i2c_enable(obj, false);
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/* EMLib function */
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I2C_Reset(obj->i2c.i2c);
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}
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int i2c_byte_read(i2c_t *obj, int last)
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{
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int timeout = I2C_TIMEOUT;
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/* Wait for data */
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while (!(obj->i2c.i2c->STATUS & I2C_STATUS_RXDATAV) && timeout--);
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if (timeout <= 0) {
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return 0; //TODO Is this the correct way to handle this?
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}
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char data = obj->i2c.i2c->RXDATA;
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if (last) {
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obj->i2c.i2c->CMD = I2C_CMD_NACK;
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} else {
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obj->i2c.i2c->CMD = I2C_CMD_ACK;
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}
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return data;
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}
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int i2c_byte_write(i2c_t *obj, int data)
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{
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obj->i2c.i2c->TXDATA = data;
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return block_and_wait_for_ack(obj->i2c.i2c);
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}
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/*
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* Returns 1 for ACK. 0 for NACK, timeout or error.
|
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*/
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int block_and_wait_for_ack(I2C_TypeDef *i2c)
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{
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uint32_t pending;
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uint32_t timeout = I2C_TIMEOUT;
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while (timeout > 0) {
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timeout -= 1;
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pending = i2c->IF;
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/* If some sort of fault, abort transfer. */
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if (pending & I2C_IF_ERRORS) {
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if (pending & I2C_IF_ARBLOST) {
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/* If arbitration fault, it indicates either a slave device */
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/* not responding as expected, or other master which is not */
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/* supported by this SW. */
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return 0;
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} else if (pending & I2C_IF_BUSERR) {
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/* A bus error indicates a misplaced start or stop, which should */
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/* not occur in master mode controlled by this SW. */
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return 0;
|
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}
|
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}
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||||
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if (pending & I2C_IF_NACK) {
|
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i2c->IFC = I2C_IFC_NACK;
|
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return 0; //Received NACK
|
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} else if (pending & I2C_IF_ACK) {
|
||||
i2c->IFC = I2C_IFC_ACK;
|
||||
return 1; //Got ACK
|
||||
}
|
||||
}
|
||||
return 0; //Timeout
|
||||
}
|
||||
|
||||
const PinMap *i2c_master_sda_pinmap()
|
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{
|
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return PinMap_I2C_SDA;
|
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}
|
||||
|
||||
const PinMap *i2c_master_scl_pinmap()
|
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{
|
||||
return PinMap_I2C_SCL;
|
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}
|
||||
|
||||
const PinMap *i2c_slave_sda_pinmap()
|
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{
|
||||
return PinMap_I2C_SDA;
|
||||
}
|
||||
|
||||
const PinMap *i2c_slave_scl_pinmap()
|
||||
{
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||||
return PinMap_I2C_SCL;
|
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}
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#if DEVICE_I2CSLAVE
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||||
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#define NoData 0
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#define ReadAddressed 1
|
||||
#define WriteGeneral 2
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#define WriteAddressed 3
|
||||
|
||||
|
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void i2c_slave_mode(i2c_t *obj, int enable_slave)
|
||||
{
|
||||
if(enable_slave) {
|
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/* Reference manual note: DIV must be set to 1 during slave operation */
|
||||
obj->i2c.i2c->CLKDIV = 1;
|
||||
obj->i2c.i2c->CTRL |= _I2C_CTRL_SLAVE_MASK;
|
||||
obj->i2c.i2c->CTRL |= _I2C_CTRL_AUTOACK_MASK; //Slave implementation assumes auto acking
|
||||
} else {
|
||||
obj->i2c.i2c->CTRL &= ~_I2C_CTRL_SLAVE_MASK;
|
||||
obj->i2c.i2c->CTRL &= ~_I2C_CTRL_AUTOACK_MASK; //Master implementation ACKs manually
|
||||
/* function is only called with enable_slave = false through i2c_init(..), so frequency is
|
||||
already guaranteed to be set */
|
||||
}
|
||||
}
|
||||
|
||||
int i2c_slave_receive(i2c_t *obj)
|
||||
{
|
||||
|
||||
if(obj->i2c.i2c->IF & I2C_IF_ADDR) {
|
||||
obj->i2c.i2c->IFC = I2C_IF_ADDR; //Clear interrupt
|
||||
/*0x00 is the address for general write.
|
||||
The address the master wrote is in RXDATA now
|
||||
and reading it also frees the buffer for the next
|
||||
write which can then be acked. */
|
||||
if(obj->i2c.i2c->RXDATA == 0x00) {
|
||||
return WriteGeneral; //Read the address;
|
||||
}
|
||||
|
||||
if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER) {
|
||||
return ReadAddressed;
|
||||
} else {
|
||||
return WriteAddressed;
|
||||
}
|
||||
}
|
||||
|
||||
return NoData;
|
||||
|
||||
}
|
||||
|
||||
int i2c_slave_read(i2c_t *obj, char *data, int length)
|
||||
{
|
||||
int count;
|
||||
for (count = 0; count < length; count++) {
|
||||
data[count] = i2c_byte_read(obj, 0);
|
||||
}
|
||||
|
||||
return count;
|
||||
|
||||
}
|
||||
|
||||
int i2c_slave_write(i2c_t *obj, const char *data, int length)
|
||||
{
|
||||
int count;
|
||||
for (count = 0; count < length; count++) {
|
||||
i2c_byte_write(obj, data[count]);
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
|
||||
{
|
||||
obj->i2c.i2c->SADDR = address;
|
||||
obj->i2c.i2c->SADDRMASK = 0xFE;//mask;
|
||||
}
|
||||
|
||||
#endif //DEVICE_I2CSLAVE
|
||||
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
|
||||
#include "em_dma.h"
|
||||
#include "dma_api_HAL.h"
|
||||
#include "dma_api.h"
|
||||
#include "buffer.h"
|
||||
|
||||
/** Start i2c asynchronous transfer.
|
||||
* @param obj The I2C object
|
||||
* @param tx The buffer to send
|
||||
* @param tx_length The number of words to transmit
|
||||
* @param rx The buffer to receive
|
||||
* @param rx_length The number of words to receive
|
||||
* @param address The address to be set - 7bit or 9 bit
|
||||
* @param stop If true, stop will be generated after the transfer is done
|
||||
* @param handler The I2C IRQ handler to be set
|
||||
* @param hint DMA hint usage
|
||||
*/
|
||||
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
|
||||
{
|
||||
I2C_TransferReturn_TypeDef retval;
|
||||
if(i2c_active(obj)) return;
|
||||
if((tx_length == 0) && (rx_length == 0)) return;
|
||||
// For now, we are assuming a solely interrupt-driven implementation.
|
||||
|
||||
#ifdef I2C_ROUTE_SDAPEN
|
||||
obj->i2c.i2c->ROUTE = obj->i2c.location;
|
||||
#else
|
||||
obj->i2c.i2c->ROUTELOC0 = obj->i2c.location;
|
||||
#endif
|
||||
|
||||
// Store transfer config
|
||||
obj->i2c.xfer.addr = address;
|
||||
|
||||
// Some combination of tx_length and rx_length will tell us what to do
|
||||
if((tx_length > 0) && (rx_length == 0)) {
|
||||
obj->i2c.xfer.flags = I2C_FLAG_WRITE;
|
||||
//Store buffer info
|
||||
obj->i2c.xfer.buf[0].data = (void *)tx;
|
||||
obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
|
||||
} else if ((tx_length == 0) && (rx_length > 0)) {
|
||||
obj->i2c.xfer.flags = I2C_FLAG_READ;
|
||||
//Store buffer info
|
||||
obj->i2c.xfer.buf[0].data = rx;
|
||||
obj->i2c.xfer.buf[0].len = (uint16_t) rx_length;
|
||||
} else if ((tx_length > 0) && (rx_length > 0)) {
|
||||
obj->i2c.xfer.flags = I2C_FLAG_WRITE_READ;
|
||||
//Store buffer info
|
||||
obj->i2c.xfer.buf[0].data = (void *)tx;
|
||||
obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
|
||||
obj->i2c.xfer.buf[1].data = rx;
|
||||
obj->i2c.xfer.buf[1].len = (uint16_t) rx_length;
|
||||
}
|
||||
|
||||
if(address > 255) obj->i2c.xfer.flags |= I2C_FLAG_10BIT_ADDR;
|
||||
|
||||
// Store event flags
|
||||
obj->i2c.events = event;
|
||||
|
||||
// Enable interrupt
|
||||
i2c_enable_interrupt(obj, handler, true);
|
||||
|
||||
// Kick off the transfer
|
||||
retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer));
|
||||
|
||||
MBED_ASSERT(retval == i2cTransferInProgress);
|
||||
}
|
||||
|
||||
/** The asynchronous IRQ handler
|
||||
* @param obj The I2C object which holds the transfer information
|
||||
* @return Returns event flags if a transfer termination condition was met or 0 otherwise.
|
||||
*/
|
||||
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
|
||||
{
|
||||
|
||||
// For now, we are assuming a solely interrupt-driven implementation.
|
||||
|
||||
I2C_TransferReturn_TypeDef status = I2C_Transfer(obj->i2c.i2c);
|
||||
switch(status) {
|
||||
case i2cTransferInProgress:
|
||||
// Still busy transferring, so let it.
|
||||
return 0;
|
||||
case i2cTransferDone:
|
||||
// Transfer has completed
|
||||
|
||||
// Disable interrupt
|
||||
i2c_enable_interrupt(obj, 0, false);
|
||||
|
||||
return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events;
|
||||
case i2cTransferNack:
|
||||
// A NACK has been received while an ACK was expected. This is usually because the slave did not respond to the address.
|
||||
// Disable interrupt
|
||||
i2c_enable_interrupt(obj, 0, false);
|
||||
|
||||
return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events;
|
||||
default:
|
||||
// An error situation has arisen.
|
||||
// Disable interrupt
|
||||
i2c_enable_interrupt(obj, 0, false);
|
||||
|
||||
// return error
|
||||
return I2C_EVENT_ERROR & obj->i2c.events;
|
||||
}
|
||||
}
|
||||
|
||||
/** Attempts to determine if I2C peripheral is already in use.
|
||||
* @param obj The I2C object
|
||||
* @return non-zero if the I2C module is active or zero if it is not
|
||||
*/
|
||||
uint8_t i2c_active(i2c_t *obj)
|
||||
{
|
||||
return (obj->i2c.i2c->STATE & I2C_STATE_BUSY);
|
||||
}
|
||||
|
||||
/** Abort ongoing asynchronous transaction.
|
||||
* @param obj The I2C object
|
||||
*/
|
||||
void i2c_abort_asynch(i2c_t *obj)
|
||||
{
|
||||
// Disable interrupt
|
||||
i2c_enable_interrupt(obj, 0, false);
|
||||
|
||||
// Do not deactivate I2C twice
|
||||
if (!i2c_active(obj)) return;
|
||||
|
||||
// Abort
|
||||
obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
|
||||
|
||||
// Block until free
|
||||
while(i2c_active(obj));
|
||||
}
|
||||
|
||||
#endif //DEVICE_I2C ASYNCH
|
||||
#endif //DEVICE_I2C
|
||||
Reference in New Issue
Block a user