Import Mbed OS hard-float snapshot
This commit is contained in:
Beslan
@@ -0,0 +1,417 @@
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;/**
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; *******************************************************************************
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; * @file startup_TMPM46B.s
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; * @brief CMSIS Cortex-M4 Core Device Startup File for the
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; * TOSHIBA 'TMPM46B' Device Series
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; * @version V2.0.2.4
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; * @date 2015/03/31
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
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; *
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; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
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; *******************************************************************************
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; */
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD INT0_IRQHandler ; 0: Interrupt pin 0
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DCD INT1_IRQHandler ; 1: Interrupt pin 1
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DCD INT2_IRQHandler ; 2: Interrupt pin 2
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DCD INT3_IRQHandler ; 3: Interrupt pin 3
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DCD INT4_IRQHandler ; 4: Interrupt pin 4
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DCD INT5_IRQHandler ; 5: Interrupt pin 5
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DCD INT6_IRQHandler ; 6: Interrupt pin 6
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DCD INT7_IRQHandler ; 7: Interrupt pin 7
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DCD INT8_IRQHandler ; 8: Interrupt pin 8
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DCD INT9_IRQHandler ; 9: Interrupt pin 9
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DCD INTA_IRQHandler ; 10: Interrupt pin A
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DCD INTB_IRQHandler ; 11: Interrupt pin B
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DCD INTC_IRQHandler ; 12: Interrupt pin C
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DCD INTD_IRQHandler ; 13: Interrupt pin D
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DCD INTE_IRQHandler ; 14: Interrupt pin E
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DCD INTF_IRQHandler ; 15: Interrupt pin F
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DCD INTRX0_IRQHandler ; 16: Serial0 reception interrupt
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DCD INTTX0_IRQHandler ; 17: Serial0 transmission interrupt
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DCD INTRX1_IRQHandler ; 18: Serial1 reception interrupt
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DCD INTTX1_IRQHandler ; 19: Serial1 transmission interrupt
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DCD INTRX2_IRQHandler ; 20: Serial2 reception interrupt
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DCD INTTX2_IRQHandler ; 21: Serial2 transmission interrupt
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DCD INTRX3_IRQHandler ; 22: Serial3 reception interrupt
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DCD INTTX3_IRQHandler ; 23: Serial3 transmission interrupt
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DCD INTUART0_IRQHandler ; 24: Full UART0 transmission and reception interrupt
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DCD INTUART1_IRQHandler ; 25: Full UART1 transmission and reception interrupt
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DCD INTI2C0_IRQHandler ; 26: I2C0 transmission and reception interrupt
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DCD INTI2C1_IRQHandler ; 27: I2C1 transmission and reception interrupt
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DCD INTI2C2_IRQHandler ; 28: I2C2 transmission and reception interrupt
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DCD INTSSP0_IRQHandler ; 29: SSP(SPI) Serial interface 0 interrupt
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DCD INTSSP1_IRQHandler ; 30: SSP(SPI) Serial interface 1 interrupt
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DCD INTSSP2_IRQHandler ; 31: SSP(SPI) Serial interface 2 interrupt
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DCD INTADHP_IRQHandler ; 32: High Priority AD conversion interrupt
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DCD INTADM0_IRQHandler ; 33: AD conversion monitor interrupt 0
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DCD INTADM1_IRQHandler ; 34: AD conversion monitor interrupt 1
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DCD INTAD_IRQHandler ; 35: AD conversion interrupt
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DCD INTAES_IRQHandler ; 36: AES completion interrupt
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DCD INTSHA_IRQHandler ; 37: SHA completion interrupt
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DCD INTMLA_IRQHandler ; 38: MLA completion interrupt
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DCD INTESG_IRQHandler ; 39: ESG completion interrupt
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DCD INTSNFCSEQ_IRQHandler ; 40: SNFC command sequence end interrupt
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DCD INTSNFCPRTAE_IRQHandler ; 41: SNFC page lead RAM transfer end interrupt
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DCD INTSNFCPRTCE_IRQHandler ; 42: SNFC decode data RAM transmission end interrupt
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DCD INTSNFCFAIL_IRQHandler ; 43: SNFC decode fail interrupt
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DCD 0 ; 44: Reserved1
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DCD 0 ; 45: Reserved2
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DCD 0 ; 46: Reserved3
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DCD INTMTEMG0_IRQHandler ; 47: MPT0 EMG interrupt
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DCD INTMTPTB00_IRQHandler ; 48: MPT0 compare match0/overflow,IGBT cycle interrupt
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DCD INTMTPTB01_IRQHandler ; 49: MPT0 compare match1/overflow,IGBT cycle interrupt
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DCD INTMTCAP00_IRQHandler ; 50: MPT0 input capture0 interrupt
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DCD INTMTCAP01_IRQHandler ; 51: MPT0 input capture1 interrupt
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DCD INTMTEMG1_IRQHandler ; 52: MPT1 EMG interrupt
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DCD INTMTPTB10_IRQHandler ; 53: MPT1 compare match0/overflow,IGBT cycle interrupt
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DCD INTMTPTB11_IRQHandler ; 54: MPT1 compare match1/overflow,IGBT cycle interrupt
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DCD INTMTCAP10_IRQHandler ; 55: MPT1 input capture0 interrupt
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DCD INTMTCAP11_IRQHandler ; 56: MPT1 input capture1 interrupt
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DCD INTMTEMG2_IRQHandler ; 57: MPT2 EMG interrupt
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DCD INTMTPTB20_IRQHandler ; 58: MPT2 compare match0/overflow,IGBT cycle interrupt
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DCD INTMTTTB21_IRQHandler ; 59: MPT2 compare match1/overflow,IGBT cycle interrupt
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DCD INTMTCAP20_IRQHandler ; 60: MPT2 input capture0 interrupt
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DCD INTMTCAP21_IRQHandler ; 61: MPT2 input capture1 interrupt
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DCD INTMTEMG3_IRQHandler ; 62: MPT3 EMG interrupt
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DCD INTMTPTB30_IRQHandler ; 63: MPT3 compare match0/overflow,IGBT cycle interrupt
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DCD INTMTTTB31_IRQHandler ; 64: MPT3 compare match1/overflow,IGBT cycle interrupt
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DCD INTMTCAP30_IRQHandler ; 65: MPT3 input capture0 interrupt
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DCD INTMTCAP31_IRQHandler ; 66: MPT3 input capture1 interrupt
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DCD INTTB0_IRQHandler ; 67: TMRB0 compare match detection interrupt
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DCD INTCAP00_IRQHandler ; 68: TMRB0 input capture 0 interrupt
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DCD INTCAP01_IRQHandler ; 69: TMRB0 input capture 1 interrupt
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DCD INTTB1_IRQHandler ; 70: TMRB1 compare match detection interrupt
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DCD INTCAP10_IRQHandler ; 71: TMRB1 input capture 0 interrupt
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DCD INTCAP11_IRQHandler ; 72: TMRB1 input capture 1 interrupt
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DCD INTTB2_IRQHandler ; 73: TMRB2 compare match detection interrupt
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DCD INTCAP20_IRQHandler ; 74: TMRB2 input capture 0 interrupt
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DCD INTCAP21_IRQHandler ; 75: TMRB2 input capture 1 interrupt
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DCD INTTB3_IRQHandler ; 76: TMRB3 compare match detection interrupt
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DCD INTCAP30_IRQHandler ; 77: TMRB3 input capture 0 interrupt
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DCD INTCAP31_IRQHandler ; 78: TMRB3 input capture 1 interrupt
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DCD INTTB4_IRQHandler ; 79: TMRB4 compare match detection interrupt
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DCD INTCAP40_IRQHandler ; 80: TMRB4 input capture 0 interrupt
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DCD INTCAP41_IRQHandler ; 81: TMRB4 input capture 1 interrupt
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DCD INTTB5_IRQHandler ; 82: TMRB5 compare match detection interrupt
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DCD INTCAP50_IRQHandler ; 83: TMRB5 input capture 0 interrupt
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DCD INTCAP51_IRQHandler ; 84: TMRB5 input capture 1 interrupt
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DCD INTTB6_IRQHandler ; 85: TMRB6 compare match detection interrupt
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DCD INTCAP60_IRQHandler ; 86: TMRB6 input capture 0 interrupt
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DCD INTCAP61_IRQHandler ; 87: TMRB6 input capture 1 interrupt
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DCD INTTB7_IRQHandler ; 88: TMRB7 compare match detection interrupt
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DCD INTCAP70_IRQHandler ; 89: TMRB7 input capture 0 interrupt
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DCD INTCAP71_IRQHandler ; 90: TMRB7 input capture 1 interrupt
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DCD INTRTC_IRQHandler ; 91: Real time clock interrupt
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DCD INTDMAA_IRQHandler ; 92: DMAC unitA transmission completion interrupt(ch4-31)
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DCD INTDMAB_IRQHandler ; 93: DMAC unitB transmission completion interrupt(ch24-31)
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DCD INTDMAC_IRQHandler ; 94: DMAC unitC transmission completion interrupt(ch12-31)
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DCD INTDMACTC8_IRQHandler ; 95: DMAC unitC transmission completion interrupt(ch8)
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DCD INTDMACTC9_IRQHandler ; 96: DMAC unitC transmission completion interrupt(ch9)
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DCD INTDMACTC10_IRQHandler ; 97: DMAC unitC transmission completion interrupt(ch10)
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DCD INTDMACTC11_IRQHandler ; 98: DMAC unitC transmission completion interrupt(ch11)
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DCD INTDMAAERR_IRQHandler ; 99: DMAC transmission error interrupt(unitA)
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DCD INTDMABERR_IRQHandler ; 100: DMAC transmission error interrupt(unitB)
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DCD INTDMACERR_IRQHandler ; 101: DMAC transmission error interrupt(unitC)
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DCD INTFLRDY_IRQHandler ; 102: Flash Ready interrupt
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT INT0_IRQHandler [WEAK]
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EXPORT INT1_IRQHandler [WEAK]
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EXPORT INT2_IRQHandler [WEAK]
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EXPORT INT3_IRQHandler [WEAK]
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EXPORT INT4_IRQHandler [WEAK]
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EXPORT INT5_IRQHandler [WEAK]
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EXPORT INT6_IRQHandler [WEAK]
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EXPORT INT7_IRQHandler [WEAK]
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EXPORT INT8_IRQHandler [WEAK]
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EXPORT INT9_IRQHandler [WEAK]
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EXPORT INTA_IRQHandler [WEAK]
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EXPORT INTB_IRQHandler [WEAK]
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EXPORT INTC_IRQHandler [WEAK]
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EXPORT INTD_IRQHandler [WEAK]
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EXPORT INTE_IRQHandler [WEAK]
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EXPORT INTF_IRQHandler [WEAK]
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EXPORT INTRX0_IRQHandler [WEAK]
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EXPORT INTTX0_IRQHandler [WEAK]
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EXPORT INTRX1_IRQHandler [WEAK]
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EXPORT INTTX1_IRQHandler [WEAK]
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EXPORT INTRX2_IRQHandler [WEAK]
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EXPORT INTTX2_IRQHandler [WEAK]
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EXPORT INTRX3_IRQHandler [WEAK]
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EXPORT INTTX3_IRQHandler [WEAK]
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EXPORT INTUART0_IRQHandler [WEAK]
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EXPORT INTUART1_IRQHandler [WEAK]
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EXPORT INTI2C0_IRQHandler [WEAK]
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EXPORT INTI2C1_IRQHandler [WEAK]
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EXPORT INTI2C2_IRQHandler [WEAK]
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EXPORT INTSSP0_IRQHandler [WEAK]
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EXPORT INTSSP1_IRQHandler [WEAK]
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EXPORT INTSSP2_IRQHandler [WEAK]
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EXPORT INTADHP_IRQHandler [WEAK]
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EXPORT INTADM0_IRQHandler [WEAK]
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EXPORT INTADM1_IRQHandler [WEAK]
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EXPORT INTAD_IRQHandler [WEAK]
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EXPORT INTAES_IRQHandler [WEAK]
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EXPORT INTSHA_IRQHandler [WEAK]
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EXPORT INTMLA_IRQHandler [WEAK]
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EXPORT INTESG_IRQHandler [WEAK]
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EXPORT INTSNFCSEQ_IRQHandler [WEAK]
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EXPORT INTSNFCPRTAE_IRQHandler [WEAK]
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EXPORT INTSNFCPRTCE_IRQHandler [WEAK]
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EXPORT INTSNFCFAIL_IRQHandler [WEAK]
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EXPORT INTMTEMG0_IRQHandler [WEAK]
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EXPORT INTMTPTB00_IRQHandler [WEAK]
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EXPORT INTMTPTB01_IRQHandler [WEAK]
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EXPORT INTMTCAP00_IRQHandler [WEAK]
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EXPORT INTMTCAP01_IRQHandler [WEAK]
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EXPORT INTMTEMG1_IRQHandler [WEAK]
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EXPORT INTMTPTB10_IRQHandler [WEAK]
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EXPORT INTMTPTB11_IRQHandler [WEAK]
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EXPORT INTMTCAP10_IRQHandler [WEAK]
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EXPORT INTMTCAP11_IRQHandler [WEAK]
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EXPORT INTMTEMG2_IRQHandler [WEAK]
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EXPORT INTMTPTB20_IRQHandler [WEAK]
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EXPORT INTMTTTB21_IRQHandler [WEAK]
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EXPORT INTMTCAP20_IRQHandler [WEAK]
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EXPORT INTMTCAP21_IRQHandler [WEAK]
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EXPORT INTMTEMG3_IRQHandler [WEAK]
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EXPORT INTMTPTB30_IRQHandler [WEAK]
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EXPORT INTMTTTB31_IRQHandler [WEAK]
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EXPORT INTMTCAP30_IRQHandler [WEAK]
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EXPORT INTMTCAP31_IRQHandler [WEAK]
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EXPORT INTTB0_IRQHandler [WEAK]
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EXPORT INTCAP00_IRQHandler [WEAK]
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EXPORT INTCAP01_IRQHandler [WEAK]
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EXPORT INTTB1_IRQHandler [WEAK]
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EXPORT INTCAP10_IRQHandler [WEAK]
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EXPORT INTCAP11_IRQHandler [WEAK]
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EXPORT INTTB2_IRQHandler [WEAK]
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EXPORT INTCAP20_IRQHandler [WEAK]
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EXPORT INTCAP21_IRQHandler [WEAK]
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EXPORT INTTB3_IRQHandler [WEAK]
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EXPORT INTCAP30_IRQHandler [WEAK]
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EXPORT INTCAP31_IRQHandler [WEAK]
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EXPORT INTTB4_IRQHandler [WEAK]
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EXPORT INTCAP40_IRQHandler [WEAK]
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EXPORT INTCAP41_IRQHandler [WEAK]
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EXPORT INTTB5_IRQHandler [WEAK]
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EXPORT INTCAP50_IRQHandler [WEAK]
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EXPORT INTCAP51_IRQHandler [WEAK]
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EXPORT INTTB6_IRQHandler [WEAK]
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EXPORT INTCAP60_IRQHandler [WEAK]
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EXPORT INTCAP61_IRQHandler [WEAK]
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EXPORT INTTB7_IRQHandler [WEAK]
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EXPORT INTCAP70_IRQHandler [WEAK]
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EXPORT INTCAP71_IRQHandler [WEAK]
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EXPORT INTRTC_IRQHandler [WEAK]
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EXPORT INTDMAA_IRQHandler [WEAK]
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EXPORT INTDMAB_IRQHandler [WEAK]
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EXPORT INTDMAC_IRQHandler [WEAK]
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EXPORT INTDMACTC8_IRQHandler [WEAK]
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EXPORT INTDMACTC9_IRQHandler [WEAK]
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EXPORT INTDMACTC10_IRQHandler [WEAK]
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EXPORT INTDMACTC11_IRQHandler [WEAK]
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EXPORT INTDMAAERR_IRQHandler [WEAK]
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EXPORT INTDMABERR_IRQHandler [WEAK]
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EXPORT INTDMACERR_IRQHandler [WEAK]
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EXPORT INTFLRDY_IRQHandler [WEAK]
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INT0_IRQHandler
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INT1_IRQHandler
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INT2_IRQHandler
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INT3_IRQHandler
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INT4_IRQHandler
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INT5_IRQHandler
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INT6_IRQHandler
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INT7_IRQHandler
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INT8_IRQHandler
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INT9_IRQHandler
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INTA_IRQHandler
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INTB_IRQHandler
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INTC_IRQHandler
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INTD_IRQHandler
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INTE_IRQHandler
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INTF_IRQHandler
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INTRX0_IRQHandler
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INTTX0_IRQHandler
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INTRX1_IRQHandler
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INTTX1_IRQHandler
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INTRX2_IRQHandler
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INTTX2_IRQHandler
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INTRX3_IRQHandler
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INTTX3_IRQHandler
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INTUART0_IRQHandler
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INTUART1_IRQHandler
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INTI2C0_IRQHandler
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INTI2C1_IRQHandler
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INTI2C2_IRQHandler
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INTSSP0_IRQHandler
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INTSSP1_IRQHandler
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INTSSP2_IRQHandler
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INTADHP_IRQHandler
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INTADM0_IRQHandler
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INTADM1_IRQHandler
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INTAD_IRQHandler
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INTAES_IRQHandler
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INTSHA_IRQHandler
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INTMLA_IRQHandler
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INTESG_IRQHandler
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INTSNFCSEQ_IRQHandler
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INTSNFCPRTAE_IRQHandler
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INTSNFCPRTCE_IRQHandler
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INTSNFCFAIL_IRQHandler
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INTMTEMG0_IRQHandler
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INTMTPTB00_IRQHandler
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INTMTPTB01_IRQHandler
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INTMTCAP00_IRQHandler
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INTMTCAP01_IRQHandler
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INTMTEMG1_IRQHandler
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INTMTPTB10_IRQHandler
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INTMTPTB11_IRQHandler
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INTMTCAP10_IRQHandler
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INTMTCAP11_IRQHandler
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INTMTEMG2_IRQHandler
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INTMTPTB20_IRQHandler
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INTMTTTB21_IRQHandler
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INTMTCAP20_IRQHandler
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INTMTCAP21_IRQHandler
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INTMTEMG3_IRQHandler
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INTMTPTB30_IRQHandler
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INTMTTTB31_IRQHandler
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INTMTCAP30_IRQHandler
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INTMTCAP31_IRQHandler
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INTTB0_IRQHandler
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INTCAP00_IRQHandler
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INTCAP01_IRQHandler
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INTTB1_IRQHandler
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INTCAP10_IRQHandler
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INTCAP11_IRQHandler
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INTTB2_IRQHandler
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INTCAP20_IRQHandler
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INTCAP21_IRQHandler
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INTTB3_IRQHandler
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INTCAP30_IRQHandler
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INTCAP31_IRQHandler
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INTTB4_IRQHandler
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INTCAP40_IRQHandler
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INTCAP41_IRQHandler
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INTTB5_IRQHandler
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INTCAP50_IRQHandler
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INTCAP51_IRQHandler
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INTTB6_IRQHandler
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INTCAP60_IRQHandler
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INTCAP61_IRQHandler
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INTTB7_IRQHandler
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INTCAP70_IRQHandler
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INTCAP71_IRQHandler
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INTRTC_IRQHandler
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INTDMAA_IRQHandler
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INTDMAB_IRQHandler
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INTDMAC_IRQHandler
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INTDMACTC8_IRQHandler
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INTDMACTC9_IRQHandler
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INTDMACTC10_IRQHandler
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INTDMACTC11_IRQHandler
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INTDMAAERR_IRQHandler
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INTDMABERR_IRQHandler
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INTDMACERR_IRQHandler
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INTFLRDY_IRQHandler
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B .
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ENDP
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ALIGN
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END
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@@ -0,0 +1,50 @@
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#! armcc -E -I. --cpu Cortex-M4
|
||||
;; TMPM46BF10 scatter file
|
||||
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||||
;; Vector table starts at 0
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||||
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
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||||
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
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||||
;; Initial PC == &__main (with LSB set to indicate Thumb)
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||||
;; These two values are provided by the library
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;; Other vectors must be provided by the user
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;; Code starts after the last possible vector
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;; Data starts at 0x20000000
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||||
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
|
||||
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
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||||
|
||||
;; Compatible with ISSM model
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||||
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||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x00000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 0x100000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
#define MBED_BOOT_STACK_SIZE 0x400
|
||||
#endif
|
||||
|
||||
#define Stack_Size MBED_BOOT_STACK_SIZE
|
||||
|
||||
; TMPM46B: 1024 KB FLASH (0x100000) + 512 KB SRAM (0x80000)
|
||||
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
|
||||
{
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE
|
||||
{
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_IRAM1 0x200001E0 (0x80000 - 0x1E0 - Stack_Size)
|
||||
{
|
||||
tmpm46b_fc.o(+RO)
|
||||
.ANY (+RW, +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_STACK (0x20000000+0x80000) EMPTY -Stack_Size { ; stack
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user