Import Mbed OS hard-float snapshot
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98
targets/TARGET_TOSHIBA/TARGET_TMPM46B/trng_api.c
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98
targets/TARGET_TOSHIBA/TARGET_TMPM46B/trng_api.c
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/* mbed Microcontroller Library
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* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "mbed_error.h"
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#include "tmpm46b_esg.h"
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#include "trng_api.h"
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static Result ESG_Config(void)
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{
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Result ret = ERROR;
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uint16_t Fintming = 560U;
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// Confirm the ESG core stops
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if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
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// Confirm no interrupt generation
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if (ESG_GetIntStatus() == DISABLE) {
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// Set the latch timing & output timing
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if ((ESG_SetLatchTiming(ESG_LATCH_TIMING_1) == SUCCESS) &&
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(ESG_SetFintiming(Fintming) == SUCCESS)) {
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ret = SUCCESS;
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}
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}
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}
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return ret;
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}
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void trng_init(trng_t *obj)
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{
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// Enable clock supply
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CG_SetFcPeriphB(CG_FC_PERIPH_ESG, ENABLE);
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// Initialise ESG core & Start up the ESG core
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if ((ESG_Config() == SUCCESS) && (ESG_Startup() == SUCCESS)) {
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obj->trng_init = true;
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} else {
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error("TRNG is not Initialised");
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obj->trng_init = false;
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}
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}
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void trng_free(trng_t *obj)
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{
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ESG_IPReset();
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// Disable clock supply
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CG_SetFcPeriphB(CG_FC_PERIPH_ESG, DISABLE);
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obj->trng_init = false;
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}
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int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
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{
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volatile uint8_t random[64] = {0};
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uint8_t i;
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Result ret = ERROR;
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*output_length = 0;
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if (!obj->trng_init) {
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error("TRNG is not Initialised");
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return FAIL; // fail i.e. -1
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}
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while (ESG_GetIntStatus() == DISABLE) {
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// Wait for ESG core for generating an interrupt
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}
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// Interrupt clearing
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ret = ESG_ClrInt();
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if (ret == ERROR) {
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return FAIL; // fail i.e. -1
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}
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// Get the calculation result
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ESG_GetResult((uint32_t*)random); //512-bit entropy
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for (i = 0; (i < 64) && (i < length); i++) {
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*output++ = random[i];
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// clear the buffer
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random[i] = 0;
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}
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*output_length = i;
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//clear and restart the ESG core
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ESG_IPReset();
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ret |= ESG_Startup();
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if (ret == ERROR) {
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return FAIL; // fail i.e. -1
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}
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return ret;
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}
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