114 lines
6.0 KiB
C
114 lines
6.0 KiB
C
/**************************************************************************//**
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* @file hdiv_reg.h
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* @version V1.00
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* @brief HDIV register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __HDIV_REG_H__
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#define __HDIV_REG_H__
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/** @addtogroup REGISTER Control Register
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@{
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*/
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/*---------------------- Hardware Divider --------------------------------*/
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/**
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@addtogroup HDIV Hardware Divider(HDIV)
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Memory Mapped Structure for HDIV Controller
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@{ */
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typedef struct
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{
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/**
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* @var HDIV_T::DIVIDEND
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* Offset: 0x00 Dividend Source Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |DIVIDEND |Dividend Source
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* | | |This register is given the dividend of divider before calculation starting.
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* @var HDIV_T::DIVISOR
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* Offset: 0x04 Divisor Source Resister
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[15:0] |DIVISOR |Divisor Source
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* | | |This register is given the divisor of divider before calculation starts.
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* | | |Note: When this register is written, hardware divider will start calculate.
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* @var HDIV_T::DIVQUO
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* Offset: 0x08 Quotient Result Resister
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |QUOTIENT |Quotient Result
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* | | |This register holds the quotient result of divider after calculation complete.
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* @var HDIV_T::DIVREM
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* Offset: 0x0C Remainder Result Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |REMAINDER |Remainder Result
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* | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.
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* | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
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* | | |This register holds the remainder result of divider after calculation complete.
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* @var HDIV_T::DIVSTS
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* Offset: 0x10 Divider Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |FINISH |Division Finish Flag
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* | | |0 = Under Calculation.
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* | | |1 = Calculation finished.
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* | | |The flag will become low when the divider is in calculation.
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* | | |The flag will go back to high once the calculation finished.
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* |[1] |DIV0 |Divisor Zero Warning
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* | | |0 = The divisor is not 0.
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* | | |1 = The divisor is 0.
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* | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written
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* | | |This register is read only.
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*/
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__IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */
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__IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */
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__IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */
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__IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */
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__I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */
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} HDIV_T;
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/**
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@addtogroup HDIV_CONST HDIV Bit Field Definition
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Constant Definitions for HDIV Controller
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@{ */
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#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
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#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
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#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
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#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
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#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */
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#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */
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#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */
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#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */
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#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */
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#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */
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#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */
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#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */
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/**@}*/ /* HDIV_CONST */
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/**@}*/ /* end of HDIV register group */
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/**@}*/ /* end of REGISTER group */
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#endif /* __HDIV_REG_H__ */
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