220 lines
8.8 KiB
C
220 lines
8.8 KiB
C
/**************************************************************************//**
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* @file pdma.h
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* @version V1.00
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* $Revision: 9 $
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* $Date: 15/06/10 4:52p $
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* @brief Nano100 series PDMA driver header file
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*
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* @note
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* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PDMA_H__
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#define __PDMA_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_PDMA_Driver PDMA Driver
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@{
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*/
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/** @addtogroup NANO100_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* Data Width Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define PDMA_WIDTH_8 0x00080000UL /*!<DMA Transfer Width 8-bit */
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#define PDMA_WIDTH_16 0x00100000UL /*!<DMA Transfer Width 16-bit */
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#define PDMA_WIDTH_32 0x00000000UL /*!<DMA Transfer Width 32-bit */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Address Attribute Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment */
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#define PDMA_SAR_FIX 0x00000020UL /*!<DMA SAR fix address */
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#define PDMA_SAR_WRA 0x00000030UL /*!<DMA SAR wrap around */
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#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment */
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#define PDMA_DAR_FIX 0x00000080UL /*!<DMA DAR fix address */
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#define PDMA_DAR_WRA 0x000000C0UL /*!<DMA DAR wrap around */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Peripheral Transfer Mode Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define PDMA_SPI0_TX 0x00000000UL /*!<DMA Connect to SPI0 TX */
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#define PDMA_SPI1_TX 0x00000001UL /*!<DMA Connect to SPI1 TX */
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#define PDMA_UART0_TX 0x00000002UL /*!<DMA Connect to UART0 TX */
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#define PDMA_UART1_TX 0x00000003UL /*!<DMA Connect to UART1 TX */
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#define PDMA_USB_TX 0x00000004UL /*!<DMA Connect to USB TX */
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#define PDMA_I2S_TX 0x00000005UL /*!<DMA Connect to I2S TX */
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#define PDMA_DAC0_TX 0x00000006UL /*!<DMA Connect to DAC0 TX */
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#define PDMA_DAC1_TX 0x00000007UL /*!<DMA Connect to DAC1 TX */
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#define PDMA_SPI2_TX 0x00000008UL /*!<DMA Connect to SPI2 TX */
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#define PDMA_TMR0 0x00000009UL /*!<DMA Connect to TMR0 */
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#define PDMA_TMR1 0x0000000AUL /*!<DMA Connect to TMR1 */
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#define PDMA_TMR2 0x0000000BUL /*!<DMA Connect to TMR2 */
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#define PDMA_TMR3 0x0000000CUL /*!<DMA Connect to TMR3 */
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#define PDMA_SPI0_RX 0x00000010UL /*!<DMA Connect to SPI0 RX */
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#define PDMA_SPI1_RX 0x00000011UL /*!<DMA Connect to SPI1 RX */
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#define PDMA_UART0_RX 0x00000012UL /*!<DMA Connect to UART0 RX */
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#define PDMA_UART1_RX 0x00000013UL /*!<DMA Connect to UART1 RX */
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#define PDMA_USB_RX 0x00000014UL /*!<DMA Connect to USB RX */
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#define PDMA_I2S_RX 0x00000015UL /*!<DMA Connect to I2S RX */
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#define PDMA_ADC 0x00000016UL /*!<DMA Connect to I2S1 RX */
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#define PDMA_SPI2_RX 0x00000018UL /*!<DMA Connect to SPI2 RX */
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#define PDMA_PWM0_CH0 0x00000019UL /*!<DMA Connect to PWM0 CH0 */
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#define PDMA_PWM0_CH2 0x0000001AUL /*!<DMA Connect to PWM0 CH2 */
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#define PDMA_PWM1_CH0 0x0000001BUL /*!<DMA Connect to PWM1 CH0 */
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#define PDMA_PWM1_CH2 0x0000001CUL /*!<DMA Connect to PWM1 CH2 */
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#define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory */
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/*@}*/ /* end of group NANO100_PDMA_EXPORTED_CONSTANTS */
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/** @addtogroup NANO100_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
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@{
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*/
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/**
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* @brief Get PDMA Interrupt Status
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*
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* @param[in] None
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*
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* @return None
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*
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* @details This macro gets the interrupt status.
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* \hideinitializer
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*/
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#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMAGCR->GCRISR))
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/**
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* @brief Get PDMA Channel Interrupt Status
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*
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* @param[in] u32Ch Selected DMA channel
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*
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* @return Interrupt Status
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*
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* @details This macro gets the channel interrupt status.
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* \hideinitializer
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*/
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#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))))
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/**
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* @brief Clear PDMA Channel Interrupt Flag
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*
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* @param[in] u32Ch Selected DMA channel
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* @param[in] u32Mask Interrupt Mask
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*
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* @return None
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*
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* @details This macro clear the channel interrupt flag.
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* \hideinitializer
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*/
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#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask))
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/**
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* @brief Check Channel Status
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*
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* @param[in] u32Ch The selected channel
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*
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* @return 0 = idle
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* @return 1 = busy
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*
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* @details Check the selected channel is busy or not.
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* \hideinitializer
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*/
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#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CSR +(uint32_t)((u32Ch-1)*0x100)))&PDMA_CSR_TRIG_EN_Msk)? 1 : 0)
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/**
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* @brief Set Source Address
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Addr The selected address
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*
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* @return None
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*
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* @details This macro set the selected channel source address.
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* \hideinitializer
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*/
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#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
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/**
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* @brief Set Destination Address
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Addr The selected address
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*
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* @return None
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*
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* @details This macro set the selected channel destination address.
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* \hideinitializer
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*/
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#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
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/**
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* @brief Set Transfer Count
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*
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* @param[in] u32Ch The selected channel
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* @param[in] u32Count Transfer Count
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*
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* @return None
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*
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* @details This macro set the selected channel transfer count.
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* \hideinitializer
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*/
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#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) \
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do{\
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if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \
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*((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 2); \
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else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \
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*((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = (u32Count); \
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else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \
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*((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 1); \
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}while(0)
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/**
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* @brief Stop the channel
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*
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* @param[in] u32Ch The selected channel
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*
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* @return None
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*
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* @details This macro stop the selected channel.
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* \hideinitializer
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*/
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#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk)
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void PDMA_Open(uint32_t u32Mask);
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void PDMA_Close(void);
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void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
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void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
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void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
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void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
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void PDMA_Trigger(uint32_t u32Ch);
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void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
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void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
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/*@}*/ /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_PDMA_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__PDMA_H__
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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