176 lines
11 KiB
C
176 lines
11 KiB
C
/**************************************************************************//**
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* @file ebi_reg.h
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* @version V1.00
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* @brief EBI register definition header file
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*
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef __EBI_REG_H__
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#define __EBI_REG_H__
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/** @addtogroup REGISTER Control Register
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@{
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*/
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/*---------------------- External Bus Interface Controller -------------------------*/
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/**
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@addtogroup EBI External Bus Interface Controller(EBI)
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Memory Mapped Structure for EBI Controller
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@{ */
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typedef struct
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{
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/**
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* @var EBI_T::CTL0
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* Offset: 0x00 External Bus Interface Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |EN |EBI Enable Bit
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* | | |This bit is the functional enable bit for EBI.
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* | | |0 = EBI function Disabled.
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* | | |1 = EBI function Enabled.
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* |[1] |DW16 |EBI Data Width 16-bit Select
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* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
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* | | |0 = EBI data width is 8-bit.
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* | | |1 = EBI data width is 16-bit.
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* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
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* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
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* | | |0 = Chip select pin (EBI_nCS) is active low.
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* | | |1 = Chip select pin (EBI_nCS) is active high.
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* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
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* | | |0 = Address/Data Bus Separating Mode Disabled.
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* | | |1 = Address/Data Bus Separating Mode Enabled.
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* |[4] |CACCESS |Continuous Data Access Mode
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* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
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* | | |0 = Continuous data access mode Disabled.
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* | | |1 = Continuous data access mode Enabled.
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* |[10:8] |MCLKDIV |External Output Clock Divider
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* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
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* | | |000 = HCLK/1.
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* | | |001 = HCLK/2.
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* | | |010 = HCLK/4.
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* | | |011 = HCLK/8.
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* | | |100 = HCLK/16.
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* | | |101 = HCLK/32.
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* | | |110 = HCLK/64.
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* | | |111 = HCLK/128.
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* |[18:16] |TALE |Extend Time of ALE
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* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
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* | | |tALE = (TALE+1)*EBI_MCLK.
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* | | |Note: This field only available in EBI_CTL0 register
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* @var EBI_T::TCTL0
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* Offset: 0x04 External Bus Interface Timing Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[7:3] |TACC |EBI Data Access Time
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* | | |TACC define data access time (tACC).
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* | | |tACC = (TACC+1) * EBI_MCLK.
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* |[10:8] |TAHD |EBI Data Access Hold Time
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* | | |TAHD define data access hold time (tAHD).
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* | | |tAHD = (TAHD+1) * EBI_MCLK.
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* |[15:12] |W2X |Idle Cycle After Write
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* | | |This field defines the number of W2X idle cycle.
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* | | |W2X idle cycle = (W2X * EBI_MCLK).
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* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
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* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
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* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
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* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
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* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
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* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
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* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
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* |[27:24] |R2R |Idle Cycle Between Read-to-read
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* | | |This field defines the number of R2R idle cycle.
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* | | |R2R idle cycle = (R2R * EBI_MCLK).
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* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
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*/
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__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
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__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
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__I uint32_t RESERVE0[2];
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__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
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__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
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__I uint32_t RESERVE1[2];
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__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
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__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
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} EBI_T;
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/**
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@addtogroup EBI_CONST EBI Bit Field Definition
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Constant Definitions for EBI Controller
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@{ */
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#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
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#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
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#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
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#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
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#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
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#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
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#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
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#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
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#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
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#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
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#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
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#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
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#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
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#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
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#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
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#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
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#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
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#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
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#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
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#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
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#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
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#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
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#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
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#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
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#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
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#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
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/**@}*/ /* EBI_CONST */
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/**@}*/ /* end of EBI register group */
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/**@}*/ /* end of REGISTER group */
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#endif /* __EBI_REG_H__ */
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