134 lines
7.5 KiB
C
134 lines
7.5 KiB
C
/**************************************************************************//**
|
|
* @file hdiv_reg.h
|
|
* @version V1.00
|
|
* @brief HDIV register definition header file
|
|
*
|
|
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without modification,
|
|
* are permitted provided that the following conditions are met:
|
|
* 1. Redistributions of source code must retain the above copyright notice,
|
|
* this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
* this list of conditions and the following disclaimer in the documentation
|
|
* and/or other materials provided with the distribution.
|
|
* 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
|
|
* may be used to endorse or promote products derived from this software
|
|
* without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*****************************************************************************/
|
|
#ifndef __HDIV_REG_H__
|
|
#define __HDIV_REG_H__
|
|
|
|
/** @addtogroup REGISTER Control Register
|
|
|
|
@{
|
|
|
|
*/
|
|
|
|
/*---------------------- Hardware Divider --------------------------------*/
|
|
/**
|
|
@addtogroup HDIV Hardware Divider(HDIV)
|
|
Memory Mapped Structure for HDIV Controller
|
|
@{ */
|
|
|
|
typedef struct
|
|
{
|
|
|
|
|
|
/**
|
|
* @var HDIV_T::DIVIDEND
|
|
* Offset: 0x00 Dividend Source Register
|
|
* ---------------------------------------------------------------------------------------------------
|
|
* |Bits |Field |Descriptions
|
|
* | :----: | :----: | :---- |
|
|
* |[31:0] |DIVIDEND |Dividend Source
|
|
* | | |This register is given the dividend of divider before calculation starting.
|
|
* @var HDIV_T::DIVISOR
|
|
* Offset: 0x04 Divisor Source Resister
|
|
* ---------------------------------------------------------------------------------------------------
|
|
* |Bits |Field |Descriptions
|
|
* | :----: | :----: | :---- |
|
|
* |[15:0] |DIVISOR |Divisor Source
|
|
* | | |This register is given the divisor of divider before calculation starts.
|
|
* | | |Note: When this register is written, hardware divider will start calculate.
|
|
* @var HDIV_T::DIVQUO
|
|
* Offset: 0x08 Quotient Result Resister
|
|
* ---------------------------------------------------------------------------------------------------
|
|
* |Bits |Field |Descriptions
|
|
* | :----: | :----: | :---- |
|
|
* |[31:0] |QUOTIENT |Quotient Result
|
|
* | | |This register holds the quotient result of divider after calculation complete.
|
|
* @var HDIV_T::DIVREM
|
|
* Offset: 0x0C Remainder Result Register
|
|
* ---------------------------------------------------------------------------------------------------
|
|
* |Bits |Field |Descriptions
|
|
* | :----: | :----: | :---- |
|
|
* |[31:0] |REMAINDER |Remainder Result
|
|
* | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.
|
|
* | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
|
|
* | | |This register holds the remainder result of divider after calculation complete.
|
|
* @var HDIV_T::DIVSTS
|
|
* Offset: 0x10 Divider Status Register
|
|
* ---------------------------------------------------------------------------------------------------
|
|
* |Bits |Field |Descriptions
|
|
* | :----: | :----: | :---- |
|
|
* |[0] |FINISH |Division Finish Flag
|
|
* | | |0 = Under Calculation.
|
|
* | | |1 = Calculation finished.
|
|
* | | |The flag will become low when the divider is in calculation.
|
|
* | | |The flag will go back to high once the calculation finished.
|
|
* |[1] |DIV0 |Divisor Zero Warning
|
|
* | | |0 = The divisor is not 0.
|
|
* | | |1 = The divisor is 0.
|
|
* | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written
|
|
* | | |This register is read only.
|
|
*/
|
|
__IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */
|
|
__IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */
|
|
__IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */
|
|
__IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */
|
|
__I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */
|
|
|
|
} HDIV_T;
|
|
|
|
/**
|
|
@addtogroup HDIV_CONST HDIV Bit Field Definition
|
|
Constant Definitions for HDIV Controller
|
|
@{ */
|
|
|
|
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
|
|
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
|
|
|
|
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
|
|
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
|
|
|
|
#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */
|
|
#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */
|
|
|
|
#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */
|
|
#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */
|
|
|
|
#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */
|
|
#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */
|
|
|
|
#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */
|
|
#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */
|
|
|
|
/**@}*/ /* HDIV_CONST */
|
|
/**@}*/ /* end of HDIV register group */
|
|
/**@}*/ /* end of REGISTER group */
|
|
|
|
|
|
#endif /* __HDIV_REG_H__ */
|