543 lines
20 KiB
C
543 lines
20 KiB
C
/**************************************************************************//**
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* @file PWM.c
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* @version V1.00
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* $Revision: 14 $
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* $Date: 14/09/04 11:58a $
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* @brief NANO100 series PWM driver source file
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*
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* @note
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* Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "Nano100Series.h"
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/** @addtogroup NANO100_Device_Driver NANO100 Device Driver
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@{
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*/
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/** @addtogroup NANO100_PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup NANO100_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Frequency Target generator frequency
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
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* @return Nearest frequency clock in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
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* existing frequency of other channel.
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*/
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uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle)
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{
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return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
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}
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/**
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* @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Frequency Target generator frequency
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
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* @return Nearest frequency clock in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
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* existing frequency of other channel.
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*/
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uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle,
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uint32_t u32Frequency2)
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{
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uint32_t i;
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uint32_t u32ClkSrc;
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uint32_t u32PWM_Clock = SystemCoreClock;
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uint8_t u8Divider = 1, u8Prescale = 0xFF;
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uint16_t u16CNR = 0xFFFF;
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if(pwm == PWM0)
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u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2));
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else
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u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2));
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switch (u32ClkSrc) {
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case 0:
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u32PWM_Clock = __HXT;
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break;
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case 1:
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u32PWM_Clock = __LXT;
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break;
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case 2:
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u32PWM_Clock = SystemCoreClock;
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break;
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case 3:
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u32PWM_Clock = __HIRC12M;
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break;
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}
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for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
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// Note: Support frequency < 1
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i = (uint64_t) u32PWM_Clock * u32Frequency2 / u32Frequency / u8Divider;
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// If target value is larger than CNR * prescale, need to use a larger divider
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if(i > (0x10000 * 0x100))
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continue;
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// CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
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u8Prescale = (i + 0xFFFF)/ 0x10000;
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// u8Prescale must at least be 2, otherwise the output stop
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if(u8Prescale < 3)
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u8Prescale = 2;
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i /= u8Prescale;
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if(i <= 0x10000) {
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if(i == 1)
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u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
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else
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u16CNR = i;
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break;
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}
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}
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// Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
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i = u32PWM_Clock / (u8Prescale * u8Divider * u16CNR);
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u8Prescale -= 1;
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u16CNR -= 1;
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// convert to real register value
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if(u8Divider == 1)
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u8Divider = 4;
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else if (u8Divider == 2)
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u8Divider = 0;
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else if (u8Divider == 4)
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u8Divider = 1;
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else if (u8Divider == 8)
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u8Divider = 2;
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else // 16
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u8Divider = 3;
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// every two channels share a prescaler
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while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk);
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pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
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pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
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pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
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while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
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if(u32DutyCycle == 0)
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
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else {
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY_CM_Pos);
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}
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
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return(i);
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}
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/**
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* @brief This function config PWM capture and get the nearest unit time
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32UnitTimeNsec Unit time of counter
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* @param[in] u32CaptureEdge Condition to latch the counter
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* @return Nearest unit time in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
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* existing frequency of other channel.
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*/
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uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32UnitTimeNsec,
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uint32_t u32CaptureEdge)
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{
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uint32_t i;
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uint32_t u32ClkSrc;
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uint32_t u32PWM_Clock = SystemCoreClock;
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uint8_t u8Divider = 1, u8Prescale = 0xFF;
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uint16_t u16CNR = 0xFFFF;
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if(pwm == PWM0)
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u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2));
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else
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u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2));
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switch (u32ClkSrc) {
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case 0:
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u32PWM_Clock = __HXT;
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break;
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case 1:
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u32PWM_Clock = __LXT;
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break;
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case 2:
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u32PWM_Clock = SystemCoreClock;
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break;
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case 3:
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u32PWM_Clock = __HIRC12M;
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break;
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}
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for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
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i = ((long long)(u32PWM_Clock / u8Divider) * u32UnitTimeNsec) / 1000000000;
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// If target value is larger than 0xFF, need to use a larger divider
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if(i > (0xFF))
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continue;
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u8Prescale = i;
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// u8Prescale must at least be 2, otherwise the output stop
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if(u8Prescale < 3)
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u8Prescale = 2;
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break;
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}
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// Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
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i = (long long) (u8Prescale * u8Divider) * 1000000000 / u32PWM_Clock;
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u8Prescale -= 1;
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u16CNR -= 1;
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// convert to real register value
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if(u8Divider == 1)
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u8Divider = 4;
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else if (u8Divider == 2)
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u8Divider = 0;
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else if (u8Divider == 4)
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u8Divider = 1;
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else if (u8Divider == 8)
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u8Divider = 2;
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else // 16
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u8Divider = 3;
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// every two channels share a prescaler
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while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk);
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pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
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pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
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pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
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while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
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return(i);
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}
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/**
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* @brief This function start PWM module
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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*/
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void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint8_t i;
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uint32_t u32Mask = 0;
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for (i = 0; i < PWM_CHANNEL_NUM; i++) {
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if ( u32ChannelMask & (1 << i))
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u32Mask |= (PWM_CTL_CH0EN_Msk << (i * 8));
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}
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pwm->CTL |= u32Mask;
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}
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/**
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* @brief This function stop PWM module
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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*/
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void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t i;
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for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
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if(u32ChannelMask & (1 << i)) {
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*(__IO uint32_t *) (&pwm->DUTY0 + 3 * i) &= ~PWM_DUTY_CN_Msk;
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}
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}
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}
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/**
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* @brief This function stop PWM generation immediately by clear channel enable bit
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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*/
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void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t i;
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for (i = 0; i < PWM_CHANNEL_NUM; i++) {
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if ( u32ChannelMask & (1 << i))
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pwm->CTL &= ~(PWM_CTL_CH0EN_Msk << (i * 8));
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}
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}
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/**
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* @brief This function enables PWM capture of selected channels
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
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* @return None
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*/
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void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint8_t i;
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uint32_t u32Mask = 0;
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for (i = 0; i < PWM_CHANNEL_NUM; i++) {
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if ( u32ChannelMask & (1 << i)) {
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u32Mask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
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}
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}
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pwm->CAPCTL |= u32Mask;
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}
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/**
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* @brief This function disables PWM capture of selected channels
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
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* @return None
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*/
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void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint8_t i;
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uint32_t u32CTLMask = 0;
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uint32_t u32CAPCTLMask = 0;
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for (i = 0; i < PWM_CHANNEL_NUM; i++) {
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if ( u32ChannelMask & (1 << i)) {
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u32CTLMask |= (PWM_CTL_CH0EN_Msk << (i * 8));
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u32CAPCTLMask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
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}
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}
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pwm->CTL &= ~u32CTLMask;
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pwm->CAPCTL &= ~u32CAPCTLMask;
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}
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/**
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* @brief This function enables PWM output generation of selected channels
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
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* @return None
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*/
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void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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pwm->OE |= u32ChannelMask;
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}
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/**
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* @brief This function disables PWM output generation of selected channels
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
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* @return None
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*/
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void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
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{
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pwm->OE &= ~u32ChannelMask;
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}
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/**
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* @brief This function enable Dead zone of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
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* dead zone.
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* @return None
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*/
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void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
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{
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// every two channels shares the same setting
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u32ChannelNum >>= 1;
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// set duration
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pwm->PRES = (pwm->PRES & ~(PWM_PRES_DZ01_Msk << (8 * u32ChannelNum))) | ((u32Duration << PWM_PRES_DZ01_Pos ) << (8 * u32ChannelNum));
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// enable dead zone
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pwm->CTL |= (PWM_CTL_DZEN01_Msk << u32ChannelNum);
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}
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/**
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* @brief This function disable Dead zone of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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*/
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void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
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{
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// every two channels shares the same setting
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u32ChannelNum >>= 1;
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// enable dead zone
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pwm->CTL &= ~(PWM_CTL_DZEN01_Msk << u32ChannelNum);
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}
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/**
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* @brief This function enable capture interrupt of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Edge Capture interrupt type. It could be either
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* - \ref PWM_RISING_LATCH_INT_ENABLE
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* - \ref PWM_FALLING_LATCH_INT_ENABLE
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* - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
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* @return None
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*/
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void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
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{
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// enable capture interrupt
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pwm->CAPINTEN |= (u32Edge << (u32ChannelNum * 8));
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}
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/**
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* @brief This function disable capture interrupt of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Edge Capture interrupt type. It could be either
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* - \ref PWM_RISING_LATCH_INT_ENABLE
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* - \ref PWM_FALLING_LATCH_INT_ENABLE
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* - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
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* @return None
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*/
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void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
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{
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// disable capture interrupt
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pwm->CAPINTEN &= ~(u32Edge << (u32ChannelNum * 8));
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}
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/**
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* @brief This function clear capture interrupt flag of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Edge Capture interrupt type. It could be either
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* - \ref PWM_RISING_LATCH_INT_FLAG
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* - \ref PWM_FALLING_LATCH_INT_FLAG
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* - \ref PWM_RISING_FALLING_LATCH_INT_FLAG
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* @return None
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*/
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void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
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{
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// disable capture interrupt flag
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pwm->CAPINTSTS = (u32Edge + 1) << (u32ChannelNum * 8);
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}
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/**
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* @brief This function get capture interrupt flag of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return Capture interrupt flag of specified channel
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* @retval 0 Capture interrupt did not occurred
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* @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred
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* @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred
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* @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred
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*/
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uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
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{
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return ((pwm->CAPINTSTS >> (u32ChannelNum * 8)) & (PWM_RISING_FALLING_LATCH_INT_FLAG));
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}
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/**
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* @brief This function enable period interrupt of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32IntPeriodType This parameter is not used
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* @return None
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* @note All channels share the same period interrupt type setting.
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*/
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void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
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{
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// enable period interrupt
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pwm->INTEN |= (PWM_INTEN_TMIE0_Msk << u32ChannelNum);
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}
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/**
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* @brief This function disable period interrupt of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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*/
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void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
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{
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pwm->INTEN &= ~(PWM_INTEN_TMIE0_Msk << u32ChannelNum);
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}
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/**
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* @brief This function clear period interrupt of selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return None
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*/
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void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
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{
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// write 1 clear
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pwm->INTSTS = (PWM_INTSTS_TMINT0_Msk << u32ChannelNum);
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}
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/**
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* @brief This function get period interrupt of selected channel
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|
* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @return Period interrupt flag of specified channel
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* @retval 0 Period interrupt did not occurred
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* @retval 1 Period interrupt occurred
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*/
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uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
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{
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return ((pwm->INTSTS & (PWM_INTSTS_TMINT0_Msk << u32ChannelNum)) ? 1 : 0);
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}
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/**
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* @brief This function enable capture PDMA of selected channel
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|
* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2
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|
* @param[in] u32RisingFirst Order of captured data transferred by PDMA. It could be either
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* - \ref PWM_CAP_PDMA_RFORDER_R
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|
* - \ref PWM_CAP_PDMA_RFORDER_F
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* @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
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|
* - \ref PWM_RISING_LATCH_PDMA_ENABLE
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|
* - \ref PWM_FALLING_LATCH_PDMA_ENABLE
|
|
* - \ref PWM_RISING_FALLING_LATCH_PDMA_ENABLE
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|
* @return None
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|
*/
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|
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
|
|
{
|
|
if (u32ChannelNum == 0)
|
|
pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD0_Msk | PWM_CAPCTL_CH0RFORDER_Msk)) | u32Mode | u32RisingFirst | PWM_CAPCTL_CH0PDMAEN_Msk;
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|
else
|
|
pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD2_Msk | PWM_CAPCTL_CH2RFORDER_Msk)) | (u32Mode << 16)| (u32RisingFirst << 16)| PWM_CAPCTL_CH2PDMAEN_Msk;
|
|
}
|
|
|
|
/**
|
|
* @brief This function disable capture PDMA of selected channel
|
|
* @param[in] pwm The base address of PWM module
|
|
* @param[in] u32ChannelNum PWM channel number. Valid values are 0 and 2
|
|
* @return None
|
|
*/
|
|
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
|
|
{
|
|
if (u32ChannelNum == 0)
|
|
pwm->CAPCTL &= ~PWM_CAPCTL_CH0PDMAEN_Msk;
|
|
else
|
|
pwm->CAPCTL &= ~PWM_CAPCTL_CH2PDMAEN_Msk;
|
|
}
|
|
|
|
/*@}*/ /* end of group NANO100_PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NANO100_PWM_Driver */
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/*@}*/ /* end of group NANO100_Device_Driver */
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/*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
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