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62 lines
1.8 KiB
Plaintext
62 lines
1.8 KiB
Plaintext
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
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/*
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* Copyright (c) 2020, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "../M451_mem.h"
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#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
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# if defined(MBED_BOOT_STACK_SIZE)
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
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# else
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
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# endif
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#endif
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#define VECTOR_SIZE (4*(16 + 64))
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LR_IROM1 MBED_APP_START MBED_APP_SIZE {
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*(RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_CONF_TARGET_BOOT_STACK_SIZE {
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}
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/* VTOR[TBLOFF] alignment requires:
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*
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* 1. Minumum 32-word
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* 2. Rounding up to the next power of two of table size
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*/
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ER_IRAMVEC AlignExpr(+0, 512) EMPTY VECTOR_SIZE { ; Reserve for vectors
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}
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RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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}
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ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
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ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
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