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446 lines
17 KiB
C
446 lines
17 KiB
C
/***************************************************************************//**
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* \file cyhal_lptimer.c
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*
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* \brief
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* Provides a high level interface for interacting with the Cypress Low-Power Timer.
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* This interface abstracts out the chip specific details. If any chip specific
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* functionality is necessary, or performance is critical the low level functions
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* can be used directly.
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*
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********************************************************************************
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* \copyright
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* Copyright 2018-2021 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*******************************************************************************/
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/**
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* \addtogroup group_hal_impl_lptimer LPTIMER
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* \ingroup group_hal_impl
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* \{
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* The maximum number of ticks that can set to an LPTIMER is 0xFFF0FFFF. It is not recommended to use 0xFFFFFFFF because to avoid both C0 and C1 overflowing.
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* \} group_hal_impl_lptimer
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*/
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#include "cmsis_compiler.h"
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#include "cy_syslib.h"
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#include "cy_sysint.h"
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#include "cyhal_lptimer.h"
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#include "cyhal_hwmgr.h"
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#include "cyhal_system_impl.h"
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#include "cyhal_utils.h"
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#if defined (CY_IP_MXS40SRSS_MCWDT) || (defined (CY_IP_M0S8WCO) && WCO_WDT_EN)
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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#include "cy_mcwdt.h"
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#elif defined (CY_IP_M0S8WCO)
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#include "cy_wdc.h"
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#define Cy_MCWDT_Init Cy_WDC_Init
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#define Cy_MCWDT_DeInit Cy_WDC_DeInit
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#define Cy_MCWDT_Enable Cy_WDC_Enable
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#define Cy_MCWDT_Disable Cy_WDC_Disable
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#define Cy_MCWDT_ClearInterrupt Cy_WDC_ClearInterrupt
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#define Cy_MCWDT_GetCount Cy_WDC_GetCount
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#define Cy_MCWDT_SetMatch Cy_WDC_SetMatch
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#define Cy_MCWDT_GetMatch Cy_WDC_GetMatch
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#define Cy_MCWDT_ResetCounters Cy_WDC_ResetCounters
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#define CY_MCWDT_COUNTER0 CY_WDC_COUNTER0
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#define CY_MCWDT_COUNTER1 CY_WDC_COUNTER1
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#define CY_MCWDT_COUNTER2 CY_WDC_COUNTER2
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#define CY_MCWDT_CTR0 CY_WDC_COUNTER0_Msk
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#define CY_MCWDT_CTR1 CY_WDC_COUNTER1_Msk
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#define CY_MCWDT_CTR2 CY_WDC_COUNTER2_Msk
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#define srss_interrupt_mcwdt_0_IRQn wco_interrupt_IRQn
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#else
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#error "Current HW block is not supported"
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#endif
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#if defined (CY_IP_MXS40SRSS_MCWDT_INSTANCES)
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static MCWDT_STRUCT_Type * const _CYHAL_LPTIMER_BASE_ADDRESSES[] = {
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#if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 1
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MCWDT_STRUCT0,
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#endif
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#if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 2
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MCWDT_STRUCT1,
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#endif
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#if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 3
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#error "CY_IP_MXS40SRSS_MCWDT_INSTANCES > 2 not supported"
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#endif
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};
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#elif defined (CY_IP_M0S8WCO_INSTANCES)
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static WCO_Type * const _CYHAL_LPTIMER_BASE_ADDRESSES[] = {
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#if CY_IP_M0S8WCO_INSTANCES >= 1
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WCO,
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#endif
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#if CY_IP_M0S8WCO_INSTANCES >= 2
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#error "CY_IP_M0S8WCO_INSTANCES > 1 not supported"
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#endif
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};
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#else
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#error "Current HW block is not supported"
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#endif
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#define _CYHAL_LPTIMER_CTRL (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2)
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#define _CYHAL_LPTIMER_MIN_DELAY (3U) /* minimum amount of lfclk cycles of that LPTIMER can delay for. */
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#define _CYHAL_LPTIMER_MAX_DELAY_TICKS (0xfff0ffffUL) /* ~36hours, Not set to 0xffffffff to avoid C0 and C1 both overflowing */
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#define _CYHAL_LPTIMER_MAX_COUNTER_VAL (0xffffffffUL) /* Maximum value of the counter before it rolls over */
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#define _CYHAL_LPTIMER_DEFAULT_PRIORITY (3U)
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/* For all CAT1/CAT2 device the MCWDT is driven by CLK_LF that will always run at 32.768 KHz */
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#define _CYHAL_LPTIMER_CLK_FREQ_HZ (32768U)
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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static cyhal_lptimer_t *_cyhal_lptimer_config_structs[CY_IP_MXS40SRSS_MCWDT_INSTANCES];
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static const uint16_t _CYHAL_LPTIMER_RESET_TIME_US = 62;
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static const uint16_t _CYHAL_LPTIMER_SETMATCH_TIME_US = 0;
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#elif defined (CY_IP_M0S8WCO)
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static cyhal_lptimer_t *_cyhal_lptimer_config_structs[CY_IP_M0S8WCO_INSTANCES];
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static const uint16_t _CYHAL_LPTIMER_RESET_TIME_US = 180;
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static const uint16_t _CYHAL_LPTIMER_SETMATCH_TIME_US = 180;
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#else
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#error "Current HW block is not supported"
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#endif
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static void _cyhal_lptimer_irq_handler(void)
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{
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uint32_t instance = (uint32_t)_CYHAL_UTILS_GET_CURRENT_IRQN() - (uint32_t) srss_interrupt_mcwdt_0_IRQn;
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cyhal_lptimer_t *obj = _cyhal_lptimer_config_structs[instance];
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Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2);
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/* Clear interrupt mask if set only from cyhal_lptimer_set_delay() function */
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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if (obj->clear_int_mask)
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{
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Cy_MCWDT_SetInterruptMask(obj->base, 0);
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}
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#endif
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if (NULL != obj->callback_data.callback)
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{
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cyhal_lptimer_event_callback_t callback = (cyhal_lptimer_event_callback_t) obj->callback_data.callback;
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(callback)(obj->callback_data.callback_arg, CYHAL_LPTIMER_COMPARE_MATCH);
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}
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}
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static uint32_t _cyhal_lptimer_set_delay_common(cyhal_lptimer_t *obj, uint32_t delay)
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{
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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if ((Cy_MCWDT_GetEnabledStatus(obj->base,CY_MCWDT_COUNTER0) == 0UL)
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|| (Cy_MCWDT_GetEnabledStatus(obj->base,CY_MCWDT_COUNTER1) == 0UL)
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|| (Cy_MCWDT_GetEnabledStatus(obj->base,CY_MCWDT_COUNTER2) == 0UL))
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{
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return CYHAL_LPTIMER_RSLT_ERR_DISABLED;
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}
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#elif defined (CY_IP_M0S8WCO)
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if ((Cy_WDC_GetEnabledStatus(obj->base,CY_WDC_COUNTER0) == 0UL)
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|| (Cy_WDC_GetEnabledStatus(obj->base,CY_WDC_COUNTER1) == 0UL)
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|| (Cy_WDC_GetEnabledStatus(obj->base,CY_WDC_COUNTER2) == 0UL))
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{
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return CYHAL_LPTIMER_RSLT_ERR_DISABLED;
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}
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#endif
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/**
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* 16 bit C0/C1 are cascaded to generated a 32 bit counter.
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* Counter0 continues counting after reaching its match value
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* Interrupt is generated on Counter1 match.
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*
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* Supposed T=C0=C1=0, and we need to trigger an interrupt at T=0x28000.
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* We set C0_match to 0x8000 and C1 match to 1.
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* At T = 0x8000, C0_value matches C0_match so C1 get incremented. C1/C0=0x18000.
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* At T = 0x18000, C0_value matches C0_match again so C1 get incremented from 1 to 2.
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* When C1 get incremented from 1 to 2 theinterrupt is generated.
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* At T = 0x18000, C1/C0 = 0x28000.
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*/
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if (delay <= _CYHAL_LPTIMER_MIN_DELAY)
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{
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delay = _CYHAL_LPTIMER_MIN_DELAY;
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}
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if (delay > _CYHAL_LPTIMER_MAX_DELAY_TICKS)
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{
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delay = _CYHAL_LPTIMER_MAX_DELAY_TICKS;
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}
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uint16_t c0_increment = (uint16_t)delay;
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uint16_t c1_increment = (uint16_t)(delay >> 16);
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Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1);
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uint16_t c0_old_match = (uint16_t)Cy_MCWDT_GetMatch(obj->base, CY_MCWDT_COUNTER0);
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uint32_t critical_section = cyhal_system_critical_section_enter();
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/* Cascading from C0 match into C1 is queued and can take 1 full LF clk cycle.
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* There are 3 cases:
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* Case 1: if c0 = match0 then the cascade into C1 will happen 1 cycle from now. The value c1_current_ticks is 1 lower than expected.
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* Case 2: if c0 = match0 -1 then cascade may or not happen before new match value would occur. Match occurs on rising clock edge.
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* Synching match value occurs on falling edge. Wait until c0 = match0 to ensure cascade occurs.
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* Case 3: everything works as expected.
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*
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* Note: timeout is needed here just in case the LFCLK source gives out. This avoids device lockup.
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*
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* ((2 * Cycles_LFClk) / Cycles_cpu_iteration) * (HFCLk_max / LFClk_min) = Iterations_required
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* Typical case: (2 / 100) * ((150x10^6)/33576) = 89 iterations
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* Worst case: (2 / 100) * ((150x10^6)/1) = 3x10^6 iterations
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* Compromise: (2 / 100) * ((150x10^6)/0xFFFF iterations) = 45 Hz = LFClk_min
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*/
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uint32_t timeout=0xFFFFUL;
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uint16_t c0_current_ticks = (uint16_t)Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0);
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// Wait until the cascade has definitively happened. It takes a clock cycle for the cascade to happen, and potentially another a full
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// LFCLK clock cycle for the cascade to propagate up to the HFCLK-domain registers that the CPU reads.
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while ((((uint16_t)(c0_old_match - 1)) == c0_current_ticks ||
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c0_old_match == c0_current_ticks ||
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((uint16_t)(c0_old_match + 1)) == c0_current_ticks) && timeout != 0UL)
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{
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c0_current_ticks = (uint16_t)Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0);
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timeout--;
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}
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if (timeout == 0UL)
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{
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// Timeout has occured. There could have been a clock failure while waiting for the count value to update.
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cyhal_system_critical_section_exit(critical_section);
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return CYHAL_LPTIMER_RSLT_ERR_DISABLED;
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}
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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uint16_t c1_current_ticks = (uint16_t)Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1);
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Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_current_ticks + c0_increment, _CYHAL_LPTIMER_SETMATCH_TIME_US);
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Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_current_ticks + c1_increment, _CYHAL_LPTIMER_SETMATCH_TIME_US);
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#elif defined (CY_IP_M0S8WCO)
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/* Set interrupt mask is not supported on current HW block.
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Instead separate timers can generate self interrupt on clear on match event.
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In this case interrupt from counter 1 is enabled counter 0 is disable
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For example: To get interupt from lp_timer after 100 counts. Set counter1=1, counter0=(100 counts)
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To get interupt from lp_timer after 0x11170 counts. Set counter1=0xF, counter0=0x1170 */
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if (!c1_increment)
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{
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c1_increment = 1;
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}
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else
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{
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c1_increment = c1_increment + (0xFFFF / c0_increment);
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}
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Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_increment, _CYHAL_LPTIMER_SETMATCH_TIME_US);
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Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_increment, _CYHAL_LPTIMER_SETMATCH_TIME_US);
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#else
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#error "Current HW block is not supported"
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#endif
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cyhal_system_critical_section_exit(critical_section);
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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Cy_MCWDT_SetInterruptMask(obj->base, CY_MCWDT_CTR1);
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#endif
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return CY_RSLT_SUCCESS;
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}
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cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj)
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{
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CY_ASSERT(NULL != obj);
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obj->resource.type = CYHAL_RSC_INVALID;
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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obj->clear_int_mask = false;
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#endif
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cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_LPTIMER, &(obj->resource));
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if (CY_RSLT_SUCCESS == rslt)
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{
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obj->base = _CYHAL_LPTIMER_BASE_ADDRESSES[obj->resource.block_num];
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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const cy_stc_mcwdt_config_t cfg = {
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.c0Match = 0xFFFF,
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.c1Match = 0xFFFF,
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.c0Mode = CY_MCWDT_MODE_INT,
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.c1Mode = CY_MCWDT_MODE_INT,
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.c2Mode = CY_MCWDT_MODE_NONE,
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.c2ToggleBit = 0,
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.c0ClearOnMatch = false,
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.c1ClearOnMatch = false,
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.c0c1Cascade = true,
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.c1c2Cascade = false
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};
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rslt = (cy_rslt_t) Cy_MCWDT_Init(obj->base, &cfg);
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#elif defined (CY_IP_M0S8WCO)
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// The WDC_SEL clock source is populated into the config
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// register by the clock driver. Extract it so that the
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// PDL init doesn't revert it to default
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cy_en_wdc_clock_t clock_source = Cy_WDC_GetClockSource(WCO);
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const cy_stc_wdc_config_t cfg = {
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.counter0Match = 0xFFFF,
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.counter1Match = 0xFFFF,
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.counter2ToggleBit = 0,
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.counter0Interrupt = false,
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.counter1Interrupt = true,
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.counter2Interrupt = false,
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.counter0ClearOnMatch = true,
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.counter1ClearOnMatch = true,
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.countersCascade = CY_WDC_CASCADE_COUNTERS01,
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.clockSource = clock_source
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};
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rslt = (cy_rslt_t) Cy_WDC_Init(obj->base, &cfg);
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#else
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#error "Current HW block is not supported"
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#endif
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}
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if (CY_RSLT_SUCCESS == rslt)
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{
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obj->callback_data.callback = NULL;
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obj->callback_data.callback_arg = NULL;
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_cyhal_lptimer_config_structs[obj->resource.block_num] = obj;
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}
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if (CY_RSLT_SUCCESS == rslt)
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{
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IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
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cy_stc_sysint_t irqCfg = { irqn, _CYHAL_LPTIMER_DEFAULT_PRIORITY };
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rslt = (cy_rslt_t) Cy_SysInt_Init(&irqCfg, _cyhal_lptimer_irq_handler);
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if (CY_RSLT_SUCCESS == rslt)
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{
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NVIC_EnableIRQ(irqn);
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Cy_MCWDT_Enable(obj->base, _CYHAL_LPTIMER_CTRL, _CYHAL_LPTIMER_RESET_TIME_US);
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}
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}
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if (CY_RSLT_SUCCESS != rslt)
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{
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cyhal_lptimer_free(obj);
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}
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return rslt;
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}
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void cyhal_lptimer_free(cyhal_lptimer_t *obj)
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{
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if (CYHAL_RSC_INVALID != obj->resource.type)
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{
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IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
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NVIC_DisableIRQ(irqn);
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cyhal_hwmgr_free(&(obj->resource));
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obj->resource.type = CYHAL_RSC_INVALID;
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}
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if (NULL != obj->base)
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{
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Cy_MCWDT_Disable(obj->base, _CYHAL_LPTIMER_CTRL, _CYHAL_LPTIMER_RESET_TIME_US);
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// When we're using the WDC, the clock source selection is stored in the WDC_CONFIG
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// register and we want that to persist across free/init calls. So don't call deinit
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// because that will clear it out.
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#if !defined(CY_IP_M0S8WCO)
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Cy_MCWDT_DeInit(obj->base);
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#endif
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obj->base = NULL;
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}
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}
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cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj)
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{
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Cy_MCWDT_ResetCounters(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2), 2 * _CYHAL_LPTIMER_RESET_TIME_US);
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return CY_RSLT_SUCCESS;
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}
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cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t ticks)
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{
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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obj->clear_int_mask = false;
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#endif
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return _cyhal_lptimer_set_delay_common(obj, ticks - cyhal_lptimer_read(obj));
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}
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cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay)
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{
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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obj->clear_int_mask = true;
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return _cyhal_lptimer_set_delay_common(obj, delay);
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#else
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CY_UNUSED_PARAMETER(obj);
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CY_UNUSED_PARAMETER(delay);
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return CYHAL_LPTIMER_RSLT_ERR_NOT_SUPPORTED;
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#endif
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}
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uint32_t cyhal_lptimer_read(const cyhal_lptimer_t *obj)
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{
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return Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER2);
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}
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void cyhal_lptimer_register_callback(cyhal_lptimer_t *obj, cyhal_lptimer_event_callback_t callback, void *callback_arg)
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{
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CY_ASSERT(CYHAL_RSC_INVALID != obj->resource.block_num);
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uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
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obj->callback_data.callback = (cy_israddress) callback;
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obj->callback_data.callback_arg = callback_arg;
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cyhal_system_critical_section_exit(savedIntrStatus);
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}
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void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t event, uint8_t intr_priority, bool enable)
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{
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CY_UNUSED_PARAMETER(event);
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CY_ASSERT(event == CYHAL_LPTIMER_COMPARE_MATCH);
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IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
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Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1);
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#if defined (CY_IP_MXS40SRSS_MCWDT)
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Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR1 : 0);
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NVIC_SetPriority(irqn, intr_priority);
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#elif defined (CY_IP_M0S8WCO)
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if (enable)
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{
|
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NVIC_SetPriority(irqn, intr_priority);
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NVIC_EnableIRQ(irqn);
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}
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else
|
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{
|
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NVIC_DisableIRQ(irqn);
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}
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#else
|
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#error "Current HW block is not supported"
|
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#endif
|
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}
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void cyhal_lptimer_irq_trigger(cyhal_lptimer_t *obj)
|
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{
|
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CY_ASSERT(CYHAL_RSC_INVALID != obj->resource.block_num);
|
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cyhal_lptimer_event_callback_t callback = (cyhal_lptimer_event_callback_t) obj->callback_data.callback;
|
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(callback)(obj->callback_data.callback_arg, CYHAL_LPTIMER_COMPARE_MATCH);
|
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}
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|
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void cyhal_lptimer_get_info(cyhal_lptimer_t *obj, cyhal_lptimer_info_t *info)
|
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{
|
|
CY_UNUSED_PARAMETER(obj);
|
|
CY_ASSERT(info != NULL);
|
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|
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info->frequency_hz = _CYHAL_LPTIMER_CLK_FREQ_HZ;
|
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info->min_set_delay = _CYHAL_LPTIMER_MIN_DELAY;
|
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info->max_counter_value = _CYHAL_LPTIMER_MAX_COUNTER_VAL;
|
|
}
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* defined (CY_IP_MXS40SRSS_MCWDT) || (defined (CY_IP_M0S8WCO) && WCO_WDT_EN) */
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