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101 lines
3.2 KiB
C
101 lines
3.2 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2015-2016 Nuvoton
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "cmsis.h"
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#include "analogin_api.h"
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void mbed_sdk_init(void)
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{
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// NOTE: Support singleton semantics to be called from other init functions
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static int inited = 0;
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if (inited) {
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return;
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}
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inited = 1;
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/*---------------------------------------------------------------------------------------------------------*/
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/* Init System Clock */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Unlock protected registers */
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SYS_UnlockReg();
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#if MBED_CONF_TARGET_HXT_PRESENT
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/* Enable External XTAL (4~24 MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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#else
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/* Disable External XTAL (4~24 MHz) */
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CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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#endif
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/* Enable LIRC */
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CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
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#if MBED_CONF_TARGET_LXT_PRESENT
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/* Enable LXT */
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CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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#else
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/* Disable LXT */
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CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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#endif
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#if MBED_CONF_TARGET_HXT_PRESENT
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/* Waiting for External XTAL (4~24 MHz) ready */
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CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
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#endif
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/* Waiting for LIRC ready */
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CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
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#if MBED_CONF_TARGET_LXT_PRESENT
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/* Waiting for LXT ready */
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CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
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#endif
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#if MBED_CONF_TARGET_HXT_PRESENT
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/* Switch HCLK clock source to HXT */
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CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
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#else
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/* Switch HCLK clock source to HIRC */
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CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC,CLK_CLKDIV0_HCLK(1));
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#endif
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/* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/
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CLK->PLLCTL|= CLK_PLLCTL_PD_Msk;
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/* Set PLL frequency */
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#if MBED_CONF_TARGET_HXT_PRESENT
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CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
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#else
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CLK->PLLCTL = CLK_PLLCTL_50MHz_HIRC;
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#endif
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/* Waiting for clock ready */
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CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
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/* Switch HCLK clock source to PLL */
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CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
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#if DEVICE_ANALOGIN
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/* Vref connect to AVDD */
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SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
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/* Switch ADC0 to EADC mode */
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SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_ADCMODESEL_Msk) | SYS_VREFCTL_ADCMODESEL_EADC;
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#endif
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/* Update System Core Clock */
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/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
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SystemCoreClockUpdate();
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/* Lock protected registers */
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SYS_LockReg();
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}
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